October 2018 - U-Boot

[U-Boot] [PATCH] QSPI flash driver compatibility fixes for mx6ull
by Neil Stainton 28 Jan '19

28 Jan '19

Avoid "SF: Timeout!" messages and generally speed up QSPI flash operations on mx6ull EVK by adding a QSPI sequence for reading "flag status register" as required for some (ST/Micron) NOR flash devices by the DM spi-flash driver. Enable QSPI clock in EVK specific board_init function, as per other Freescale EVKs. Tested on mcimx6ull EVK, U303 populated with a Micron MT25QL256ABA (ID reads as 'n25q256'). Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Jagan Teki <jagan(a)openedev.com> Signed-off-by: Neil Stainton <nstainton(a)asl-control.co.uk> --- arch/arm/dts/imx6ull-14x14-evk.dts | 2 +- board/freescale/mx6ullevk/mx6ullevk.c | 15 +++++++++++++++ drivers/mtd/spi/spi_flash.c | 4 ++-- drivers/spi/fsl_qspi.c | 24 +++++++++++++++++++----- 4 files changed, 37 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts index 8a1b67d..7cb6d16 100644 --- a/arch/arm/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -454,10 +454,10 @@ flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; - /* compatible = "micron,n25q256a"; */ compatible = "spi-flash"; spi-max-frequency = <29000000>; spi-nor,ddr-quad-read-dummy = <6>; + memory-map = <0x60000000 0x02000000>; reg = <0>; }; }; diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index ad83f36..46d61bc 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -58,11 +58,26 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_FSL_QSPI +static int board_qspi_init(void) +{ + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif /* !defined(CONFIG_FSL_QSPI) */ + int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_FSL_QSPI + /* Set the clock */ + board_qspi_init(); +#endif + return 0; } diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index c159124..c817772 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -360,7 +360,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) } #ifdef CONFIG_SPI_FLASH_BAR - ret = clean_bar(flash); + clean_bar(flash); #endif return ret; @@ -422,7 +422,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, } #ifdef CONFIG_SPI_FLASH_BAR - ret = clean_bar(flash); + clean_bar(flash); #endif return ret; diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 1598c4f..07c3ade 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -47,10 +47,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif #define SEQID_WRAR 13 #define SEQID_RDAR 14 +#define SEQID_RDFSR 15 /* QSPI CMD */ #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ #define QSPI_CMD_RDSR 0x05 /* Read status register */ +#define QSPI_CMD_RDFSR 0x70 /* Read flag status register */ #define QSPI_CMD_WREN 0x06 /* Write enable */ #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ #define QSPI_CMD_BE_4K 0x20 /* 4K erase */ @@ -230,6 +232,15 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); + /* Read Flag Status */ + lut_base = SEQID_RDFSR * 4; + qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDFSR) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0); + qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0); + /* Erase a sector */ lut_base = SEQID_SE * 4; #ifdef CONFIG_SPI_FLASH_BAR @@ -698,7 +709,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) qspi_write32(priv->flags, &regs->mcr, mcr_reg); } -static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) +static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len, u8 seqid) { struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg, reg, data; @@ -712,7 +723,7 @@ static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len) qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base); qspi_write32(priv->flags, &regs->ipcr, - (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0); + (seqid << QSPI_IPCR_SEQID_SHIFT) | 0); while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK) ; @@ -815,10 +826,13 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, #endif } else if (priv->cur_seqid == QSPI_CMD_RDAR) { qspi_op_read(priv, din, bytes); - } else if (priv->cur_seqid == QSPI_CMD_RDID) + } else if (priv->cur_seqid == QSPI_CMD_RDID) { qspi_op_rdid(priv, din, bytes); - else if (priv->cur_seqid == QSPI_CMD_RDSR) - qspi_op_rdsr(priv, din, bytes); + } else if (priv->cur_seqid == QSPI_CMD_RDSR) { + qspi_op_rdsr(priv, din, bytes, SEQID_RDSR); + } else if (priv->cur_seqid == QSPI_CMD_RDFSR) { + qspi_op_rdsr(priv, din, bytes, SEQID_RDFSR); + } #ifdef CONFIG_SPI_FLASH_BAR else if ((priv->cur_seqid == QSPI_CMD_BRRD) || (priv->cur_seqid == QSPI_CMD_RDEAR)) { -- 2.7.4

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[U-Boot] [PATCH 0/3] Support for the Aspeed ast2500 FMC/SPI controllers
by Cédric Le Goater 26 Jan '19

26 Jan '19

Hello, This series adds a driver for the Aspeed ast2500 FMC/SPI controllers as one can find on the POWER9 OpenPOWER platforms. It was tested on the AST2500 evb using a w25q256 flash device. Git tree available here: https://github.com/legoater/u-boot/commits/aspeed Thanks, C. Cédric Le Goater (3): aspeed: ast2500: Add AHB clock spi: Add support for the Aspeed ast2500 SPI controllers aspeed: Add SPI support to the ast2500 Eval Board .../arm/include/asm/arch-aspeed/scu_ast2500.h | 2 + arch/arm/include/asm/arch-aspeed/spi.h | 114 +++ include/dt-bindings/clock/ast2500-scu.h | 1 + drivers/clk/aspeed/clk_ast2500.c | 12 + drivers/spi/aspeed_spi.c | 788 ++++++++++++++++++ arch/arm/dts/ast2500-evb.dts | 17 + arch/arm/dts/ast2500-u-boot.dtsi | 12 + arch/arm/dts/ast2500.dtsi | 71 ++ configs/evb-ast2500_defconfig | 10 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + 11 files changed, 1036 insertions(+) create mode 100644 arch/arm/include/asm/arch-aspeed/spi.h create mode 100644 drivers/spi/aspeed_spi.c -- 2.17.1

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[U-Boot] [PATCH 1/2] AQUANTIA USXGMII autoneg enable
by Valentin-catalin Neacsu 24 Jan '19

24 Jan '19

If System interface protocol is USXGMII then enable USXGMII autoneg Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu(a)nxp.com> --- drivers/net/phy/aquantia.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 6678147545..603abb5a7f 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #include <config.h> #include <common.h> @@ -20,6 +21,13 @@ #define AQUNTIA_SPEED_LSB_MASK 0x2000 #define AQUNTIA_SPEED_MSB_MASK 0x40 +#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812 +#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441 + +#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008 +#define AQUANTIA_SI_IN_USE_MASK 0x0078 +#define AQUANTIA_SI_USXGMII 0x0018 + int aquantia_config(struct phy_device *phydev) { u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); @@ -41,6 +49,16 @@ int aquantia_config(struct phy_device *phydev) phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, AQUNTIA_SPEED_LSB_MASK | AQUNTIA_SPEED_MSB_MASK); + + val = phy_read(phydev, MDIO_MMD_PHYXS, + AQUANTIA_SYSTEM_INTERFACE_SR); + /* If SI is USXGMII then start USXGMII autoneg*/ + if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) { + phy_write(phydev, MDIO_MMD_PHYXS, + AQUANTIA_VENDOR_PROVISIONING_REG, + AQUANTIA_USX_AUTONEG_CONTROL_ENA); + } + } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { /* 2.5GBASE-T mode */ phydev->advertising = SUPPORTED_1000baseT_Full; -- 2.17.1

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[U-Boot] [PATCH 0/4] Topic board support updates
by Mike Looijmans 22 Jan '19

22 Jan '19

There have been hardware changes to a few topic-miami boards, these are included in these commits (the production version of the "lite" became cheaper, the "plus" was made faster). Also improvements for usability. @Michal: These also apply cleanly to u-boot-xlnx, it'd be great if they could be included there as well. Mike Looijmans (4): topic-miamiplus: Run CPU at 800MHz for speedgrade-2 board: topic_miamilite: Support cost-reduced version configs/topic_miami.h: Use same partitioning for USB boot as for SD board: topic-miamiplus: Run IO PLL at 1000 MHz arch/arm/dts/zynq-topic-miamilite.dts | 7 +++-- arch/arm/dts/zynq-topic-miamiplus.dts | 9 ++++++ .../topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 14 ++++----- board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt | 14 ++++----- .../topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 34 ++++++++++------------ include/configs/topic_miami.h | 19 +++++++----- include/configs/topic_miamilite.h | 11 +++++++ 7 files changed, 65 insertions(+), 43 deletions(-) create mode 100644 include/configs/topic_miamilite.h -- 1.9.1

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[U-Boot] re-use dm data for pre-relocate and post-relocate
by Kever Yang 21 Jan '19

21 Jan '19

Hi Simon, In order to make people easier to maintain a U-Boot for product, we want to re-use the dtb from kernel. Some peripheral like power/pmic and display panel, key, charger which need work in U-Boot and may different in different product, we want to make people only maintain kernel dts, but not one more U-Boot project for all these devices. I want to do this just around the relocate, need to read dtb from storage like emmc/nand/spi, and then use a new dtb for initr_dm after relocate. Here are issues I have met: - The kernel dts may not have a stdout in chosen, we may use earlycon, earlyprintk instead; this lead to U-Boot can not find a serial driver after relocate; - no alias for mmc device which is need by U-Boot but not used in kernel; - not able to init mmc driver twice with current driver; mmc driver not able to work before relocate, no bss for (static int initialized), and hang even if I skip this; mmc driver can init and read dtb before initr_dm, but not able to init again after initr_dm. In fact, I don't think we have to re-init serial driver and mmc driver, and most other driver which need pre-relocate like clock, the only driver I have seem have different use in pre-relocate and post-relocate is video driver(no idea why it have to be pre-relocate, we always have display very late), can we add a tag for re-use the dm driver data for those with pre-relocate ? Thanks, - Kever

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[U-Boot] [PATCH 0/9] Support 4GB of memory on 32bit systems
by Philipp Tomsich 19 Jan '19

19 Jan '19

Even on 32bit systems a full 4GB of DRAM may be installed and reported by the DRAM controller. Whether these 4GB are larger available depends on the size/configuration of address decoding windows and architectural features. This increases the fields holding the RAM size to have at least 33bits (i.e. we use a u64) and fixes the fallout from the change: some casts, the usage of min() and a few printf formats have to be adjusted. Philipp Tomsich (9): dm: allow 4GB of DRAM on 32bit systems rockchip: support 4GB DRAM on 32bit systems common: include <inttypes.h> always MIPS: use PRIx64 macros for printing ram size rockchip: rk3368: change type of ram-size field for a min()-calculation ram: stm32mp1: use PRIx64 macros for printing ram size board: keymile: add explicit cast to truncate the 64bit ram size field board: cm_fx6: use PRIx64 macros for printing ram size mpc85xx: add casts for ram size in min() calculation. arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 +- arch/arm/mach-rockchip/sdram_common.c | 8 ++++---- arch/arm/mach-stm32mp/dram_init.c | 2 +- arch/mips/mach-bmips/dram.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 6 ++++-- board/compulab/cm_fx6/cm_fx6.c | 3 ++- board/keymile/km_arm/km_arm.c | 6 ++++-- drivers/ram/rockchip/dmc-rk3368.c | 2 +- drivers/ram/stm32mp1/stm32mp1_ram.c | 2 +- include/asm-generic/global_data.h | 2 +- include/common.h | 1 + include/ram.h | 9 ++++++++- 12 files changed, 29 insertions(+), 16 deletions(-) -- 2.1.4

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[U-Boot] [PATCH] [RFC] blk: Increase cache element size
by Marek Vasut 16 Jan '19

16 Jan '19

Cache up to 4 kiB entries. 4 kiB is the default block size on ext4, yet the underlying block layer devices usually report support for 512B . In most cases, the 512B support is emulated (ie. SD cards, SSDs, USB sticks etc.) and the real block size of those devices is much bigger. To avoid performance degradation with such devices and FS setup, bump the maximum cache entry size to 4 kiB. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/block/blkcache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c index 294511fcdb..1fa64989d3 100644 --- a/drivers/block/blkcache.c +++ b/drivers/block/blkcache.c @@ -24,7 +24,7 @@ struct block_cache_node { static LIST_HEAD(block_cache); static struct block_cache_stats _stats = { - .max_blocks_per_entry = 2, + .max_blocks_per_entry = 8, .max_entries = 32 }; -- 2.16.2

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[U-Boot] [PATCH 0/4] net: dm: fec: Fixes and improvements
by Martin Fuzzey 15 Jan '19

15 Jan '19

A few fixes and improvements for the FEC driver. They are functionally independent but included in a series to avoid conflicts if merged out of order as they touch the same files. Martin Fuzzey (4): net: dm: fec: Fix time unit error in phy-reset-duration net: dm: fec: Fix phy-reset-duration clamping and defaults net: dm: fec: Support the phy-supply binding net: dm: fec: Obtain the transceiver type from the DT drivers/net/fec_mxc.c | 60 ++++++++++++++++++++++++++++++++++++++++----------- drivers/net/fec_mxc.h | 3 +++ 2 files changed, 51 insertions(+), 12 deletions(-) -- 1.9.1

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[U-Boot] BPI-M2 Magic: DRAM:Timeout initialising DRAM
by Jagan Teki 10 Jan '19

10 Jan '19

Hi, Anyone find this dram timeout issue with BPI-M2 Magic Log: U-Boot SPL 2018.05-00294-g855ff8e6dd (May 21 2018 - 22:27:49 +0530) DRAM:Timeout initialising DRAM resetting ... Look like dram fex values seems ok, any inputs? [1] https://github.com/BPI-SINOVOIP/BPI-M2M-bsp/blob/master/sunxi-pack/allwinne… Jagan. -- Jagan Teki Senior Linux Kernel Engineer | Amarula Solutions U-Boot, Linux | Upstream Maintainer Hyderabad, India.

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[U-Boot] [PATCH] spl: fix the new position of gd and stack
by Peng Donglin 27 Dec '18

27 Dec '18

If we enable CONFIG_SPL_SYS_MALLOC_SIMPLE and set CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN, the new gd and stack will inside malloc area,so there is a overwrite risk. We can place the new position of gd and stack under the malloc area to fix this issue. Signed-off-by: Peng Donglin <dolinux.peng(a)gmail.com> --- common/spl/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/spl.c b/common/spl/spl.c index 292e659c9a..e85a153869 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -628,7 +628,7 @@ ulong spl_relocate_stack_gd(void) } #endif /* Get stack position: use 8-byte alignment for ABI compliance */ - ptr = CONFIG_SPL_STACK_R_ADDR - roundup(sizeof(gd_t),16); + ptr -= roundup(sizeof(gd_t), 16); new_gd = (gd_t *)ptr; memcpy(new_gd, (void *)gd, sizeof(gd_t)); #if CONFIG_IS_ENABLED(DM) -- 2.17.1

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