October 2018 - U-Boot

[U-Boot] [PATCH v2] efi_loader: Align runtime section to 64kb
by Alexander Graf 09 Dec '18

09 Dec '18

The UEFI spec mandates that runtime sections are 64kb aligned to enable support for 64kb page size OSs. This patch ensures that we extend the runtime section to 64kb to be spec compliant. Signed-off-by: Alexander Graf <agraf(a)suse.de> --- v1 -> v2: - rename kb to KiB in accordance to the spec - add reference to spec section for alignment requirement - only use 64KiB alignment on aarch64 --- lib/efi_loader/efi_memory.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 5bd4f4d7fc..b4cb543275 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -11,6 +11,7 @@ #include <mapmem.h> #include <watchdog.h> #include <linux/list_sort.h> +#include <linux/sizes.h> DECLARE_GLOBAL_DATA_PTR; @@ -563,6 +564,7 @@ __weak void efi_add_known_memory(void) static void add_u_boot_and_runtime(void) { unsigned long runtime_start, runtime_end, runtime_pages; + unsigned long runtime_mask = EFI_PAGE_MASK; unsigned long uboot_start, uboot_pages; unsigned long uboot_stack_size = 16 * 1024 * 1024; @@ -571,10 +573,22 @@ static void add_u_boot_and_runtime(void) uboot_pages = (gd->ram_top - uboot_start) >> EFI_PAGE_SHIFT; efi_add_memory_map(uboot_start, uboot_pages, EFI_LOADER_DATA, false); - /* Add Runtime Services */ - runtime_start = (ulong)&__efi_runtime_start & ~EFI_PAGE_MASK; +#if defined(__aarch64__) + /* + * Runtime Services must be 64KiB aligned according to the + * "AArch64 Platforms" section in the UEFI spec (2.7+). + */ + + runtime_mask = SZ_64K - 1; +#endif + + /* + * Add Runtime Services. We mark surrounding boottime code as runtime as + * well to fulfill the runtime alignment constraints but avoid padding. + */ + runtime_start = (ulong)&__efi_runtime_start & ~runtime_mask; runtime_end = (ulong)&__efi_runtime_stop; - runtime_end = (runtime_end + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; + runtime_end = (runtime_end + runtime_mask) & ~runtime_mask; runtime_pages = (runtime_end - runtime_start) >> EFI_PAGE_SHIFT; efi_add_memory_map(runtime_start, runtime_pages, EFI_RUNTIME_SERVICES_CODE, false); -- 2.12.3

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[U-Boot] [PATCH 0/3] Small fixes for Olimex MX23 based Olinuxino boards
by Michael Heimpold 08 Dec '18

08 Dec '18

Testing of v2018.11-rc2 on this board uncovered three small "issues" I would like to see fixed. See individual patch descriptions for details. Michael Heimpold (3): configs: drop CMD_CACHE from mx23_olinuxino_defconfig configs: mx23_olinuxino_defconfig: fix status led definition configs: mx23_olinuxino_defconfig: disable bootefi command configs/mx23_olinuxino_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1

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[U-Boot] [PATCH] w1: Add driver for i.MX bus master controller
by Martin Fuzzey 08 Dec '18

08 Dec '18

Two variants of controllers are supported: V1 (bitwise only) found in i.MX21, i.MX27, i.MX31, i.MX51 V2 (byte operations) found in i.MX25, i.MX35, i.MX50, i.MX53 Only tested on i.MX53 hardware but in both modes (by modifying the device tree). Signed-off-by: Martin Fuzzey <martin.fuzzey(a)flowbird.group> --- doc/device-tree-bindings/w1/mxc-w1.txt | 37 ++++++ drivers/w1/Kconfig | 14 ++ drivers/w1/Makefile | 1 + drivers/w1/mxc_w1.c | 232 +++++++++++++++++++++++++++++++++ 4 files changed, 284 insertions(+) create mode 100644 doc/device-tree-bindings/w1/mxc-w1.txt create mode 100644 drivers/w1/mxc_w1.c diff --git a/doc/device-tree-bindings/w1/mxc-w1.txt b/doc/device-tree-bindings/w1/mxc-w1.txt new file mode 100644 index 0000000..1fb49cc --- /dev/null +++ b/doc/device-tree-bindings/w1/mxc-w1.txt @@ -0,0 +1,37 @@ +NXP i.MX (MXC) One wire bus master controller +======================= + +Child nodes are required in device tree. The driver will detect +the devices serial number and then search in the child nodes in the device tree +for the proper node and try to match it with the device. + +Also check doc/device-tree-bindings/w1-eeprom for possible child nodes drivers + +Driver: +- drivers/w1/mxc_w1.c + +Required properties: +- compatible : should be one of + "fsl,imx21-owire", "fsl,imx27-owire", "fsl,imx31-owire", "fsl,imx25-owire" + "fsl,imx25-owire", "fsl,imx35-owire", "fsl,imx50-owire", "fsl,imx53-owire" + +- reg : Address and length of the register set for the device + +Optional: +* none + +Example: + onewire { + compatible = "fsl,imx53-owire"; + reg = <0x63fa4000 0x4000>; + }; + +Example with child: + onewire { + compatible = "fsl,imx53-owire"; + reg = <0x63fa4000 0x4000>; + + eeprom1: eeprom@0 { + compatible = "maxim,ds24xxx"; + }; + }; diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig index d6e0457..031bab2 100644 --- a/drivers/w1/Kconfig +++ b/drivers/w1/Kconfig @@ -20,6 +20,20 @@ config W1_GPIO help Emulate a 1-wire bus using a GPIO. +config W1_MXC + bool "Enable 1-wire controller on i.MX processors" + default no + depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5 + help + Support the one wire controller found in some members of the NXP + i.MX SoC family. + There are currently two silicon variants: + V1: i.MX21, i.MX27, i.MX31, i.MX51 + V2: i.MX25, i.MX35, i.MX50, i.MX53 + Newer i.MX SoCs such as the i.MX6 do not have one wire controllers. + + The driver supports both silicon variants. + endif endmenu diff --git a/drivers/w1/Makefile b/drivers/w1/Makefile index 7fd8697..9825187 100644 --- a/drivers/w1/Makefile +++ b/drivers/w1/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_W1) += w1-uclass.o obj-$(CONFIG_W1_GPIO) += w1-gpio.o +obj-$(CONFIG_W1_MXC) += mxc_w1.o diff --git a/drivers/w1/mxc_w1.c b/drivers/w1/mxc_w1.c new file mode 100644 index 0000000..9279ba3 --- /dev/null +++ b/drivers/w1/mxc_w1.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for one wire controller in some i.MX Socs + * + * There are currently two silicon variants: + * V1: i.MX21, i.MX27, i.MX31, i.MX51 + * V2: i.MX25, i.MX35, i.MX50, i.MX53 + * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers. + * + * The V1 controller only supports single bit operations. + * The V2 controller is backwards compatible on the register level but adds + * byte size operations and a "search ROM accelerator mode" + * + * This driver does not currently support the search ROM accelerator + * + * Copyright (c) 2018 Flowbird + * Martin Fuzzey <martin.fuzzey(a)flowbird.group> + */ + +#include <asm/arch/clock.h> +#include <common.h> +#include <dm.h> +#include <linux/io.h> +#include <w1.h> + +struct mxc_w1_regs { + u16 control; +#define MXC_W1_CONTROL_RPP BIT(7) +#define MXC_W1_CONTROL_PST BIT(6) +#define MXC_W1_CONTROL_WR(x) BIT(5 - (x)) +#define MXC_W1_CONTROL_RDST BIT(3) + + u16 time_divider; + u16 reset; + + /* Registers below on V2 silicon only */ + u16 command; + u16 tx_rx; + u16 interrupt; +#define MXC_W1_INTERRUPT_TBE BIT(2) +#define MXC_W1_INTERRUPT_TSRE BIT(3) +#define MXC_W1_INTERRUPT_RBF BIT(4) +#define MXC_W1_INTERRUPT_RSRF BIT(5) + + u16 interrupt_en; +}; + +struct mxc_w1_pdata { + struct mxc_w1_regs *regs; +}; + +/* + * this is the low level routine to read/write a bit on the One Wire + * interface on the hardware. It does write 0 if parameter bit is set + * to 0, otherwise a write 1/read. + */ +static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit) +{ + u16 *ctrl_addr = &pdata->regs->control; + u16 mask = MXC_W1_CONTROL_WR(bit); + unsigned int timeout_cnt = 400; /* Takes max. 120us according to + * datasheet. + */ + + writew(mask, ctrl_addr); + + while (timeout_cnt--) { + if (!(readw(ctrl_addr) & mask)) + break; + + udelay(1); + } + + return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0; +} + +static u8 mxc_w1_read_byte(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + struct mxc_w1_regs *regs = pdata->regs; + u16 status; + + if (dev_get_driver_data(dev) < 2) { + int i; + u8 ret = 0; + + for (i = 0; i < 8; i++) + ret |= (mxc_w1_touch_bit(pdata, 1) << i); + + return ret; + } + + readw(&regs->tx_rx); + writew(0xFF, &regs->tx_rx); + + do { + udelay(1); /* Without this bytes are sometimes duplicated... */ + status = readw(&regs->interrupt); + } while (!(status & MXC_W1_INTERRUPT_RBF)); + + return (u8)readw(&regs->tx_rx); +} + +static void mxc_w1_write_byte(struct udevice *dev, u8 byte) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + struct mxc_w1_regs *regs = pdata->regs; + u16 status; + + if (dev_get_driver_data(dev) < 2) { + int i; + + for (i = 0; i < 8; i++) + mxc_w1_touch_bit(pdata, (byte >> i) & 0x1); + + return; + } + + readw(&regs->tx_rx); + writew(byte, &regs->tx_rx); + + do { + udelay(1); + status = readw(&regs->interrupt); + } while (!(status & MXC_W1_INTERRUPT_TSRE)); +} + +static bool mxc_w1_reset(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + u16 reg_val; + + writew(MXC_W1_CONTROL_RPP, &pdata->regs->control); + + do { + reg_val = readw(&pdata->regs->control); + } while (reg_val & MXC_W1_CONTROL_RPP); + + return !(reg_val & MXC_W1_CONTROL_PST); +} + +static u8 mxc_w1_triplet(struct udevice *dev, bool bdir) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + u8 id_bit = mxc_w1_touch_bit(pdata, 1); + u8 comp_bit = mxc_w1_touch_bit(pdata, 1); + u8 retval; + + if (id_bit && comp_bit) + return 0x03; /* error */ + + if (!id_bit && !comp_bit) { + /* Both bits are valid, take the direction given */ + retval = bdir ? 0x04 : 0; + } else { + /* Only one bit is valid, take that direction */ + bdir = id_bit; + retval = id_bit ? 0x05 : 0x02; + } + + mxc_w1_touch_bit(pdata, bdir); + + return retval; +} + +static int mxc_w1_ofdata_to_platdata(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + pdata->regs = (struct mxc_w1_regs *)addr; + + return 0; +}; + +static int mxc_w1_probe(struct udevice *dev) +{ + struct mxc_w1_pdata *pdata = dev_get_platdata(dev); + unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK); + unsigned int clkdiv; + + if (clkrate < 10000000) { + dev_err(dev, "input clock frequency (%u Hz) too low\n", + clkrate); + return -EINVAL; + } + + clkdiv = clkrate / 1000000; + clkrate /= clkdiv; + if (clkrate < 980000 || clkrate > 1020000) { + dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate); + return -EINVAL; + } + + writew(clkdiv - 1, &pdata->regs->time_divider); + + return 0; +} + +static const struct w1_ops mxc_w1_ops = { + .read_byte = mxc_w1_read_byte, + .reset = mxc_w1_reset, + .triplet = mxc_w1_triplet, + .write_byte = mxc_w1_write_byte, +}; + +static const struct udevice_id mxc_w1_id[] = { + { .compatible = "fsl,imx21-owire", .data = 1 }, + { .compatible = "fsl,imx27-owire", .data = 1 }, + { .compatible = "fsl,imx31-owire", .data = 1 }, + { .compatible = "fsl,imx51-owire", .data = 1 }, + + { .compatible = "fsl,imx25-owire", .data = 2 }, + { .compatible = "fsl,imx35-owire", .data = 2 }, + { .compatible = "fsl,imx50-owire", .data = 2 }, + { .compatible = "fsl,imx53-owire", .data = 2 }, + { }, +}; + +U_BOOT_DRIVER(mxc_w1_drv) = { + .id = UCLASS_W1, + .name = "mxc_w1_drv", + .of_match = mxc_w1_id, + .ofdata_to_platdata = mxc_w1_ofdata_to_platdata, + .ops = &mxc_w1_ops, + .platdata_auto_alloc_size = sizeof(struct mxc_w1_pdata), + .probe = mxc_w1_probe, +}; -- 1.9.1

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[U-Boot] [PATCH v2 1/2] watchdog: driver support for fsl-lsch2
by Xiaoliang Yang 08 Dec '18

08 Dec '18

Support watchdog driver for fsl-lsch2. It's disabled in default. If you want to use it, please enable CONFIG_IMX_WATCHDOG. Define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1(a)nxp.com> --- v1->v2: Remove LSCH3 config from imx-watchdog.c, because it only support LSCH2 platforms. Use Kconfig option IMX_WATCHDOG to introduce how to use watchdog driver in README.lsch2. --- arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 | 9 +++++++++ drivers/watchdog/Makefile | 2 ++ drivers/watchdog/imx_watchdog.c | 7 +++++++ 3 files changed, 18 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 index a6ef830..9176546 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2 @@ -8,3 +8,12 @@ Freescale LayerScape with Chassis Generation 2 This architecture supports Freescale ARMv8 SoCs with Chassis generation 2, for example LS1043A. + +Watchdog support Overview +------------------- +Support watchdog driver for LSCH2. The driver is disabled in default. +You can enable it by setting CONFIG_IMX_WATCHDOG. +Use following config to set watchdog timeout, if this config is not defined, +the default timeout value is 128s which is the maximum. Set 10 seconds for +example: + #define CONFIG_WATCHDOG_TIMEOUT_MSECS 10000 diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 08406ca..19c631b 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -7,6 +7,8 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610)) obj-y += imx_watchdog.o +else +obj-$(CONFIG_IMX_WATCHDOG) += imx_watchdog.o endif obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 3f826d1..ddcf474 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -8,6 +8,9 @@ #include <asm/io.h> #include <watchdog.h> #include <asm/arch/imx-regs.h> +#ifdef CONFIG_FSL_LSCH2 +#include <asm/arch/immap_lsch2.h> +#endif #include <fsl_wdog.h> #ifdef CONFIG_IMX_WATCHDOG @@ -33,8 +36,12 @@ void hw_watchdog_init(void) #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; +#ifdef CONFIG_FSL_LSCH2 + writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr); +#else writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); +#endif /* CONFIG_FSL_LSCH2*/ hw_watchdog_reset(); } #endif -- 1.7.1

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[U-Boot] [PATCH] warp7: configs: add CONFIG_FIT option
by Pierre-Jean Texier 08 Dec '18

08 Dec '18

This enable FIT image support. Signed-off-by: Pierre-Jean Texier <pjtexier(a)koncepto.io> --- configs/warp7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 15a6673..919d484 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -8,6 +8,8 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/warp7/imximage.cfg" CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set -- 2.7.4

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[U-Boot] [PATCH V3 0/6] board: ge: Move bootcount to EEPROM
by Fabien Lahoudere 08 Dec '18

08 Dec '18

GE boards need bootcount set in EEPROM instead of file to avoid some issues. This series replace v2 sent by Sebastian Reichel on 2018-07-20. Changes since v2: - Patches have been rebased to apply correctly on master. - Remove a build time warning - Remove checkpatch.pl warning Denis Zalevskiy (6): board: ge: Remove EEPROM bus param from read_vpd() board: ge: Move VPD EEPROM configuration to the defconfig bootcount: i2c: Add bus switching to the I2C bootcount driver bootcount: Configure length limit for I2C bootcount board: ge: Move VPD reading to the vpd_reader board: ge: Store bootcount in EEPROM on PPD and Bx50v3 board/ge/bx50v3/Kconfig | 2 + board/ge/bx50v3/bx50v3.c | 57 ++++++---------------------- board/ge/common/Kconfig | 14 +++++++ board/ge/common/vpd_reader.c | 57 ++++++++++++++++++++++++++-- board/ge/common/vpd_reader.h | 16 +++++--- board/ge/mx53ppd/Kconfig | 2 + board/ge/mx53ppd/mx53ppd.c | 44 ++++------------------ configs/ge_bx50v3_defconfig | 27 +++++++++++-- configs/mx53ppd_defconfig | 29 ++++++++++++-- drivers/bootcount/Kconfig | 21 ++++++++++- drivers/bootcount/bootcount_i2c.c | 79 +++++++++++++++++++++++++++++++++------ include/configs/ge_bx50v3.h | 6 +-- include/configs/mx53ppd.h | 6 +-- 13 files changed, 243 insertions(+), 117 deletions(-) create mode 100644 board/ge/common/Kconfig -- 1.8.3.1

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[U-Boot] [PATCH v3 00/19] DM_I2C_COMPAT removal for all ti platforms
by Jean-Jacques Hiblot 07 Dec '18

07 Dec '18

This series remove the usage of the DM_I2C_COMPAT option for all the ti platforms. It also takes this opportunity to not disable DM_I2C in the SPL. There are a couples of issues to fix: - CMD_EEPROM does not support the DM API. Fixed by removing this option when DM_I2C is used without DM_I2C_COMPAT - i2c_get_chip_for_busnum() does not work when OF_CONTROL is not used (as is the case with am33xx SPL). - The I2C driver do not support DM_I2C without OF_CONTROL. - Most of the PMIC drivers do not support the I2C DM API. - Board detection is done prior DM initialization. Fixed by moving it after DM is initialized. That move breaks the DRA7 platforms (The fixes for that are at the last 5 patches this series) When all this is taken care of DM_I2C_COMPAT can be removed and DM_I2C enabled in the SPL. This has been tested with the following boards: - am437x SK - am335x SK - am335x beaglebone (both DM and non-DM config) - dra76 evm - am572 evm - k2g evm The following targets may be impacted by the changes related to SPL_OF_CONTROL and SPL_OF_PLATDATA: - am3517_evm_defconfig - omap3_logic_defconfig - chromebit_mickey_defconfig - chromebook_jerry_defconfig - chromebook_minnie_defconfig - evb-rk3399_defconfig - rock_defconfig It would be nice it some of you could try to boot them. Changes in v3: - removed commit introducing dm_i2c_probe_device(). Instead probe the presence of the chip on the I2C bus in i2c_get_chip_for_busnum(). - fdtdec_resetup() need not call fdtdec_setup() when only a single DTB is used. - Add documentation in README-fdt-control explaining why and how to use fdtdec_resetup() Changes in v2: - Add missing commit log to the commit disabling CMD_EEPROM when non-DM API is not available - don't use the DT to find the req_seq number if SPL_OF_PLATDATA is used. Instead do it as if SPL_OF_CONTROL is not defined. - Also add DM_I2C support to the twl6030 driver - remove the remaining non-DM I2C API call for pdu001 board. - Fixed warning in power_init_board() for the am43xx ti boards. Andreas Dannenberg (1): ti: common: board_detect: Allow DM I2C without CONFIG_DM_I2C_COMPAT Jean-Jacques Hiblot (17): cmd: Kconfig: Do not include EEPROM if DM_I2C is used without DM_I2C_COMPAT dm: i2c: Make i2c_get_chip_for_busnum() fail if the chip is not detected dm: device: Allow using uclass_find_device_by_seq() without OF_CONTROL configs: am335x: am57x: dra7x: Enable CONFIG_SPL_DM_SEQ_ALIAS i2c: omap24xx_i2c: Use platdata to probe the device am335x: Register the I2C controllers if DM_I2C is used. dts: am43x: omap5: Add node for I2C in SPL omap: detect the board after DM is available power: make most tps drivers and the twl4030 driver compatible with DM_I2C configs: am335x_pdu001: remove CONFIG_DM_I2C_COMPAT ti: remove usage of DM_I2C_COMPAT and don't disable DM_I2C in SPL am57xx: remove non-DM I2C code configs: dra7xx-evm: increase the size of the malloc's pool before relocation lib: fdtdec: Add function re-setup the fdt more effeciently drivers: core: Add the option SPL_DM_DEVICE_REMOVE to the Kconfig drivers: core: nullify gd->dm_root after dm_uninit() dra7: Allow selecting a new dtb after board detection. Vignesh R (1): i2c: omap24xx_i2c: Move away from SoC specific headers for reg offset arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 4 + arch/arm/dts/omap5-u-boot.dtsi | 4 + arch/arm/include/asm/arch-am33xx/i2c.h | 47 +-- arch/arm/include/asm/arch-omap3/i2c.h | 47 --- arch/arm/include/asm/arch-omap4/i2c.h | 45 --- arch/arm/include/asm/arch-omap5/i2c.h | 45 --- arch/arm/include/asm/omap_i2c.h | 24 ++ arch/arm/mach-keystone/ddr3_spd.c | 7 + arch/arm/mach-omap2/am33xx/board.c | 24 +- arch/arm/mach-omap2/am33xx/clk_synthesizer.c | 56 +++- arch/arm/mach-omap2/clocks-common.c | 2 + arch/arm/mach-omap2/hwinit-common.c | 23 +- board/eets/pdu001/board.c | 1 - board/ti/am335x/board.c | 17 +- board/ti/am335x/mux.c | 11 + board/ti/am43xx/board.c | 46 ++- board/ti/am57xx/board.c | 25 +- board/ti/common/board_detect.c | 110 +++---- board/ti/ks2_evm/board_k2g.c | 11 + cmd/Kconfig | 1 + configs/am335x_pdu001_defconfig | 1 + configs/am57xx_evm_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/dra7xx_evm_defconfig | 4 +- configs/dra7xx_hs_evm_defconfig | 1 + configs/omap3_logic_defconfig | 1 + doc/README.fdt-control | 18 ++ drivers/core/Kconfig | 12 +- drivers/core/device.c | 10 +- drivers/core/root.c | 1 + drivers/core/uclass.c | 24 ++ drivers/i2c/i2c-uclass.c | 11 + drivers/i2c/omap24xx_i2c.c | 467 ++++++++++++++++++--------- drivers/power/palmas.c | 39 +++ drivers/power/pmic/pmic_tps62362.c | 24 ++ drivers/power/pmic/pmic_tps65217.c | 44 ++- drivers/power/pmic/pmic_tps65218.c | 85 +++++ drivers/power/pmic/pmic_tps65910.c | 57 +++- drivers/power/twl4030.c | 39 +++ drivers/power/twl6030.c | 39 +++ include/asm-generic/global_data.h | 4 + include/configs/am43xx_evm.h | 2 + include/configs/pdu001.h | 6 - include/configs/ti_armv7_common.h | 18 +- include/dm/uclass-internal.h | 13 + include/fdtdec.h | 21 ++ include/palmas.h | 5 + include/power/tps65217.h | 2 + include/power/tps65910.h | 1 + include/twl4030.h | 6 +- include/twl6030.h | 5 + lib/fdtdec.c | 43 ++- 52 files changed, 1083 insertions(+), 472 deletions(-) create mode 100644 arch/arm/include/asm/omap_i2c.h -- 2.7.4

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[U-Boot] [PATCH v3 0/4] Add Rock960 and Ficus 96Board support
by Manivannan Sadhasivam 06 Dec '18

06 Dec '18

This patchset adds support for Rock960 and Ficus 96Boards from Vamrs. Since both boards share most of the configurations, a common Rock960 family support is added with common support and the actual boards are based on this. The previous version of the patchseries were adding Rock960 [1] and Ficus [2] board support individually, but this series fuses them together based on the common board support as per Linux kernel. [1] https://patchwork.ozlabs.org/cover/963239/ [2] https://lists.denx.de/pipermail/u-boot/2018-August/339059.html This patchseries has been tested on Rock960 v1.2 board and expecting Ezequiel to do the testing for Ficus. PS: I have explicitly removed the previous Ack's for the Ficus board since there has been a heavy modification done on these patches. Thanks, Mani Manivannan Sadhasivam (4): arm: dts: rockchip: add some common pin-settings to rk3399 rockchip: rk3399: Add common Rock960 family from Vamrs rockchip: rk3399: Add Rock960 CE board support rockchip: rk3399: Add Ficus EE board support arch/arm/dts/Makefile | 2 + arch/arm/dts/rk3399-ficus.dts | 78 + arch/arm/dts/rk3399-rock960.dts | 45 + arch/arm/dts/rk3399-rock960.dtsi | 506 ++++++ .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 1536 +++++++++++++++++ arch/arm/dts/rk3399.dtsi | 55 +- arch/arm/mach-rockchip/rk3399/Kconfig | 26 + board/vamrs/rock960_rk3399/Kconfig | 15 + board/vamrs/rock960_rk3399/MAINTAINERS | 6 + board/vamrs/rock960_rk3399/Makefile | 6 + board/vamrs/rock960_rk3399/README | 152 ++ board/vamrs/rock960_rk3399/rock960-rk3399.c | 50 + configs/ficus-rk3399_defconfig | 71 + configs/rock960-rk3399_defconfig | 69 + include/configs/rock960_rk3399.h | 15 + 15 files changed, 2626 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/rk3399-ficus.dts create mode 100644 arch/arm/dts/rk3399-rock960.dts create mode 100644 arch/arm/dts/rk3399-rock960.dtsi create mode 100644 arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi create mode 100644 board/vamrs/rock960_rk3399/Kconfig create mode 100644 board/vamrs/rock960_rk3399/MAINTAINERS create mode 100644 board/vamrs/rock960_rk3399/Makefile create mode 100644 board/vamrs/rock960_rk3399/README create mode 100644 board/vamrs/rock960_rk3399/rock960-rk3399.c create mode 100644 configs/ficus-rk3399_defconfig create mode 100644 configs/rock960-rk3399_defconfig create mode 100644 include/configs/rock960_rk3399.h -- 2.17.1

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[U-Boot] FOSDEM Hardware Enablement Devroom
by Paul Kocialkowski 04 Dec '18

04 Dec '18

A Hardware Enablement devroom will be taking place at FOSDEM this year, on Sunday 10 December 2017. This newly-created devroom is the result of 3 proposals that were merged together. It is co-organized by several individuals. The devroom covers all aspects related to hardware enablement and support with free software, including aspects related to boot software, firmwares, drivers and userspace tools and adaptation. Proposals for talks related to these topics are welcome and can be submitted until Sunday 26 November 2017 via the pentabarf interface. Short talks are encouraged over longer ones in order to cover a wide range of topics. The announcement for the devroom, that contains all the useful information, was published at: https://lists.fosdem.org/pipermail/fosdem/2017-October/002649.html Cheers and see you at FOSDEM! -- Paul Kocialkowski, developer of free digital technology and hardware support Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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[U-Boot] [PATCH] driver/spi: fsl_qspi: Remove non-DM stuff
by Ashish Kumar 04 Dec '18

04 Dec '18

Convert fsl_qspi.c to complete DM mode. Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Tested-by: Rajat Srivastava <rajat.srivastava(a)nxp.com> Tested-by: Ye Li <ye.li(a)nxp.com> --- Tested on LS1088ARDB(arm64). Tested on LS1021ATWR(arm32) by Rajat Tested on i.mx6 and i.mx7 by Ye Li Depends on patch series: http://patchwork.ozlabs.org/patch/935858/ http://patchwork.ozlabs.org/patch/935860/ drivers/spi/fsl_qspi.c | 138 ----------------------------------------- 1 file changed, 138 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 197f41f9db..1598c4f698 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -84,7 +84,6 @@ DECLARE_GLOBAL_DATA_PTR; /* QSPI max chipselect signals number */ #define FSL_QSPI_MAX_CHIPSELECT_NUM 4 -#ifdef CONFIG_DM_SPI /** * struct fsl_qspi_platdata - platform data for Freescale QSPI * @@ -105,7 +104,6 @@ struct fsl_qspi_platdata { u32 flash_num; u32 num_chipselect; }; -#endif /** * struct fsl_qspi_priv - private data for Freescale QSPI @@ -136,12 +134,6 @@ struct fsl_qspi_priv { struct fsl_qspi_regs *regs; }; -#ifndef CONFIG_DM_SPI -struct fsl_qspi { - struct spi_slave slave; - struct fsl_qspi_priv priv; -}; -#endif static u32 qspi_read32(u32 flags, u32 *addr) { @@ -869,136 +861,7 @@ void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits) smpr_val |= set_bits; qspi_write32(priv->flags, &priv->regs->smpr, smpr_val); } -#ifndef CONFIG_DM_SPI -static unsigned long spi_bases[] = { - QSPI0_BASE_ADDR, -#ifdef CONFIG_MX6SX - QSPI1_BASE_ADDR, -#endif -}; - -static unsigned long amba_bases[] = { - QSPI0_AMBA_BASE, -#ifdef CONFIG_MX6SX - QSPI1_AMBA_BASE, -#endif -}; - -static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave) -{ - return container_of(slave, struct fsl_qspi, slave); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - u32 mcr_val; - struct fsl_qspi *qspi; - struct fsl_qspi_regs *regs; - u32 total_size; - - if (bus >= ARRAY_SIZE(spi_bases)) - return NULL; - - if (cs >= FSL_QSPI_FLASH_NUM) - return NULL; - - qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); - if (!qspi) - return NULL; - -#ifdef CONFIG_SYS_FSL_QSPI_BE - qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG; -#endif - - regs = (struct fsl_qspi_regs *)spi_bases[bus]; - qspi->priv.regs = regs; - /* - * According cs, use different amba_base to choose the - * corresponding flash devices. - * - * If not, only one flash device is used even if passing - * different cs using `sf probe` - */ - qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE; - - qspi->slave.max_write_size = TX_BUFFER_SIZE; - - mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr); - - /* Set endianness to LE for i.mx */ - if (IS_ENABLED(CONFIG_MX6) || IS_ENABLED(CONFIG_MX7)) - mcr_val = QSPI_MCR_END_CFD_LE; - - qspi_write32(qspi->priv.flags, &regs->mcr, - QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK | - (mcr_val & QSPI_MCR_END_CFD_MASK)); - - qspi_cfg_smpr(&qspi->priv, - ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK | - QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); - - total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; - /* - * Any read access to non-implemented addresses will provide - * undefined results. - * - * In case single die flash devices, TOP_ADDR_MEMA2 and - * TOP_ADDR_MEMB2 should be initialized/programmed to - * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, - * setting the size of these devices to 0. This would ensure - * that the complete memory map is assigned to only one flash device. - */ - qspi_write32(qspi->priv.flags, &regs->sfa1ad, - FSL_QSPI_FLASH_SIZE | amba_bases[bus]); - qspi_write32(qspi->priv.flags, &regs->sfa2ad, - FSL_QSPI_FLASH_SIZE | amba_bases[bus]); - qspi_write32(qspi->priv.flags, &regs->sfb1ad, - total_size | amba_bases[bus]); - qspi_write32(qspi->priv.flags, &regs->sfb2ad, - total_size | amba_bases[bus]); - - qspi_set_lut(&qspi->priv); - -#ifdef CONFIG_SYS_FSL_QSPI_AHB - qspi_init_ahb_read(&qspi->priv); -#endif - - qspi_module_disable(&qspi->priv, 0); - - return &qspi->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_qspi *qspi = to_qspi_spi(slave); - - free(qspi); -} -int spi_claim_bus(struct spi_slave *slave) -{ - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - /* Nothing to do */ -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct fsl_qspi *qspi = to_qspi_spi(slave); - - return qspi_xfer(&qspi->priv, bitlen, dout, din, flags); -} - -void spi_init(void) -{ - /* Nothing to do */ -} -#else static int fsl_qspi_child_pre_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); @@ -1265,4 +1128,3 @@ U_BOOT_DRIVER(fsl_qspi) = { .probe = fsl_qspi_probe, .child_pre_probe = fsl_qspi_child_pre_probe, }; -#endif -- 2.17.1

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