October 2018 - U-Boot

[U-Boot] [PATCH 1/1] dm: video: correctly set the cursor position
by Heinrich Schuchardt 29 Oct '18

29 Oct '18

The terminal escape sequence ESC [ <x> ; <y> H is used to set the cursor position. According to the ECMA 48 standard the upper left corner in the escape sequences is [1, 1]. The video uclass uses [0, 0] as upper left corner. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/video/vidconsole-uclass.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/video/vidconsole-uclass.c b/drivers/video/vidconsole-uclass.c index 1874887f2f3..5564cfe9930 100644 --- a/drivers/video/vidconsole-uclass.c +++ b/drivers/video/vidconsole-uclass.c @@ -271,6 +271,14 @@ static void vidconsole_escape_char(struct udevice *dev, char ch) s = parsenum(s, &row); s++; /* ; */ s = parsenum(s, &col); + + /* + * Video origin is [0, 0], terminal origin is [1, 1]. + */ + if (row) + --row; + if (col) + --col; set_cursor_position(priv, row, col); -- 2.19.1

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[U-Boot] [PATCH][v2] armv8: lx2160ardb : Add support for LX2160ARDB platform
by Priyanka Jain 29 Oct '18

29 Oct '18

LX2160ARDB is an evaluation board that supports LX2160A family SoCs. This patch add base support for this board. Signed-off-by: Wasim Khan <wasim.khan(a)nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur(a)nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Signed-off-by: Pankit Garg <pankit.garg(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: Rebased on top of test_qoriq branch of u-boot-fsl-qoriq.git Corrected line seria01.clock = get_serial_clock -> serial1.clock = get_serial_clock(); Corrected CONFIG_ENV_OFFSET to 0x500000 [Thanks to Ashish K for pointing this] Depends on below patches[sequence in increasing order] 1)https://patchwork.ozlabs.org/patch/982258/ 2)https://patchwork.ozlabs.org/patch/975541/ 3)https://patchwork.ozlabs.org/patch/962408/ 4)https://patchwork.ozlabs.org/patch/982259/ 5)https://patchwork.ozlabs.org/patch/982237/ 6)https://patchwork.ozlabs.org/patch/990088/ 7)https://patchwork.ozlabs.org/patch/990093/ arch/arm/Kconfig | 14 ++ arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/fsl-lx2160a-rdb.dts | 20 +++ board/freescale/common/qixis.c | 4 + board/freescale/lx2160a/Kconfig | 16 ++ board/freescale/lx2160a/MAINTAINERS | 8 + board/freescale/lx2160a/Makefile | 9 + board/freescale/lx2160a/README | 79 +++++++++ board/freescale/lx2160a/ddr.c | 20 +++ board/freescale/lx2160a/eth_lx2160ardb.c | 210 +++++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 279 +++++++++++++++++++++++++++++++ configs/lx2160ardb_tfa_defconfig | 74 ++++++++ include/configs/lx2160a_common.h | 214 ++++++++++++++++++++++++ include/configs/lx2160ardb.h | 102 +++++++++++ 15 files changed, 1052 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-rdb.dts create mode 100644 board/freescale/lx2160a/Kconfig create mode 100644 board/freescale/lx2160a/MAINTAINERS create mode 100644 board/freescale/lx2160a/Makefile create mode 100644 board/freescale/lx2160a/README create mode 100644 board/freescale/lx2160a/ddr.c create mode 100644 board/freescale/lx2160a/eth_lx2160ardb.c create mode 100644 board/freescale/lx2160a/lx2160a.c create mode 100644 configs/lx2160ardb_tfa_defconfig create mode 100644 include/configs/lx2160a_common.h create mode 100644 include/configs/lx2160ardb.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ccf2a84..28a81e7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1027,6 +1027,19 @@ config TARGET_LS2081ARDB development platform that supports the QorIQ LS2081A/LS2041A Layerscape Architecture processor. +config TARGET_LX2160ARDB + bool "Support lx2160ardb" + select ARCH_LX2160A + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY + select BOARD_LATE_INIT + help + Support for NXP LX2160ARDB platform. + The lx2160ardb (LX2160A Reference design board (RDB) + is a high-performance development platform that supports the + QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. + config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 @@ -1488,6 +1501,7 @@ source "board/freescale/ls1046ardb/Kconfig" source "board/freescale/ls1012aqds/Kconfig" source "board/freescale/ls1012ardb/Kconfig" source "board/freescale/ls1012afrdm/Kconfig" +source "board/freescale/lx2160a/Kconfig" source "board/freescale/mx35pdk/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/grinn/chiliboard/Kconfig" diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index c8bebab..aac3aeb 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -105,7 +105,7 @@ config PSCI_RESET !TARGET_LS1012AFRWY && \ !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ - !TARGET_LS2081ARDB && \ + !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 44ebc50..25cd773 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -226,7 +226,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ fsl-ls1088a-rdb.dtb \ - fsl-ls1088a-qds.dtb + fsl-ls1088a-qds.dtb \ + fsl-lx2160a-rdb.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts new file mode 100644 index 0000000..08201b5 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160ARDB device tree source + * + * Author: Priyanka Jain <priyanka.jain(a)nxp.com> + * Sriram Dash <sriram.dash(a)nxp.com> + * + * Copyright 2018 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160ARDB Board"; + compatible = "fsl,lx2160ardb", "fsl,lx2160a"; + +}; diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index af3dc59..f1b98bc 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -227,8 +227,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const ar #ifdef QIXIS_LBMAP_SD QIXIS_WRITE(rst_ctl, 0x30); QIXIS_WRITE(rcfg_ctl, 0); +#ifdef NON_EXTENDED_DUTCFG + QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD); +#else set_lbmap(QIXIS_LBMAP_SD); set_rcw_src(QIXIS_RCW_SRC_SD); +#endif QIXIS_WRITE(rcfg_ctl, 0x20); QIXIS_WRITE(rcfg_ctl, 0x21); #else diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig new file mode 100644 index 0000000..5562c3e --- /dev/null +++ b/board/freescale/lx2160a/Kconfig @@ -0,0 +1,16 @@ +if TARGET_LX2160ARDB + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2160ardb" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS new file mode 100644 index 0000000..b4dd842 --- /dev/null +++ b/board/freescale/lx2160a/MAINTAINERS @@ -0,0 +1,8 @@ +LX2160ARDB BOARD +M: Priyanka Jain <priyanka.jain(a)nxp.com> +S: Maintained +F: board/freescale/lx2160a/ +F: include/configs/lx2160a_common.h +F: include/configs/lx2160ardb.h +F: configs/lx2160ardb_defconfig +F: arch/arm/dts/fsl-lx2160a-rdb.dts diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile new file mode 100644 index 0000000..be3709d --- /dev/null +++ b/board/freescale/lx2160a/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2018 Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lx2160a.o +obj-y += ddr.o +obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README new file mode 100644 index 0000000..618c40b --- /dev/null +++ b/board/freescale/lx2160a/README @@ -0,0 +1,79 @@ +Overview +-------- +The LX2160A Reference Design (RDB) is a high-performance computing, +evaluation, and development platform that supports the QorIQ LX2160A +Layerscape Architecture processor and its personalities. + +LX2160A SoC Overview +-------------------------------------- +For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +LX2160ARDB board Overview +---------------------- +DDR Memory + Two ports of 72-bits (8-bits ECC) DDR4. + Each port supports four chip-selects and two DIMM + connectors. Data rate upto 3.2 GT/s. + +SERDES ports + Thress serdes controllers (24 lanes) + Serdes1: Supports two USXGMII connectors, each connected through + Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi + IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi + CS4223 phy. + + Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0 + connectors + + Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector + +eSDHC + eSDHC1: Supports a SD connector for connecting SD cards + eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC + +Octal SPI (XSPI) + Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator + for off-board emulation + +I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer + Serial Ports + +USB 3.0 + Two high speed USB 3.0 ports. First USB 3.0 port configured as + Host with Type-A connector, second USB 3.0 port configured as OTG + with micro-AB connector + +Serial Ports Two UART ports +Ethernet Two RGMII interfaces +Debug ARM JTAG support + +Booting Options +--------------- +a) Flexspi boot +b) SD boot + +Memory map for Flexspi flash +---------------------------- +Image Flash Offset +bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00100000 +Boot firmware Environment 0x00500000 +DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 +DPAA2 MC Firmware 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for sd card +---------------------------- +Image SD card Offset +bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00800 +Boot firmware Environment 0x02800 +DDR PHY Firmware (fip_ddr_all.bin) 0x04000 +DPAA2 MC Firmware 0x05000 +DPAA2 DPL 0x06800 +DPAA2 DPC 0x07000 +Kernel.itb 0x08000 diff --git a/board/freescale/lx2160a/ddr.c b/board/freescale/lx2160a/ddr.c new file mode 100644 index 0000000..cd422bf --- /dev/null +++ b/board/freescale/lx2160a/ddr.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <fsl_ddr_sdram.h> +#include <fsl_ddr_dimm_params.h> + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_initdram(void) +{ + gd->ram_size = tfa_get_dram_size(); + + if (!gd->ram_size) + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; +} diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c new file mode 100644 index 0000000..ab75582 --- /dev/null +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -0,0 +1,210 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <malloc.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <exports.h> +#include <asm/arch/fsl_serdes.h> +#include <fsl-mc/fsl_mc.h> +#include <fsl-mc/ldpaa_wriop.h> + +DECLARE_GLOBAL_DATA_PTR; + +static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad) +{ + int phy_reg; + u32 phy_id; + + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + phy_id = (phy_reg & 0xffff) << 16; + + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + phy_id |= (phy_reg & 0xffff); + + if (phy_id == PHY_UID_IN112525_S03) + return true; + else + return false; +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FSL_MC_ENET) + struct memac_mdio_info mdio_info; + struct memac_mdio_controller *reg; + int i, interface; + struct mii_dev *dev; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /* Register the EMI 1 */ + fm_memac_mdio_init(bis, &mdio_info); + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /* Register the EMI 2 */ + fm_memac_mdio_init(bis, &mdio_info); + + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + switch (srds_s1) { + case 19: + wriop_set_phy_address(WRIOP1_DPMAC2, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC3, + AQR107_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC4, + AQR107_PHY_ADDR2); + if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + wriop_set_phy_address(WRIOP1_DPMAC5, + INPHI_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, + INPHI_PHY_ADDR1); + } + wriop_set_phy_address(WRIOP1_DPMAC17, + RGMII_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC18, + RGMII_PHY_ADDR2); + break; + + case 18: + wriop_set_phy_address(WRIOP1_DPMAC7, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC8, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC9, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC10, + CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC3, + AQR107_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC4, + AQR107_PHY_ADDR2); + if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + wriop_set_phy_address(WRIOP1_DPMAC5, + INPHI_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, + INPHI_PHY_ADDR1); + } + wriop_set_phy_address(WRIOP1_DPMAC17, + RGMII_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC18, + RGMII_PHY_ADDR2); + break; + + default: + printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n", + srds_s1); + goto next; + } + + for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_25G_AUI: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + wriop_set_mdio(i, dev); + break; + case PHY_INTERFACE_MODE_XLAUI: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + +next: + cpu_eth_init(bis); +#endif /* CONFIG_FSL_MC_ENET */ + +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + return pci_eth_init(bis); +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +int fdt_fixup_board_phy(void *fdt) +{ + int mdio_offset; + int ret; + struct mii_dev *dev; + + ret = 0; + + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) { + mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000"); + + if (mdio_offset < 0) + mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000"); + + if (mdio_offset < 0) { + printf("mdio@0x8B9700 node not found in dts\n"); + return mdio_offset; + } + + ret = fdt_setprop_string(fdt, mdio_offset, "status", + "disabled"); + if (ret) { + printf("Could not set disable mdio@0x8B97000 %s\n", + fdt_strerror(ret)); + return ret; + } + } + + return ret; +} diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c new file mode 100644 index 0000000..a62222e --- /dev/null +++ b/board/freescale/lx2160a/lx2160a.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <dm.h> +#include <dm/platform_data/serial_pl01x.h> +#include <i2c.h> +#include <malloc.h> +#include <errno.h> +#include <netdev.h> +#include <fsl_ddr.h> +#include <fsl_sec.h> +#include <asm/io.h> +#include <fdt_support.h> +#include <linux/libfdt.h> +#include <fsl-mc/fsl_mc.h> +#include <environment.h> +#include <efi_loader.h> +#include <asm/arch/mmu.h> +#include <hwconfig.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include "../common/qixis.h" +#include "../common/vid.h" +#include <fsl_immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct pl01x_serial_platdata serial0 = { +#if CONFIG_CONS_INDEX == 0 + .base = CONFIG_SYS_SERIAL0, +#elif CONFIG_CONS_INDEX == 1 + .base = CONFIG_SYS_SERIAL1, +#else +#error "Unsupported console index value." +#endif + .type = TYPE_PL011, +}; + +U_BOOT_DEVICE(nxp_serial0) = { + .name = "serial_pl01x", + .platdata = &serial0, +}; + +static struct pl01x_serial_platdata serial1 = { + .base = CONFIG_SYS_SERIAL1, + .type = TYPE_PL011, +}; + +U_BOOT_DEVICE(nxp_serial1) = { + .name = "serial_pl01x", + .platdata = &serial1, +}; + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +static void uart_get_clock(void) +{ + serial0.clock = get_serial_clock(); + serial1.clock = get_serial_clock(); +} + +int board_early_init_f(void) +{ +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif + /* get required clock for UART IP */ + uart_get_clock(); + + fsl_lsch3_early_init_f(); + return 0; +} + +int esdhc_status_fixup(void *blob, const char *compat) +{ + /* Enable both esdhc DT nodes for LX2160ARDB */ + do_fixup_by_compat(blob, compat, "status", "okay", + sizeof("okay"), 1); + + return 0; +} + +#if defined(CONFIG_VID) +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + +#endif + +int checkboard(void) +{ + enum boot_src src = get_boot_src(); + char buf[64]; + u8 sw; + + cpu_name(buf); + printf("Board: %s-RDB, ", buf); + + sw = QIXIS_READ(arch); + printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); + + if (src == BOOT_SOURCE_SD_MMC) { + puts("SD\n"); + } else { + sw = QIXIS_READ(brdcfg[0]); + sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; + switch (sw) { + case 0: + case 4: + puts("FlexSPI DEV#0\n"); + break; + case 1: + puts("FlexSPI DEV#1\n"); + break; + case 2: + case 3: + puts("FlexSPI EMU\n"); + break; + default: + printf("invalid setting, xmap: %d\n", sw); + break; + } + } + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); + + puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); + puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); + puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n"); + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + return 100000000; +} + +unsigned long get_board_ddr_clk(void) +{ + return 100000000; +} + +int board_init(void) +{ +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + int i; + u64 ddr_size = 0; + + puts("\nDDR "); + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + ddr_size += gd->bd->bi_dram[i].size; + print_size(ddr_size, ""); + print_ddr_info(0); +} + +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + return 0; +} +#endif + +#ifdef CONFIG_FSL_MC_ENET +extern int fdt_fixup_board_phy(void *fdt); + +void fdt_fixup_board_enet(void *fdt) +{ + int offset; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc"); + + if (offset < 0) { + printf("%s: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + + if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) { + fdt_status_okay(fdt, offset); + fdt_fixup_board_phy(fdt); + } else { + fdt_status_fail(fdt, offset); + } +} + +void board_quiesce_devices(void) +{ + fsl_mc_ldpaa_exit(gd->bd); +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP + +int ft_board_setup(void *blob, bd_t *bd) +{ + int i; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + + ft_cpu_setup(blob, bd); + + /* fixup DT for the three GPP DDR banks */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + base[i] = gd->bd->bi_dram[i].start; + size[i] = gd->bd->bi_dram[i].size; + } + +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; + else if (gd->arch.resv_ram >= base[2] && + gd->arch.resv_ram < base[2] + size[2]) + size[2] = gd->arch.resv_ram - base[2]; +#endif + + fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); + +#ifdef CONFIG_USB + fsl_fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_FSL_MC_ENET + fdt_fsl_mc_fixup_iommu_map_entry(blob); + fdt_fixup_board_enet(blob); +#endif + + return 0; +} +#endif + +void qixis_dump_switch(void) +{ + int i, nr_of_cfgsw; + + QIXIS_WRITE(cms[0], 0x00); + nr_of_cfgsw = QIXIS_READ(cms[1]); + + puts("DIP switch settings dump:\n"); + for (i = 1; i <= nr_of_cfgsw; i++) { + QIXIS_WRITE(cms[0], i); + printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); + } +} diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig new file mode 100644 index 0000000..fb1102e --- /dev/null +++ b/configs/lx2160ardb_tfa_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2160ARDB=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_DM=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_TFABOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_SERIAL=y +CONFIG_CONS_INDEX=0 +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=n +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_NXP_FSPI=y +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_SYS_FSPI_AHB_INIT=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_PHY_GIGE=y +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_NET=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +# CONFIG_SYS_FSL_DDR_PHY is not set +CONFIG_SYS_GEN2_DDR_PHY=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_PHYLIB_10G=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_INPHI=y +CONFIG_INPHI_25G=y +CONFIG_HUSH_PARSER=y +CONFIG_EMC2305=y diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h new file mode 100644 index 0000000..5c08c87 --- /dev/null +++ b/include/configs/lx2160a_common.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LX2_COMMON_H +#define __LX2_COMMON_H + +#include <asm/arch/stream_id_lsch3.h> +#include <asm/arch/config.h> +#include <asm/arch/soc.h> + +#define CONFIG_REMAKE_ELF +#define CONFIG_FSL_LAYERSCAPE +#define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 +#define CONFIG_FSL_MEMAC + +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_FLASH_BASE 0x20000000 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* DDR */ +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 +#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL +#define CONFIG_DDR_SPD +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS3 0x53 +#define SPD_EEPROM_ADDRESS4 0x54 +#define SPD_EEPROM_ADDRESS5 0x55 +#define SPD_EEPROM_ADDRESS6 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ +#define CONFIG_SYS_MONITOR_LEN (936 * 1024) + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) + +/* SMP Definitinos */ +#define CPU_RELEASE_ADDR secondary_boot_func + +/* Generic Timer Definitions */ +/* + * This is not an accurate number. It is used in start.S. The frequency + * will be udpated later when get_bus_freq(0) is available. + */ + +#define COUNTER_FREQUENCY 25000000 /* 25MHz */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) + +/* Serial Port */ +#define CONFIG_PL01X_SERIAL +#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) +#define CONFIG_SYS_SERIAL0 0x21c0000 +#define CONFIG_SYS_SERIAL1 0x21d0000 +#define CONFIG_SYS_SERIAL2 0x21e0000 +#define CONFIG_SYS_SERIAL3 0x21f0000 +/*below might needs to be removed*/ +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1, \ + (void *)CONFIG_SYS_SERIAL2, \ + (void *)CONFIG_SYS_SERIAL3 } +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* MC firmware */ +#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 + +/* Define phy_reset function to boot the MC based on mcinitcmd. + * This happens late enough to properly fixup u-boot env MAC addresses. + */ +#define CONFIG_RESET_PHY_R + +/* + * Carve out a DDR region which will not be used by u-boot/Linux + * + * It will be used by MC and Debug Server. The MC region must be + * 512MB aligned, so the min size to hide is 512MB. + */ +#ifdef CONFIG_FSL_MC_ENET +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#endif + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_CH_DEFAULT 0x8 + +/* RTC */ +#define RTC +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Qixis */ +#define CONFIG_FSL_QIXIS +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + +/* PCI */ +#ifdef CONFIG_PCI +#define CONFIG_SYS_PCI_64BIT +#define CONFIG_PCI_SCAN_SHOW +#endif + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#endif + +/* SATA */ + +#ifdef CONFIG_SCSI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 +#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) +#endif + +/* USB */ +#ifdef CONFIG_USB +#define CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +/* FlexSPI */ +#ifdef CONFIG_NXP_FSPI +#define NXP_FSPI_FLASH_SIZE SZ_64M +#define NXP_FSPI_FLASH_NUM 1 +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ + CONFIG_ENV_OFFSET) + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* Initial environment variables */ +#define XSPI_NOR_BOOTCOMMAND "fsl_mc apply dpl 0x20d00000;" \ + "sf probe 0:0;" \ + "sf read 0xa0000000 0x1000000 0x3000000;" \ + "bootm 0xa0000000" + +#define SD_BOOTCOMMAND "mmc read 0xa0000000 0x6800 0xA0;" \ + "fsl_mc apply dpl 0xa0000000;" \ + "mmc read 0xb0000000 0x8000 0x1d000;" \ + "bootm 0xb0000000" + +#define XSPI_MC_INIT_CMD \ + "fsl_mc start mc 0x20a00000 0x20e00000\0" + +#define SD_MC_INIT_CMD \ + "mmc read 0x80000000 0x5000 0x800;" \ + "mmc read 0x80100000 0x7000 0x800;" \ + "fsl_mc start mc 0x80000000 0x80100000\0" + +#endif /* __LX2_COMMON_H */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h new file mode 100644 index 0000000..67d214d --- /dev/null +++ b/include/configs/lx2160ardb.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __LX2_RDB_H +#define __LX2_RDB_H + +#include "lx2160a_common.h" + +/* Qixis */ +#define QIXIS_XMAP_MASK 0x07 +#define QIXIS_XMAP_SHIFT 5 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SD +#define QIXIS_RCW_SRC_SD 0x08 +#define NON_EXTENDED_DUTCFG + +/* VID */ + +#define I2C_MUX_CH_VOL_MONITOR 0xA +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" +#define CONFIG_VID + +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 855 + +/* PM Bus commands code for LTC3882*/ +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 +#define PMBUS_CMD_VOUT_COMMAND 0x21 +#define PWM_CHANNEL0 0x0 + +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 4 + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC1@xgmii" + +#define AQR107_PHY_ADDR1 0x04 +#define AQR107_PHY_ADDR2 0x05 + +#define CORTINA_NO_FW_UPLOAD +#define CORTINA_PHY_ADDR1 0x0 +#define INPHI_PHY_ADDR1 0x0 + +#define RGMII_PHY_ADDR1 0x01 +#define RGMII_PHY_ADDR2 0x02 + +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x21000000\0" \ + "lx2160ardb_vdd_mv=800\0" \ + "mcmemsize=0x40000000\0" + +#include <asm/fsl_secure_boot.h> + +#endif /* __LX2_RDB_H */ -- 2.7.4

1 0

[U-Boot] [PATCH 1/2] AQUANTIA USXGMII autoneg enable
by Valentin-catalin Neacsu 29 Oct '18

29 Oct '18

If System interface protocol is USXGMII then enable USXGMII autoneg Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu(a)nxp.com> --- drivers/net/phy/aquantia.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 6678147545..57eede14ce 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -20,6 +20,13 @@ #define AQUNTIA_SPEED_LSB_MASK 0x2000 #define AQUNTIA_SPEED_MSB_MASK 0x40 +#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812 +#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441 + +#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008 +#define AQUANTIA_SI_IN_USE_MASK 0x0078 +#define AQUANTIA_SI_USXGMII 0x0018 + int aquantia_config(struct phy_device *phydev) { u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); @@ -41,6 +48,16 @@ int aquantia_config(struct phy_device *phydev) phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, AQUNTIA_SPEED_LSB_MASK | AQUNTIA_SPEED_MSB_MASK); + + val = phy_read(phydev, MDIO_MMD_PHYXS, + AQUANTIA_SYSTEM_INTERFACE_SR); + /* If SI is USXGMII then start USXGMII autoneg*/ + if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) { + phy_write(phydev, MDIO_MMD_PHYXS, + AQUANTIA_VENDOR_PROVISIONING_REG, + AQUANTIA_USX_AUTONEG_CONTROL_ENA); + } + } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { /* 2.5GBASE-T mode */ phydev->advertising = SUPPORTED_1000baseT_Full; -- 2.17.1

1 1

[U-Boot] [PATCH] riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
by Andes 29 Oct '18

29 Oct '18

From: Rick Chen <rick(a)andestech.com> ax25-ae350 use CONFIG_OF_BOARD which allow the board to override the fdt address. And prior_stage_fdt_address offer a temporary memory address to keep the dtb address which was passed from loader(gdb) to u-boot with a1. Signed-off-by: Rick Chen <rick(a)andestech.com> Cc: Greentime Hu <greentime(a)andestech.com> --- board/AndesTech/ax25-ae350/ax25-ae350.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 5f4ca0f..d343453 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -14,6 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; +extern phys_addr_t prior_stage_fdt_address; /* * Miscellaneous platform dependent initializations */ @@ -66,7 +67,7 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) void *board_fdt_blob_setup(void) { - void **ptr = (void *)CONFIG_SYS_SDRAM_BASE; + void **ptr = (void *)&prior_stage_fdt_address; if (fdt_magic(*ptr) == FDT_MAGIC) return (void *)*ptr; -- 2.7.4

4 8

[U-Boot] [PATCH] sunxi: lower the DDR frequency of Orange Pi Prime
by Icenowy Zheng 29 Oct '18

29 Oct '18

When I use Orange Pi Prime to do some heavy compliation tasks, the gcc compiler sometimes mysteriously segfaults, and memtester catches memory error. As the lima-memtester cannot support H5 (Mali-450 GPU equipped), there's no really reliable way to detect DRAM stability except try and error. Lower the DDR frequency to 624MHz seems to solved the issue. Set the default frequency to 624MHz in the defconfig, as 672MHz is observed to be unstable at least on my board. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> --- configs/orangepi_prime_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 3d87374002..88eaf12741 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN50I_H5=y -CONFIG_DRAM_CLK=672 +CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-prime" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set -- 2.13.6

5 9

[U-Boot] [PATCH 0/7] Exynos4412 SPL support
by Simon Shields 29 Oct '18

29 Oct '18

Hi, This patch series adds support for using U-Boot's SPL as the second stage bootloader ("BL2") on Exynos4412 SoCs. - Patch #1 adds support for the EMMC/SD OM pin configuration, which is used by the boards I tested on. - Patch #2 configures the magic values used to indicate system suspend state (which are identical to exynos5). - Patch #3 renames the existing exynos4 clock/dmc initialisation code to reflect the fact that it only supports exynos4210. - Patches #4 and #5 add/fill in structs reflecting the PMU and TZASC register layouts on exynos4412, respectively. - Patch #6 adds the exynos4412 DMC and clock initialisation code and enables building the SPL on exynos4412 platforms. - Patch #7 enables building the "mkexynosspl" utility for exynos4 SoCs. The majority of the logic in patch #6 comes from a vendor u-boot dump (2010.12!), however, small portions (mostly code used for 2GB RAM initialisation) were reverse engineered from the vendor bootloader found on a GT-N7100. This patch series has been tested on a GT-I9300 (exynos4412, 1GB RAM) and a GT-N7100 (exynos4412 prime, 2GB RAM), with a few additional patchsets applied for board/HW support (which I intend to upstream in the future). Cheers, Simon Simon Shields (7): ARM: exynos: spl: add EMMC/SD boot mode support exynos4: configure power down magic values ARM: exynos: rename exynos4 setup files to exynos4210 ARM: exynos: fill in exynos4412_power struct ARM: exynos: add exynos4412 TZASC memory layout ARM: exynos: SPL support for exynos 4412 tools: build mkexynosspl for exynos4 as well arch/arm/mach-exynos/Kconfig | 6 + arch/arm/mach-exynos/Makefile | 3 +- ...init_exynos4.c => clock_init_exynos4210.c} | 2 +- arch/arm/mach-exynos/clock_init_exynos4412.c | 122 +++++ ...c_init_exynos4.c => dmc_init_exynos4210.c} | 2 +- arch/arm/mach-exynos/dmc_init_exynos4412.c | 185 ++++++++ .../{exynos4_setup.h => exynos4210_setup.h} | 0 arch/arm/mach-exynos/exynos4412_setup.h | 425 ++++++++++++++++++ arch/arm/mach-exynos/include/mach/cpu.h | 2 +- arch/arm/mach-exynos/include/mach/dmc.h | 19 + arch/arm/mach-exynos/include/mach/power.h | 290 +++++++++++- arch/arm/mach-exynos/power.c | 12 + arch/arm/mach-exynos/spl_boot.c | 22 +- include/configs/exynos4-common.h | 5 + tools/Makefile | 1 + 15 files changed, 1084 insertions(+), 12 deletions(-) rename arch/arm/mach-exynos/{clock_init_exynos4.c => clock_init_exynos4210.c} (99%) create mode 100644 arch/arm/mach-exynos/clock_init_exynos4412.c rename arch/arm/mach-exynos/{dmc_init_exynos4.c => dmc_init_exynos4210.c} (99%) create mode 100644 arch/arm/mach-exynos/dmc_init_exynos4412.c rename arch/arm/mach-exynos/{exynos4_setup.h => exynos4210_setup.h} (100%) create mode 100644 arch/arm/mach-exynos/exynos4412_setup.h -- 2.18.0

3 13

[U-Boot] Please pull u-boot-x86
by Bin Meng 29 Oct '18

29 Oct '18

Hi Tom, These are various small fixes for x86 for this release. The following changes since commit 24a72511e7eeec78c9cc3f72953ff8726849b0c1: vf610twr: Enable thumb2 for builds (2018-10-26 08:40:53 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to 3d2be8003c77cad350f1ec7c79f914797718c5bf: x86: Fix car_uninit weak symbol definition (2018-10-28 21:02:15 +0800) ---------------------------------------------------------------- Bin Meng (1): x86: Fix car_uninit weak symbol definition Stefan Roese (4): x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / region x86: theadorable-x86-common: Change pci hotplug cmdline parameters (again) x86: theadorable-x86: Generate and pass root=PARTUUID instead of /dev/sdaX x86: theadorable-x86-xxx_defconfig: Move VGA BIOS to make room for U-Boot arch/x86/cpu/start.S | 12 ++++++------ arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl | 6 +++--- configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 3 ++- configs/theadorable-x86-conga-qa3-e3845_defconfig | 3 ++- configs/theadorable-x86-dfi-bt700_defconfig | 2 +- include/configs/theadorable-x86-common.h | 38 ++++++++++++++++++++++---------------- 6 files changed, 36 insertions(+), 28 deletions(-) Regards, Bin

2 1

[U-Boot] [PATCH] drivers: cosmetic: Convert SPDX license tags to Linux Kernel style
by Patrick Delaunay 29 Oct '18

29 Oct '18

Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- drivers/adc/Makefile | 3 +-- drivers/axi/Makefile | 3 +-- drivers/board/Makefile | 2 +- drivers/board/gazerbeam.h | 1 - drivers/clk/Makefile | 3 +-- drivers/clk/altera/Makefile | 3 +-- drivers/clk/aspeed/Makefile | 3 +-- drivers/clk/owl/Makefile | 2 +- drivers/clk/rockchip/Makefile | 3 +-- drivers/clk/tegra/Makefile | 3 ++- drivers/cpu/Makefile | 4 ++-- drivers/fastboot/Makefile | 2 +- drivers/mailbox/Makefile | 3 ++- drivers/misc/fs_loader.c | 4 ++-- drivers/net/pfe_eth/Makefile | 3 ++- drivers/phy/allwinner/Makefile | 4 ++-- drivers/power/domain/Makefile | 3 ++- drivers/power/regulator/Makefile | 3 +-- drivers/ram/Makefile | 3 +-- drivers/ram/rockchip/Makefile | 3 +-- drivers/reset/Makefile | 3 ++- drivers/usb/common/Makefile | 4 ++-- drivers/usb/dwc3/dwc3-generic.c | 2 +- drivers/video/tegra124/Makefile | 3 +-- 24 files changed, 32 insertions(+), 38 deletions(-) diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile index cca0fec..c1387f3 100644 --- a/drivers/adc/Makefile +++ b/drivers/adc/Makefile @@ -1,9 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2015 Samsung Electronics # Przemyslaw Marczak <p.marczak(a)samsung.com> # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_ADC) += adc-uclass.o obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o diff --git a/drivers/axi/Makefile b/drivers/axi/Makefile index 66b6c5a..045db1a 100644 --- a/drivers/axi/Makefile +++ b/drivers/axi/Makefile @@ -1,9 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2017 # Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_AXI) += axi-uclass.o obj-$(CONFIG_IHS_AXI) += ihs_axi.o diff --git a/drivers/board/Makefile b/drivers/board/Makefile index 2224338..c8dab4f 100644 --- a/drivers/board/Makefile +++ b/drivers/board/Makefile @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2017 # Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc diff --git a/drivers/board/gazerbeam.h b/drivers/board/gazerbeam.h index 0ca003a..171729d 100644 --- a/drivers/board/gazerbeam.h +++ b/drivers/board/gazerbeam.h @@ -3,7 +3,6 @@ * (C) Copyright 2017 * Mario Six, Guntermann & Drunck GmbH, mario.six(a)gdsys.cc * - * SPDX-License-Identifier: GPL-2.0+ */ enum { diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 8bc9f52..abd112d 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -1,9 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (c) 2015 Google, Inc # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 2542b7f..a3ae8b2 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -1,7 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2018 Marek Vasut <marex(a)denx.de> # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile index 65d1cd6..81764b4 100644 --- a/drivers/clk/aspeed/Makefile +++ b/drivers/clk/aspeed/Makefile @@ -1,7 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (c) 2016 Google, Inc # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile index 9132dcc..63ab573 100644 --- a/drivers/clk/owl/Makefile +++ b/drivers/clk/owl/Makefile @@ -1,3 +1,3 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_CLK_S900) += clk_s900.o diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index eae0ef6..41cfb7a 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -1,8 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (c) 2017 Rockchip Electronics Co., Ltd # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o obj-$(CONFIG_ROCKCHIP_RK3128) += clk_rk3128.o diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index 0fcc5205..7f1a318 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -1,6 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# # Copyright (c) 2016, NVIDIA CORPORATION. # -# SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_TEGRA_CAR_CLOCK) += tegra-car-clk.o obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile index f452ee4..858b037 100644 --- a/drivers/cpu/Makefile +++ b/drivers/cpu/Makefile @@ -1,9 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (c) 2015 Google, Inc # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. # -# SPDX-License-Identifier: GPL-2.0+ -# + obj-$(CONFIG_CPU) += cpu-uclass.o obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o diff --git a/drivers/fastboot/Makefile b/drivers/fastboot/Makefile index a242156..048af5a 100644 --- a/drivers/fastboot/Makefile +++ b/drivers/fastboot/Makefile @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0+ +# SPDX-License-Identifier: GPL-2.0+ obj-y += fb_common.o obj-y += fb_getvar.o diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 243ff6f..cd23769 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -1,6 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# # Copyright (c) 2016, NVIDIA CORPORATION. # -# SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 5fe642b..b7bb96a 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -1,7 +1,7 @@ -/* +// SPDX-License-Identifier: GPL-2.0 + /* * Copyright (C) 2018 Intel Corporation <www.intel.com> * - * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> #include <dm.h> diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile index 6b5248f..ab5a7b2 100644 --- a/drivers/net/pfe_eth/Makefile +++ b/drivers/net/pfe_eth/Makefile @@ -1,7 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# # Copyright 2015-2016 Freescale Semiconductor, Inc. # Copyright 2017 NXP # -# SPDX-License-Identifier:GPL-2.0+ # Layerscape PFE driver obj-y += pfe_cmd.o \ diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile index 5ed2702..e709fca 100644 --- a/drivers/phy/allwinner/Makefile +++ b/drivers/phy/allwinner/Makefile @@ -1,6 +1,6 @@ -# Copyright (C) 2016 Amarula Solutions +# SPDX-License-Identifier: GPL-2.0+ # -# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2016 Amarula Solutions # obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 6bdaa17..15926be 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -1,6 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# # Copyright (c) 2016, NVIDIA CORPORATION. # -# SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 16208af..a5f5683 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -1,9 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2015 Samsung Electronics # Przemyslaw Marczak <p.marczak(a)samsung.com> # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 4ad3604..cfba57f 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -1,9 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (c) 2015 Google, Inc # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_RAM) += ram-uclass.o obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o obj-$(CONFIG_SANDBOX) += sandbox_ram.o diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index 1a1e557..5df1960 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -1,8 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH # -# SPDX-License-Identifier: GPL-2.0+ -# obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o obj-$(CONFIG_ROCKCHIP_RK3128) = sdram_rk3128.o diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index abdfa0c..f452087 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -1,6 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# # Copyright (c) 2016, NVIDIA CORPORATION. # -# SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_DM_RESET) += reset-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile index aee7e32..55e0547 100644 --- a/drivers/usb/common/Makefile +++ b/drivers/usb/common/Makefile @@ -1,6 +1,6 @@ -# (C) Copyright 2016 Freescale Semiconductor, Inc. +# SPDX-License-Identifier: GPL-2.0+ # -# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2016 Freescale Semiconductor, Inc. # obj-$(CONFIG_DM_USB) += common.o diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index ca63eac..56c9fd6 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 /* * Generic DWC3 Glue layer * diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra124/Makefile index 4287b9a..a378382 100644 --- a/drivers/video/tegra124/Makefile +++ b/drivers/video/tegra124/Makefile @@ -1,8 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ # # Copyright (c) 2014 Google, Inc # -# SPDX-License-Identifier: GPL-2.0+ -# obj-y += display.o obj-y += dp.o -- 2.7.4

3 2

[U-Boot] [PATCH 01/14] mips: Add in_le32(), out_le32() etc IO accessor functions
by Stefan Roese 28 Oct '18

28 Oct '18

in_le32() and out_le32() are needed for the bootcounter support. So lets implement these accessor functions for MIPS as well. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> --- arch/mips/include/asm/io.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 957442effd..a750f6c0e4 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -391,6 +391,27 @@ __BUILDIO(q, u64) #define readq readq #define writeq writeq +/* in_le32(), out_le32() and friends */ +#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) +#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a)) + +#define out_le64(a,v) out_arch(q,le64,a,v) +#define out_le32(a,v) out_arch(l,le32,a,v) +#define out_le16(a,v) out_arch(w,le16,a,v) + +#define in_le64(a) in_arch(q,le64,a) +#define in_le32(a) in_arch(l,le32,a) +#define in_le16(a) in_arch(w,le16,a) + +#define out_be32(a,v) out_arch(l,be32,a,v) +#define out_be16(a,v) out_arch(w,be16,a,v) + +#define in_be32(a) in_arch(l,be32,a) +#define in_be16(a) in_arch(w,be16,a) + +#define out_8(a,v) __raw_writeb(v,a) +#define in_8(a) __raw_readb(a) + #define __BUILD_MEMORY_STRING(bwlq, type) \ \ static inline void writes##bwlq(volatile void __iomem *mem, \ -- 2.19.1

3 18

[U-Boot] [PATCH] net: Add MT76xx ethernet driver
by Stefan Roese 28 Oct '18

28 Oct '18

This patch adds ethernet support for the Mediatek MT76xx SoC, including a minimum setup of the integrated switch. This driver is loosly based on the driver version included in this MediaTek github repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Tested on the MT7688 LinkIt smart-gateway and on the Gardena-smart-gateway. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/mt76xx-eth.c | 648 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 656 insertions(+) create mode 100644 drivers/net/mt76xx-eth.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5441da47d1..ed73f21a59 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -227,6 +227,13 @@ config MACB_ZYNQ The Cadence MACB ethernet interface was used on Zynq platform. Say Y to enable support for the MACB/GEM in Zynq chip. +config MT76XX_ETH + bool "MediaTek MT76xx Ethernet Interface" + depends on ARCH_MT7620 + help + The MediaTek MT76xx ethernet interface is used on MT7688 + based boards. + config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" depends on DM_ETH && DM_PCI diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878071..05189514b7 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o +obj-$(CONFIG_MT76XX_ETH) += mt76xx-eth.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o diff --git a/drivers/net/mt76xx-eth.c b/drivers/net/mt76xx-eth.c new file mode 100644 index 0000000000..a1a0cdad82 --- /dev/null +++ b/drivers/net/mt76xx-eth.c @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MediaTek ethernet IP driver for U-Boot + * + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + */ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <miiphy.h> +#include <net.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <linux/err.h> + +/* System controller register */ +#define MT76XX_RSTCTRL_REG 0x34 +#define RSTCTRL_EPHY_RST BIT(24) + +#define MT76XX_AGPIO_CFG_REG 0x3c +#define MT7628_EPHY_GPIO_AIO_EN GENMASK(20, 17) +#define MT7628_EPHY_P0_DIS BIT(16) + +#define MT76XX_GPIO2_MODE_REG 0x64 + +/* Ethernet frame engine register */ +#define PDMA_RELATED 0x0800 + +#define TX_BASE_PTR0 (PDMA_RELATED + 0x000) +#define TX_MAX_CNT0 (PDMA_RELATED + 0x004) +#define TX_CTX_IDX0 (PDMA_RELATED + 0x008) +#define TX_DTX_IDX0 (PDMA_RELATED + 0x00c) + +#define RX_BASE_PTR0 (PDMA_RELATED + 0x100) +#define RX_MAX_CNT0 (PDMA_RELATED + 0x104) +#define RX_CALC_IDX0 (PDMA_RELATED + 0x108) + +#define PDMA_GLO_CFG (PDMA_RELATED + 0x204) +#define PDMA_RST_IDX (PDMA_RELATED + 0x208) +#define DLY_INT_CFG (PDMA_RELATED + 0x20c) + +#define SDM_RELATED 0x0c00 + +#define SDM_MAC_ADRL (SDM_RELATED + 0x0c) /* MAC address LSB */ +#define SDM_MAC_ADRH (SDM_RELATED + 0x10) /* MAC Address MSB */ + +#define RST_DTX_IDX0 BIT(0) +#define RST_DRX_IDX0 BIT(16) + +#define TX_DMA_EN BIT(0) +#define TX_DMA_BUSY BIT(1) +#define RX_DMA_EN BIT(2) +#define RX_DMA_BUSY BIT(3) +#define TX_WB_DDONE BIT(6) + +/* Ethernet switch register */ +#define MT76XX_SWITCH_FCT0 0x0008 +#define MT76XX_SWITCH_PFC1 0x0014 +#define MT76XX_SWITCH_FPA 0x0084 +#define MT76XX_SWITCH_SOCPC 0x008c +#define MT76XX_SWITCH_POC0 0x0090 +#define MT76XX_SWITCH_POC2 0x0098 +#define MT76XX_SWITCH_SGC 0x009c +#define MT76XX_SWITCH_PCR0 0x00c0 +#define MT76XX_SWITCH_PCR1 0x00c4 +#define MT76XX_SWITCH_FPA1 0x00c8 +#define MT76XX_SWITCH_FCT2 0x00cc +#define MT76XX_SWITCH_SGC2 0x00e4 +#define MT76XX_SWITCH_BMU_CTRL 0x0110 + +/* rxd2 */ +#define RX_DMA_DONE BIT(31) +#define RX_DMA_LSO BIT(30) +#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) +#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) +#define RX_DMA_TAG BIT(15) +/* rxd3 */ +#define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff) +#define RX_DMA_VID(_x) ((_x) & 0xffff) +/* rxd4 */ +#define RX_DMA_L4VALID BIT(30) + +struct fe_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +} __packed __aligned(4); + +#define TX_DMA_BUF_LEN 0x3fff +#define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16) +#define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16) +#define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) +#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN) +#define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) +#define TX_DMA_LS1 BIT(14) +#define TX_DMA_LS0 BIT(30) +#define TX_DMA_DONE BIT(31) + +#define TX_DMA_INS_VLAN_MT7621 BIT(16) +#define TX_DMA_INS_VLAN BIT(7) +#define TX_DMA_INS_PPPOE BIT(12) +#define TX_DMA_QN(_x) ((_x) << 16) +#define TX_DMA_PN(_x) ((_x) << 24) +#define TX_DMA_QN_MASK TX_DMA_QN(0x7) +#define TX_DMA_PN_MASK TX_DMA_PN(0x7) +#define TX_DMA_UDF BIT(20) +#define TX_DMA_CHKSUM (0x7 << 29) +#define TX_DMA_TSO BIT(28) + +struct fe_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +} __packed __aligned(4); + +#define NUM_RX_DESC 256 +#define NUM_TX_DESC 4 + +#define PADDING_LENGTH 60 + +#define MTK_QDMA_PAGE_SIZE 2048 + +#define CONFIG_MDIO_TIMEOUT 100 +#define CONFIG_DMA_STOP_TIMEOUT 100 +#define CONFIG_TX_DMA_TIMEOUT 100 + +#define LINK_DELAY_TIME 500 /* 500 ms */ +#define LINK_TIMEOUT 10000 /* 10 seconds */ + +struct mt76xx_eth_dev { + void __iomem *base; /* frame engine base address */ + void __iomem *eth_sw_base; /* switch base address */ + void __iomem *sysctrl_base; /* system-controller base address */ + + struct mii_dev *bus; + + struct fe_tx_dma *tx_ring; + struct fe_rx_dma *rx_ring; + + u8 *rx_buf[NUM_RX_DESC]; + + /* Point to the next RXD DMA wants to use in RXD Ring0 */ + int rx_dma_idx; + /* Point to the next TXD in TXD Ring0 CPU wants to use */ + int tx_dma_idx; +}; + +static int mdio_wait_read(struct mt76xx_eth_dev *priv, u32 mask, bool mask_set) +{ + void __iomem *base = priv->eth_sw_base; + int timeout = CONFIG_MDIO_TIMEOUT; + int start; + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (mask_set) { + if (readl(base + MT76XX_SWITCH_PCR1) & mask) + return 0; + } else { + if (!(readl(base + MT76XX_SWITCH_PCR1) & mask)) + return 0; + } + } + + printf("MDIO operation timeout!\n"); + + return -ETIMEDOUT; +} + +static int mii_mgr_read(struct mt76xx_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 *read_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 status = 0; + u32 ret; + + *read_data = 0xffff; + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, BIT(1), false); + if (ret) + return ret; + + writel(BIT(14) | (phy_register << 8) | phy_addr, + base + MT76XX_SWITCH_PCR0); + + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, BIT(1), true); + if (ret) + return ret; + + status = readl(base + MT76XX_SWITCH_PCR1); + *read_data = (u32)(status >> 16); + + return 0; +} + +static int mii_mgr_write(struct mt76xx_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 write_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 data; + int ret; + + /* Make sure previous write operation is complete */ + ret = mdio_wait_read(priv, BIT(0), false); + if (ret) + return ret; + + data = (write_data & 0xffff) << 16; + data |= (phy_register << 8) | phy_addr; + data |= BIT(13); + writel(data, base + MT76XX_SWITCH_PCR0); + + return mdio_wait_read(priv, BIT(0), true); +} + +static int mt76xx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + u32 val; + int ret; + + ret = mii_mgr_read(bus->priv, addr, reg, &val); + if (ret) + return ret; + + return val; +} + +static int mt76xx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) +{ + return mii_mgr_write(bus->priv, addr, reg, value); +} + +static void mt7628_ephy_init(struct mt76xx_eth_dev *priv) +{ + int i; + + mii_mgr_write(priv, 0, 31, 0x2000); /* change G2 page */ + mii_mgr_write(priv, 0, 26, 0x0000); + + for (i = 0; i < 5; i++) { + mii_mgr_write(priv, i, 31, 0x8000); /*change L0 page */ + mii_mgr_write(priv, i, 0, 0x3100); + + /* EEE disable */ + mii_mgr_write(priv, i, 30, 0xa000); + mii_mgr_write(priv, i, 31, 0xa000); /* change L2 page */ + mii_mgr_write(priv, i, 16, 0x0606); + mii_mgr_write(priv, i, 23, 0x0f0e); + mii_mgr_write(priv, i, 24, 0x1610); + mii_mgr_write(priv, i, 30, 0x1f15); + mii_mgr_write(priv, i, 28, 0x6111); + } + + /* 100Base AOI setting */ + mii_mgr_write(priv, 0, 31, 0x5000); /* change G5 page */ + mii_mgr_write(priv, 0, 19, 0x004a); + mii_mgr_write(priv, 0, 20, 0x015a); + mii_mgr_write(priv, 0, 21, 0x00ee); + mii_mgr_write(priv, 0, 22, 0x0033); + mii_mgr_write(priv, 0, 23, 0x020a); + mii_mgr_write(priv, 0, 24, 0x0000); + mii_mgr_write(priv, 0, 25, 0x024a); + mii_mgr_write(priv, 0, 26, 0x035a); + mii_mgr_write(priv, 0, 27, 0x02ee); + mii_mgr_write(priv, 0, 28, 0x0233); + mii_mgr_write(priv, 0, 29, 0x000a); + mii_mgr_write(priv, 0, 30, 0x0000); + + /* Fix EPHY idle state abnormal behavior */ + mii_mgr_write(priv, 0, 31, 0x4000); /* change G4 page */ + mii_mgr_write(priv, 0, 29, 0x000d); + mii_mgr_write(priv, 0, 30, 0x0500); +} + +static void rt305x_esw_init(struct mt76xx_eth_dev *priv) +{ + void __iomem *sysctrl_base = priv->sysctrl_base; + void __iomem *base = priv->eth_sw_base; + + /* + * FC_RLS_TH=200, FC_SET_TH=160 + * DROP_RLS=120, DROP_SET_TH=80 + */ + writel(0xc8a07850, base + MT76XX_SWITCH_FCT0); + writel(0x00000000, base + MT76XX_SWITCH_SGC2); + writel(0x00405555, base + MT76XX_SWITCH_PFC1); + writel(0x00007f7f, base + MT76XX_SWITCH_POC0); + writel(0x00007f7f, base + MT76XX_SWITCH_POC2); /* disable VLAN */ + writel(0x0002500c, base + MT76XX_SWITCH_FCT2); + /* hashing algorithm=XOR48, aging interval=300sec */ + writel(0x0008a301, base + MT76XX_SWITCH_SGC); + writel(0x02404040, base + MT76XX_SWITCH_SOCPC); + + /* Ext PHY Addr=0x1f */ + writel(0x3f502b28, base + MT76XX_SWITCH_FPA1); + writel(0x00000000, base + MT76XX_SWITCH_FPA); + /* 1us cycle number=125 (FE's clock=125Mhz) */ + writel(0x7d000000, base + MT76XX_SWITCH_BMU_CTRL); + + /* Configure analog GPIO setup */ + clrsetbits_le32(sysctrl_base + MT76XX_AGPIO_CFG_REG, + MT7628_EPHY_P0_DIS, MT7628_EPHY_GPIO_AIO_EN); + + /* Reset PHY */ + setbits_le32(sysctrl_base + MT76XX_RSTCTRL_REG, RSTCTRL_EPHY_RST); + clrbits_le32(sysctrl_base + MT76XX_RSTCTRL_REG, RSTCTRL_EPHY_RST); + mdelay(10); + + /* Set P0 EPHY LED mode */ + clrsetbits_le32(sysctrl_base + MT76XX_GPIO2_MODE_REG, + 0x0ffc0ffc, 0x05540554); + mdelay(10); + + mt7628_ephy_init(priv); +} + +static void eth_dma_start(struct mt76xx_eth_dev *priv) +{ + void __iomem *base = priv->base; + + setbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); +} + +static void eth_dma_stop(struct mt76xx_eth_dev *priv) +{ + void __iomem *base = priv->base; + int timeout = CONFIG_DMA_STOP_TIMEOUT; + int start; + u32 val; + + clrbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); + + /* Wait for DMA to stop */ + start = get_timer(0); + while (get_timer(start) < timeout) { + val = readl(base + PDMA_GLO_CFG); + if ((val & (RX_DMA_BUSY | TX_DMA_BUSY)) == 0) + return; + } + + printf("DMA stop timeout error!\n"); +} + +static int mt76xx_eth_write_hwaddr(struct udevice *dev) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u8 *addr = ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr; + u32 val; + u16 tmp; + + /* Set MAC address. */ + tmp = (u16)addr[0]; + val = (tmp << 8) | addr[1]; + + writel(val, base + SDM_MAC_ADRH); + + tmp = (u16)addr[2]; + val = (tmp << 8) | addr[3]; + val = val << 16; + tmp = (u16)addr[4]; + val |= (tmp << 8) | addr[5]; + writel(val, base + SDM_MAC_ADRL); + + return 0; +} + +static int mt76xx_eth_send(struct udevice *dev, void *packet, int length) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + int ret; + int idx; + int i; + + idx = priv->tx_dma_idx; + + /* Pad message to a minimum length */ + if (length < PADDING_LENGTH) { + char *p = (char *)packet; + + for (i = 0; i < PADDING_LENGTH - length; i++) + p[length + i] = 0; + length = PADDING_LENGTH; + } + + /* Check if buffer is ready for next TX DMA */ + ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true, + CONFIG_TX_DMA_TIMEOUT, false); + if (ret) { + printf("TX: DMA still busy on buffer %d\n", idx); + return ret; + } + + flush_dcache_range((u32)packet, (u32)packet + length); + + priv->tx_ring[idx].txd1 = CPHYSADDR(packet); + priv->tx_ring[idx].txd2 |= TX_DMA_PLEN0(length); + priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE; + + idx = (idx + 1) % NUM_TX_DESC; + + /* Make sure the writes exceuted at this place */ + wmb(); + writel(idx, base + TX_CTX_IDX0); + + priv->tx_dma_idx = idx; + + return 0; +} + +static int mt76xx_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u32 rxd_info; + int length; + int idx; + + idx = priv->rx_dma_idx; + + rxd_info = priv->rx_ring[idx].rxd2; + if ((rxd_info & RX_DMA_DONE) == 0) + return -EAGAIN; + + length = RX_DMA_GET_PLEN0(priv->rx_ring[idx].rxd2); + if (length == 0 || length > MTK_QDMA_PAGE_SIZE) { + printf("%s: invalid length (%d bytes)\n", __func__, length); + return -EIO; + } + + *packetp = priv->rx_buf[idx]; + invalidate_dcache_range((u32)*packetp, (u32)*packetp + length); + + priv->rx_ring[idx].rxd4 = 0; + priv->rx_ring[idx].rxd2 = RX_DMA_LSO; + + /* Make sure the writes exceuted at this place */ + wmb(); + + /* Move point to next RXD which wants to alloc */ + writel(idx, base + RX_CALC_IDX0); + + /* Update to Next packet point that was received */ + idx = (idx + 1) % NUM_RX_DESC; + + priv->rx_dma_idx = idx; + + return length; +} + +static int phy_link_up(struct mt76xx_eth_dev *priv) +{ + u32 val; + + mii_mgr_read(priv, 0x00, MII_BMSR, &val); + return !!(val & BMSR_LSTATUS); +} + +static int mt76xx_eth_start(struct udevice *dev) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + uchar packet[MTK_QDMA_PAGE_SIZE]; + uchar *packetp; + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + memset((void *)&priv->rx_ring[i], 0, sizeof(priv->rx_ring[0])); + priv->rx_ring[i].rxd2 |= RX_DMA_LSO; + priv->rx_ring[i].rxd1 = CPHYSADDR(priv->rx_buf[i]); + } + + for (i = 0; i < NUM_TX_DESC; i++) { + memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0])); + priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE; + priv->tx_ring[i].txd4 = TX_DMA_PN(1); + } + + priv->rx_dma_idx = 0; + priv->tx_dma_idx = 0; + + /* Make sure the writes exceuted at this place */ + wmb(); + + /* disable delay interrupt */ + writel(0, base + DLY_INT_CFG); + + clrbits_le32(base + PDMA_GLO_CFG, 0xffff0000); + + /* Tell the adapter where the TX/RX rings are located. */ + writel(CPHYSADDR(&priv->rx_ring[0]), base + RX_BASE_PTR0); + writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0); + + writel(NUM_RX_DESC, base + RX_MAX_CNT0); + writel(NUM_TX_DESC, base + TX_MAX_CNT0); + + writel(priv->tx_dma_idx, base + TX_CTX_IDX0); + writel(RST_DTX_IDX0, base + PDMA_RST_IDX); + + writel(NUM_RX_DESC - 1, base + RX_CALC_IDX0); + writel(RST_DRX_IDX0, base + PDMA_RST_IDX); + + /* Make sure the writes exceuted at this place */ + wmb(); + eth_dma_start(priv); + + /* Check if link is not up yet */ + if (!phy_link_up(priv)) { + /* Wait for link to come up */ + + printf("Waiting for link to come up ."); + for (i = 0; i < (LINK_TIMEOUT / LINK_DELAY_TIME); i++) { + mdelay(LINK_DELAY_TIME); + if (phy_link_up(priv)) { + mdelay(100); /* Ensure all is ready */ + break; + } + + printf("."); + } + + if (phy_link_up(priv)) + printf(" done\n"); + else + printf(" timeout! Trying anyways\n"); + } + + /* + * The integrated switch seems to queue some received ethernet + * packets in some FIFO. Lets read the already queued packets + * out by using the reveice routine, so that these old messages + * are dropped before the new xfer starts. + */ + packetp = &packet[0]; + while (mt76xx_eth_recv(dev, 0, &packetp) != -EAGAIN) + ; + + return 0; +} + +static void mt76xx_eth_stop(struct udevice *dev) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + + eth_dma_stop(priv); +} + +static int mt76xx_eth_probe(struct udevice *dev) +{ + struct mt76xx_eth_dev *priv = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + struct mii_dev *bus; + fdt_addr_t base; + fdt_size_t size; + int node; + int ret; + int i; + + /* Save frame-engine base address for later use */ + priv->base = dev_remap_addr_index(dev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* Save switch base address for later use */ + priv->eth_sw_base = dev_remap_addr_index(dev, 1); + if (IS_ERR(priv->eth_sw_base)) + return PTR_ERR(priv->eth_sw_base); + + /* Get system controller base address */ + node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc"); + if (node < 0) + return -FDT_ERR_NOTFOUND; + + base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg", + 0, &size, true); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->sysctrl_base = ioremap_nocache(base, size); + + /* Put rx and tx rings into KSEG1 area (uncached) */ + priv->tx_ring = (struct fe_tx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->tx_ring) * NUM_TX_DESC)); + priv->rx_ring = (struct fe_rx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->rx_ring) * NUM_RX_DESC)); + + for (i = 0; i < NUM_RX_DESC; i++) + priv->rx_buf[i] = memalign(PKTALIGN, MTK_QDMA_PAGE_SIZE); + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = mt76xx_mdio_read; + bus->write = mt76xx_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + bus->priv = (void *)priv; + + ret = mdio_register(bus); + if (ret) + return ret; + + /* Switch configuration */ + rt305x_esw_init(priv); + + return 0; +} + +static const struct eth_ops mt76xx_eth_ops = { + .start = mt76xx_eth_start, + .send = mt76xx_eth_send, + .recv = mt76xx_eth_recv, + .stop = mt76xx_eth_stop, + .write_hwaddr = mt76xx_eth_write_hwaddr, +}; + +static const struct udevice_id mt76xx_eth_ids[] = { + { .compatible = "mediatek,mt7622-eth" }, + { } +}; + +U_BOOT_DRIVER(mt76xx_eth) = { + .name = "mt76xx_eth", + .id = UCLASS_ETH, + .of_match = mt76xx_eth_ids, + .probe = mt76xx_eth_probe, + .ops = &mt76xx_eth_ops, + .priv_auto_alloc_size = sizeof(struct mt76xx_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; -- 2.19.0

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