October 2018 - U-Boot

[U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
by Stefan Roese 26 Oct '18

26 Oct '18

Some SPI NOR chips only support 4-byte mode addressing. Here the default 3-byte mode does not work and leads to incorrect accesses. This patch now reads the 4-byte mode status bit (in this case in the CR register of the Macronix SPI NOR) and configures the SPI transfers accordingly. This was noticed on the LinkIt Smart 7688 modul, which is equipped with an Macronix MX25L25635F device. But this device does *NOT* support switching to 3-byte mode via the EX4B command. This should also work when the bootrom configures the SPI flash to 4-byte mode and runs U-Boot after this. U-Boot should dectect this mode (if the 4-byte mode detection is available for this chip) and use the correct OPs in this case. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Jagan Teki <jagan(a)openedev.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- v3: - Rebased on latest version (merge conflict because of new patches from Simon Glass) - Added Tested-by tag from Simon Goldschmidt v2: - Integrated STMICRO 4-byte detection from Simon drivers/mtd/spi/sf_internal.h | 3 +- drivers/mtd/spi/spi_flash.c | 131 ++++++++++++++++++++++++++++------ include/spi_flash.h | 5 ++ 3 files changed, 118 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 4f63cacc64..eb076401d1 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -26,7 +26,8 @@ enum spi_nor_option_flags { }; #define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_4B_ADDR_LEN 4 +#define SPI_FLASH_CMD_MAX_LEN (1 + SPI_FLASH_4B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 /* CFI Manufacture ID's */ diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 9230060364..b22eea2d1c 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -20,12 +20,19 @@ #include "sf_internal.h" -static void spi_flash_addr(u32 addr, u8 *cmd) +static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd) { /* cmd[0] is actual command */ - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr >> 0; + if (flash->in_4byte_mode) { + cmd[1] = addr >> 24; + cmd[2] = addr >> 16; + cmd[3] = addr >> 8; + cmd[4] = addr >> 0; + } else { + cmd[1] = addr >> 16; + cmd[2] = addr >> 8; + cmd[3] = addr >> 0; + } } static int read_sr(struct spi_flash *flash, u8 *rs) @@ -110,6 +117,72 @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif +#if defined(CONFIG_SPI_FLASH_MACRONIX) +static bool flash_in_4byte_mode_macronix(struct spi_flash *flash) +{ + int ret; + u8 cr; + u8 cmd; + + cmd = 0x15; /* Macronix: read configuration register RDCR */ + ret = spi_flash_read_common(flash, &cmd, 1, &cr, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return false; + } + + /* Return true, if 4-byte mode is enabled */ + if (cr & BIT(5)) + return true; + + return false; +} +#else +static bool flash_in_4byte_mode_macronix(struct spi_flash *flash) +{ + return false; +} +#endif + +#if defined(CONFIG_SPI_FLASH_STMICRO) +static bool flash_in_4byte_mode_stmicro(struct spi_flash *flash) +{ + int ret; + u8 fsr; + u8 cmd; + + cmd = 0x70; /* STMicro/Micron: read flag status register */ + ret = spi_flash_read_common(flash, &cmd, 1, &fsr, 1); + if (ret < 0) { + debug("SF: fail to read config register\n"); + return false; + } + + /* Return true, if 4-byte mode is enabled */ + if (fsr & BIT(0)) + return true; + + return false; +} +#else +static bool flash_in_4byte_mode_stmicro(struct spi_flash *flash) +{ + return false; +} +#endif + +static bool flash_in_4byte_mode(struct spi_flash *flash, + const struct spi_flash_info *info) +{ + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) + return flash_in_4byte_mode_macronix(flash); + + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO) + return flash_in_4byte_mode_stmicro(flash); + + return false; +} + #ifdef CONFIG_SPI_FLASH_BAR /* * This "clean_bar" is necessary in a situation when one was accessing @@ -314,7 +387,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { u32 erase_size, erase_addr; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; int ret = -1; erase_size = flash->erase_size; @@ -344,12 +417,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) if (ret < 0) return ret; #endif - spi_flash_addr(erase_addr, cmd); + spi_flash_addr(flash, erase_addr, cmd); debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], erase_addr); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); + ret = spi_flash_write_common(flash, cmd, flash->cmdlen, + NULL, 0); if (ret < 0) { debug("SF: erase failed\n"); break; @@ -373,7 +447,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, unsigned long byte_addr, page_size; u32 write_addr; size_t chunk_len, actual; - u8 cmd[SPI_FLASH_CMD_LEN]; + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; int ret = -1; page_size = flash->page_size; @@ -404,15 +478,15 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, if (spi->max_write_size) chunk_len = min(chunk_len, - spi->max_write_size - sizeof(cmd)); + spi->max_write_size - flash->cmdlen); - spi_flash_addr(write_addr, cmd); + spi_flash_addr(flash, write_addr, cmd); debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), - buf + actual, chunk_len); + ret = spi_flash_write_common(flash, cmd, flash->cmdlen, + buf + actual, chunk_len); if (ret < 0) { debug("SF: write failed\n"); break; @@ -469,9 +543,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, { struct spi_slave *spi = flash->spi; u8 cmdsz; - u32 remain_len, read_len, read_addr; + u64 remain_len; + u32 read_len, read_addr; int bank_sel = 0; int ret = 0; + int shift; /* Handle memory-mapped SPI */ if (flash->memory_map) { @@ -487,7 +563,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return 0; } - cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmdsz = flash->cmdlen + flash->dummy_byte; u8 cmd[cmdsz]; cmd[0] = flash->read_cmd; @@ -504,8 +580,13 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, return log_ret(ret); bank_sel = flash->bank_curr; #endif - remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * - (bank_sel + 1)) - offset; + shift = flash->shift; + if (flash->in_4byte_mode) + shift += 8; + + remain_len = (((u64)SPI_FLASH_16MB_BOUN << shift) * + (bank_sel + 1)) - offset; + if (len < remain_len) read_len = len; else @@ -514,7 +595,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, if (spi->max_read_size) read_len = min(read_len, spi->max_read_size); - spi_flash_addr(read_addr, cmd); + spi_flash_addr(flash, read_addr, cmd); ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { @@ -1155,6 +1236,13 @@ int spi_flash_scan(struct spi_flash *flash) write_sr(flash, sr); } + /* Set default value for cmd length */ + flash->cmdlen = 1 + SPI_FLASH_3B_ADDR_LEN; + if (flash_in_4byte_mode(flash, info)) { + flash->in_4byte_mode = true; + flash->cmdlen = 1 + SPI_FLASH_4B_ADDR_LEN; + } + flash->name = info->name; flash->memory_map = spi->memory_map; @@ -1306,14 +1394,17 @@ int spi_flash_scan(struct spi_flash *flash) print_size(flash->size, ""); if (flash->memory_map) printf(", mapped at %p", flash->memory_map); + if (flash->in_4byte_mode) + printf(" (4-byte mode)"); puts("\n"); #endif #ifndef CONFIG_SPI_FLASH_BAR - if (((flash->dual_flash == SF_SINGLE_FLASH) && - (flash->size > SPI_FLASH_16MB_BOUN)) || + if ((((flash->dual_flash == SF_SINGLE_FLASH) && + (flash->size > SPI_FLASH_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE_FLASH) && - (flash->size > SPI_FLASH_16MB_BOUN << 1))) { + (flash->size > SPI_FLASH_16MB_BOUN << 1))) && + !flash->in_4byte_mode) { puts("SF: Warning - Only lower 16MiB accessible,"); puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); } diff --git a/include/spi_flash.h b/include/spi_flash.h index 0ec98fb55d..b5bc4a85f6 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -36,6 +36,8 @@ struct spi_slave; * @dual_flash: Indicates dual flash memories - dual stacked, parallel * @shift: Flash shift useful in dual parallel * @flags: Indication of spi flash flags + * @in_4byte_mode: True if flash is detected to be in 4-byte mode + * @cmdlen: CMD length (3-byte vs 4-byte mode) * @size: Total flash size * @page_size: Write (page) size * @sector_size: Sector size @@ -69,6 +71,9 @@ struct spi_flash { u8 shift; u16 flags; + bool in_4byte_mode; + int cmdlen; + u32 size; u32 page_size; u32 sector_size; -- 2.19.1

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[U-Boot] sunxi: add custom board
by Giulio Benetti 26 Oct '18

26 Oct '18

Hello Jagan and Maxime, I've looked around a lot, but I can't find a way to use the board/sunxi: http://git.denx.de/?p=u-boot.git;a=tree;f=board/sunxi;h=304ee6b4cc8e075759d… to fit what we need. We have 5 gpios that control the max current setting on current-driver for Backlight biasing shunt kathode resistor, and I don't know where to place the code to set those pins. I would like to avoid to create another new board if possible, since board/sunxi has everything we need to make our board operative. In general, is there some sort of __weak__ hooks to be used to extend an existing board? Because I understand that probably you wouldn't add this code I'm talking about inside board/sunxi. This request is done with idea to upstream patch for this board. Can you help me? Thanks in advance Best regards -- Giulio Benetti CTO MICRONOVA SRL Sede: Via A. Niedda 3 - 35010 Vigonza (PD) Tel. 049/8931563 - Fax 049/8931346 Cod.Fiscale - P.IVA 02663420285 Capitale Sociale € 26.000 i.v. Iscritta al Reg. Imprese di Padova N. 02663420285 Numero R.E.A. 258642

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[U-Boot] [PATCH 00/30] General fixes / cleanup for RISC-V and improvements to qemu-riscv
by Lukas Auer 26 Oct '18

26 Oct '18

This patch series includes general fixes and cleanup for RISC-V. It also adds support for booting Linux on qemu-riscv. At the moment, only single-core systems are supported. Support for multi-core systems will be added with a future patch series. To boot Linux on qemu-riscv, Linux must be compiled into BBL as a payload. BBL must be included in a FIT image and supplied to QEMU with the -kernel parameter. Its location in memory is embedded in the device tree, which QEMU passes to u-boot. To test this, QEMU and riscv-pk (BBL) must be modified. QEMU is modified to add support for loading binary files (FIT images in this case) in addition to ELF files. riscv-pk must be modified to adjust the link address and to ignore the kernel address from the device tree. A pull request for QEMU, which implements this, is available at [1]. A modified version of riscv-pk is available at [2]. [1]: https://github.com/riscv/riscv-qemu/pull/175 [2]: https://github.com/lukasauer/riscv-pk/tree/riscv-u-boot Lukas Auer (30): tools: .gitignore: add prelink-riscv riscv: ignore device tree binaries dts: riscv: update makefile to also clean the RISC-V dts directory riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I riscv: select CONFIG_PHYS_64BIT on RV64I systems riscv: add Kconfig entries for the C and A ISA extensions riscv: set -march and -mabi based on the Kconfig configuration riscv: add Kconfig entries for the code model riscv: move target selection into separate file riscv: enable -fdata-sections riscv: fix use of incorrectly sized variables riscv: make use of the barrier functions from Linux riscv: do not reimplement generic io functions riscv: complete the list of exception codes riscv: treat undefined exception codes as reserved riscv: hang on unhandled exceptions riscv: implement the invalidate_icache_* functions riscv: invalidate the instruction cache before jumping to Linux riscv: fix inconsistent use of spaces and tabs in start.S riscv: align mtvec on a 4-byte boundary riscv: remove CONFIG_INIT_CRITICAL riscv: remove unused labels in start.S riscv: do not blindly modify the mstatus CSR riscv: save hart ID and device tree passed by prior boot stage riscv: qemu: use device tree passed by prior boot stage bdinfo: riscv: print fdt_blob address riscv: qemu: support booting Linux riscv: align bootm implementation with that of other architectures dm: core: add missing prototype for ofnode_read_u64 riscv: qemu: detect and boot the kernel passed by QEMU arch/riscv/Kconfig | 54 ++-- arch/riscv/Kconfig.board | 14 + arch/riscv/Makefile | 16 ++ arch/riscv/config.mk | 7 +- arch/riscv/cpu/cpu.c | 6 + arch/riscv/cpu/start.S | 339 +++++++++++------------- arch/riscv/dts/.gitignore | 1 + arch/riscv/include/asm/barrier.h | 67 +++++ arch/riscv/include/asm/io.h | 48 +--- arch/riscv/include/asm/posix_types.h | 6 +- arch/riscv/include/asm/types.h | 4 + arch/riscv/lib/bootm.c | 93 +++++-- arch/riscv/lib/cache.c | 10 + arch/riscv/lib/interrupts.c | 31 ++- arch/riscv/lib/setjmp.S | 2 +- board/emulation/qemu-riscv/Kconfig | 1 + board/emulation/qemu-riscv/qemu-riscv.c | 35 ++- cmd/bdinfo.c | 2 + configs/ax25-ae350_defconfig | 2 +- configs/qemu-riscv32_defconfig | 4 +- configs/qemu-riscv64_defconfig | 6 +- dts/Makefile | 2 +- include/config_distro_bootcmd.h | 8 +- include/configs/qemu-riscv.h | 13 + include/dm/ofnode.h | 10 + tools/.gitignore | 1 + 26 files changed, 494 insertions(+), 288 deletions(-) create mode 100644 arch/riscv/Kconfig.board create mode 100644 arch/riscv/dts/.gitignore create mode 100644 arch/riscv/include/asm/barrier.h -- 2.17.2

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Re: [U-Boot] [PATCH 26/30] bdinfo: riscv: print fdt_blob address
by Rick Chen 26 Oct '18

26 Oct '18

> > > Print the address of the u-boot device tree. > > > > > > > This is unnecessary as it is already done by 'fdt' command. > > Hi Bin & Lukas At the beginning, I really don't understand the fdt Usage: Maybe I am not so familiar with fdt. I can't find any string about fdt_blob. It seem not describe so clearly After I trace fdt.c, I finally know to get it as below. RISC-V # bdinfo boot_params = 0x00000400 ... baudrate = 38400 bps fdt_blob = 0x3FF0F340 RISC-V # RISC-V # fdt addr -c The address of the fdt is 0x3ff0f340 Usage: fdt addr [-c] <addr> [<length>] - Set the [control] fdt location to <addr> fdt move <fdt> <newaddr> <length> - Copy the fdt to <addr> and make it active fdt resize [<extrasize>] - Resize fdt to size + padding to 4k addr + some optional <extrasize> if needed fdt print <path> [<prop>] - Recursive print starting at <path> fdt list <path> [<prop>] - Print one level starting at <path> fdt get value <var> <path> <prop> - Get <property> and store in <var> fdt get name <var> <path> <index> - Get name of node <index> and store in <var> fdt get addr <var> <path> <prop> - Get start address of <property> and store in <var> fdt get size <var> <path> [<prop>] - Get size of [<property>] or num nodes and store in <var> fdt set <path> <prop> [<val>] - Set <property> [to <val>] fdt mknode <path> <node> - Create a new node after <path> fdt rm <path> [<prop>] - Delete the node or <property> fdt header - Display header info fdt bootcpu <id> - Set boot cpuid fdt memory <addr> <size> - Add/Update memory node fdt rsvmem print - Show current mem reserves fdt rsvmem add <addr> <size> - Add a mem reserve fdt rsvmem delete <index> - Delete a mem reserves fdt chosen [<start> <end>] - Add/update the /chosen branch in the tree <start>/<end> - initrd start/end addr It seem that other arch (MICROBLAZE, ARM) also print fdt_blob in bdinfo cmd. So I think this patch can be accepted. Reviewed-by: Rick Chen <rick(a)andestech.com> Rick > > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > > > --- > > > > > > cmd/bdinfo.c | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > > Regards, > > Bin

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[U-Boot] [PATCH v5] net: Add MT7628 ethernet driver
by Stefan Roese 26 Oct '18

26 Oct '18

This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs (e.g. MT7628 and MT7688), including a minimum setup of the integrated switch. This driver is loosly based on the driver version included in this MediaTek github repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git Tested on the MT7688 LinkIt smart-gateway and on the Gardena-smart-gateway. Signed-off-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Frank Wunderlich <frankwu(a)gmx.de> Cc: Weijie Gao <hackpascal(a)gmail.com> --- v5: - Rename driver and Kconfig and functions names again to avoid mix-up with the MT76xx ARM SoCs v4: - Rename driver and Kconfig to avoid mix-up with the MT76xx ARM SoCs v3: - Add Reviewed-by from Daniel - Address review comments from Joe: - Use more macros / defines instead of magic values, especially in the MDIO functions - Use FIELD_xxx from include/linux/bitfield.h whereever possible - Remove some unreferenced defines - Remove some unnecessary casts - Spelling fixes - Add documentation in doc/device-tree-bindings/net/ v2: - Use wait_for_bit_le32() in more places - Use syscon / regmap to access the system-controller registers needed in this driver instead of finding and mapping this area .../net/mediatek,mt7628-eth.txt | 17 + drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/mt7628-eth.c | 635 ++++++++++++++++++ 4 files changed, 660 insertions(+) create mode 100644 doc/device-tree-bindings/net/mediatek,mt7628-eth.txt create mode 100644 drivers/net/mt7628-eth.c diff --git a/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt b/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt new file mode 100644 index 0000000000..ec97504a3f --- /dev/null +++ b/doc/device-tree-bindings/net/mediatek,mt7628-eth.txt @@ -0,0 +1,17 @@ +* MediaTek Frame Engine Ethernet controller + +Required properties: +- compatible: should be "mediatek,mt7628-eth" +- reg: address and length of the register set for the frame + engine ethernet controller and the internal switch. +- syscon: phandle to the system controller + +Example: + +eth@10100000 { + compatible = "mediatek,mt7628-eth"; + reg = <0x10100000 0x10000 + 0x10110000 0x8000>; + + syscon = <&sysc>; +}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f1f0e2d94e..fba9d7c31c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -227,6 +227,13 @@ config MACB_ZYNQ The Cadence MACB ethernet interface was used on Zynq platform. Say Y to enable support for the MACB/GEM in Zynq chip. +config MT7628_ETH + bool "MediaTek MT7628 Ethernet Interface" + depends on ARCH_MT7620 + help + The MediaTek MT7628 ethernet interface is used on MT7628 and + MT7688 based boards. + config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" depends on DM_ETH && DM_PCI diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 48a2878071..cc0971c614 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o +obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o diff --git a/drivers/net/mt7628-eth.c b/drivers/net/mt7628-eth.c new file mode 100644 index 0000000000..93efea395b --- /dev/null +++ b/drivers/net/mt7628-eth.c @@ -0,0 +1,635 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MediaTek ethernet IP driver for U-Boot + * + * Copyright (C) 2018 Stefan Roese <sr(a)denx.de> + * + * This code is mostly based on the code extracted from this MediaTek + * github repository: + * + * https://github.com/MediaTek-Labs/linkit-smart-uboot.git + * + * I was not able to find a specific license or other developers + * copyrights here, so I can't add them here. + */ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <miiphy.h> +#include <net.h> +#include <regmap.h> +#include <syscon.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <linux/err.h> + +/* System controller register */ +#define MT7628_RSTCTRL_REG 0x34 +#define RSTCTRL_EPHY_RST BIT(24) + +#define MT7628_AGPIO_CFG_REG 0x3c +#define MT7628_EPHY_GPIO_AIO_EN GENMASK(20, 17) +#define MT7628_EPHY_P0_DIS BIT(16) + +#define MT7628_GPIO2_MODE_REG 0x64 + +/* Ethernet frame engine register */ +#define PDMA_RELATED 0x0800 + +#define TX_BASE_PTR0 (PDMA_RELATED + 0x000) +#define TX_MAX_CNT0 (PDMA_RELATED + 0x004) +#define TX_CTX_IDX0 (PDMA_RELATED + 0x008) +#define TX_DTX_IDX0 (PDMA_RELATED + 0x00c) + +#define RX_BASE_PTR0 (PDMA_RELATED + 0x100) +#define RX_MAX_CNT0 (PDMA_RELATED + 0x104) +#define RX_CALC_IDX0 (PDMA_RELATED + 0x108) + +#define PDMA_GLO_CFG (PDMA_RELATED + 0x204) +#define PDMA_RST_IDX (PDMA_RELATED + 0x208) +#define DLY_INT_CFG (PDMA_RELATED + 0x20c) + +#define SDM_RELATED 0x0c00 + +#define SDM_MAC_ADRL (SDM_RELATED + 0x0c) /* MAC address LSB */ +#define SDM_MAC_ADRH (SDM_RELATED + 0x10) /* MAC Address MSB */ + +#define RST_DTX_IDX0 BIT(0) +#define RST_DRX_IDX0 BIT(16) + +#define TX_DMA_EN BIT(0) +#define TX_DMA_BUSY BIT(1) +#define RX_DMA_EN BIT(2) +#define RX_DMA_BUSY BIT(3) +#define TX_WB_DDONE BIT(6) + +/* Ethernet switch register */ +#define MT7628_SWITCH_FCT0 0x0008 +#define MT7628_SWITCH_PFC1 0x0014 +#define MT7628_SWITCH_FPA 0x0084 +#define MT7628_SWITCH_SOCPC 0x008c +#define MT7628_SWITCH_POC0 0x0090 +#define MT7628_SWITCH_POC2 0x0098 +#define MT7628_SWITCH_SGC 0x009c +#define MT7628_SWITCH_PCR0 0x00c0 +#define PCR0_PHY_ADDR GENMASK(4, 0) +#define PCR0_PHY_REG GENMASK(12, 8) +#define PCR0_WT_PHY_CMD BIT(13) +#define PCR0_RD_PHY_CMD BIT(14) +#define PCR0_WT_DATA GENMASK(31, 16) + +#define MT7628_SWITCH_PCR1 0x00c4 +#define PCR1_WT_DONE BIT(0) +#define PCR1_RD_RDY BIT(1) +#define PCR1_RD_DATA GENMASK(31, 16) + +#define MT7628_SWITCH_FPA1 0x00c8 +#define MT7628_SWITCH_FCT2 0x00cc +#define MT7628_SWITCH_SGC2 0x00e4 +#define MT7628_SWITCH_BMU_CTRL 0x0110 + +/* rxd2 */ +#define RX_DMA_DONE BIT(31) +#define RX_DMA_LSO BIT(30) +#define RX_DMA_PLEN0 GENMASK(29, 16) +#define RX_DMA_TAG BIT(15) + +struct fe_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +} __packed __aligned(4); + +#define TX_DMA_PLEN0 GENMASK(29, 16) +#define TX_DMA_LS1 BIT(14) +#define TX_DMA_LS0 BIT(30) +#define TX_DMA_DONE BIT(31) + +#define TX_DMA_INS_VLAN_MT7621 BIT(16) +#define TX_DMA_INS_VLAN BIT(7) +#define TX_DMA_INS_PPPOE BIT(12) +#define TX_DMA_PN GENMASK(26, 24) + +struct fe_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +} __packed __aligned(4); + +#define NUM_RX_DESC 256 +#define NUM_TX_DESC 4 + +#define PADDING_LENGTH 60 + +#define MTK_QDMA_PAGE_SIZE 2048 + +#define CONFIG_MDIO_TIMEOUT 100 +#define CONFIG_DMA_STOP_TIMEOUT 100 +#define CONFIG_TX_DMA_TIMEOUT 100 + +#define LINK_DELAY_TIME 500 /* 500 ms */ +#define LINK_TIMEOUT 10000 /* 10 seconds */ + +struct mt7628_eth_dev { + void __iomem *base; /* frame engine base address */ + void __iomem *eth_sw_base; /* switch base address */ + struct regmap *sysctrl_regmap; /* system-controller reg-map */ + + struct mii_dev *bus; + + struct fe_tx_dma *tx_ring; + struct fe_rx_dma *rx_ring; + + u8 *rx_buf[NUM_RX_DESC]; + + /* Point to the next RXD DMA wants to use in RXD Ring0 */ + int rx_dma_idx; + /* Point to the next TXD in TXD Ring0 CPU wants to use */ + int tx_dma_idx; +}; + +static int mdio_wait_read(struct mt7628_eth_dev *priv, u32 mask, bool mask_set) +{ + void __iomem *base = priv->eth_sw_base; + int ret; + + ret = wait_for_bit_le32(base + MT7628_SWITCH_PCR1, mask, mask_set, + CONFIG_MDIO_TIMEOUT, false); + if (ret) { + printf("MDIO operation timeout!\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static int mii_mgr_read(struct mt7628_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 *read_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 status = 0; + u32 ret; + + *read_data = 0xffff; + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, PCR1_RD_RDY, false); + if (ret) + return ret; + + writel(PCR0_RD_PHY_CMD | + FIELD_PREP(PCR0_PHY_REG, phy_register) | + FIELD_PREP(PCR0_PHY_ADDR, phy_addr), + base + MT7628_SWITCH_PCR0); + + /* Make sure previous read operation is complete */ + ret = mdio_wait_read(priv, PCR1_RD_RDY, true); + if (ret) + return ret; + + status = readl(base + MT7628_SWITCH_PCR1); + *read_data = FIELD_GET(PCR1_RD_DATA, status); + + return 0; +} + +static int mii_mgr_write(struct mt7628_eth_dev *priv, + u32 phy_addr, u32 phy_register, u32 write_data) +{ + void __iomem *base = priv->eth_sw_base; + u32 data; + int ret; + + /* Make sure previous write operation is complete */ + ret = mdio_wait_read(priv, PCR1_WT_DONE, false); + if (ret) + return ret; + + data = FIELD_PREP(PCR0_WT_DATA, write_data) | + FIELD_PREP(PCR0_PHY_REG, phy_register) | + FIELD_PREP(PCR0_PHY_ADDR, phy_addr) | + PCR0_WT_PHY_CMD; + writel(data, base + MT7628_SWITCH_PCR0); + + return mdio_wait_read(priv, PCR1_WT_DONE, true); +} + +static int mt7628_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + u32 val; + int ret; + + ret = mii_mgr_read(bus->priv, addr, reg, &val); + if (ret) + return ret; + + return val; +} + +static int mt7628_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) +{ + return mii_mgr_write(bus->priv, addr, reg, value); +} + +static void mt7628_ephy_init(struct mt7628_eth_dev *priv) +{ + int i; + + mii_mgr_write(priv, 0, 31, 0x2000); /* change G2 page */ + mii_mgr_write(priv, 0, 26, 0x0000); + + for (i = 0; i < 5; i++) { + mii_mgr_write(priv, i, 31, 0x8000); /* change L0 page */ + mii_mgr_write(priv, i, 0, 0x3100); + + /* EEE disable */ + mii_mgr_write(priv, i, 30, 0xa000); + mii_mgr_write(priv, i, 31, 0xa000); /* change L2 page */ + mii_mgr_write(priv, i, 16, 0x0606); + mii_mgr_write(priv, i, 23, 0x0f0e); + mii_mgr_write(priv, i, 24, 0x1610); + mii_mgr_write(priv, i, 30, 0x1f15); + mii_mgr_write(priv, i, 28, 0x6111); + } + + /* 100Base AOI setting */ + mii_mgr_write(priv, 0, 31, 0x5000); /* change G5 page */ + mii_mgr_write(priv, 0, 19, 0x004a); + mii_mgr_write(priv, 0, 20, 0x015a); + mii_mgr_write(priv, 0, 21, 0x00ee); + mii_mgr_write(priv, 0, 22, 0x0033); + mii_mgr_write(priv, 0, 23, 0x020a); + mii_mgr_write(priv, 0, 24, 0x0000); + mii_mgr_write(priv, 0, 25, 0x024a); + mii_mgr_write(priv, 0, 26, 0x035a); + mii_mgr_write(priv, 0, 27, 0x02ee); + mii_mgr_write(priv, 0, 28, 0x0233); + mii_mgr_write(priv, 0, 29, 0x000a); + mii_mgr_write(priv, 0, 30, 0x0000); + + /* Fix EPHY idle state abnormal behavior */ + mii_mgr_write(priv, 0, 31, 0x4000); /* change G4 page */ + mii_mgr_write(priv, 0, 29, 0x000d); + mii_mgr_write(priv, 0, 30, 0x0500); +} + +static void rt305x_esw_init(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->eth_sw_base; + + /* + * FC_RLS_TH=200, FC_SET_TH=160 + * DROP_RLS=120, DROP_SET_TH=80 + */ + writel(0xc8a07850, base + MT7628_SWITCH_FCT0); + writel(0x00000000, base + MT7628_SWITCH_SGC2); + writel(0x00405555, base + MT7628_SWITCH_PFC1); + writel(0x00007f7f, base + MT7628_SWITCH_POC0); + writel(0x00007f7f, base + MT7628_SWITCH_POC2); /* disable VLAN */ + writel(0x0002500c, base + MT7628_SWITCH_FCT2); + /* hashing algorithm=XOR48, aging interval=300sec */ + writel(0x0008a301, base + MT7628_SWITCH_SGC); + writel(0x02404040, base + MT7628_SWITCH_SOCPC); + + /* Ext PHY Addr=0x1f */ + writel(0x3f502b28, base + MT7628_SWITCH_FPA1); + writel(0x00000000, base + MT7628_SWITCH_FPA); + /* 1us cycle number=125 (FE's clock=125Mhz) */ + writel(0x7d000000, base + MT7628_SWITCH_BMU_CTRL); + + /* Configure analog GPIO setup */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_AGPIO_CFG_REG, + MT7628_EPHY_P0_DIS, MT7628_EPHY_GPIO_AIO_EN); + + /* Reset PHY */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, + 0, RSTCTRL_EPHY_RST); + regmap_update_bits(priv->sysctrl_regmap, MT7628_RSTCTRL_REG, + RSTCTRL_EPHY_RST, 0); + mdelay(10); + + /* Set P0 EPHY LED mode */ + regmap_update_bits(priv->sysctrl_regmap, MT7628_GPIO2_MODE_REG, + 0x0ffc0ffc, 0x05540554); + mdelay(10); + + mt7628_ephy_init(priv); +} + +static void eth_dma_start(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->base; + + setbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); +} + +static void eth_dma_stop(struct mt7628_eth_dev *priv) +{ + void __iomem *base = priv->base; + int ret; + + clrbits_le32(base + PDMA_GLO_CFG, TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); + + /* Wait for DMA to stop */ + ret = wait_for_bit_le32(base + PDMA_GLO_CFG, + RX_DMA_BUSY | TX_DMA_BUSY, false, + CONFIG_DMA_STOP_TIMEOUT, false); + if (ret) + printf("DMA stop timeout error!\n"); +} + +static int mt7628_eth_write_hwaddr(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u8 *addr = ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr; + u32 val; + u16 tmp; + + /* Set MAC address. */ + tmp = addr[0]; + val = (tmp << 8) | addr[1]; + writel(val, base + SDM_MAC_ADRH); + + tmp = addr[2]; + val = (tmp << 8) | addr[3]; + val = val << 16; + tmp = addr[4]; + val |= (tmp << 8) | addr[5]; + writel(val, base + SDM_MAC_ADRL); + + return 0; +} + +static int mt7628_eth_send(struct udevice *dev, void *packet, int length) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + int ret; + int idx; + int i; + + idx = priv->tx_dma_idx; + + /* Pad message to a minimum length */ + if (length < PADDING_LENGTH) { + char *p = (char *)packet; + + for (i = 0; i < PADDING_LENGTH - length; i++) + p[length + i] = 0; + length = PADDING_LENGTH; + } + + /* Check if buffer is ready for next TX DMA */ + ret = wait_for_bit_le32(&priv->tx_ring[idx].txd2, TX_DMA_DONE, true, + CONFIG_TX_DMA_TIMEOUT, false); + if (ret) { + printf("TX: DMA still busy on buffer %d\n", idx); + return ret; + } + + flush_dcache_range((u32)packet, (u32)packet + length); + + priv->tx_ring[idx].txd1 = CPHYSADDR(packet); + priv->tx_ring[idx].txd2 &= ~TX_DMA_PLEN0; + priv->tx_ring[idx].txd2 |= FIELD_PREP(TX_DMA_PLEN0, length); + priv->tx_ring[idx].txd2 &= ~TX_DMA_DONE; + + idx = (idx + 1) % NUM_TX_DESC; + + /* Make sure the writes executed at this place */ + wmb(); + writel(idx, base + TX_CTX_IDX0); + + priv->tx_dma_idx = idx; + + return 0; +} + +static int mt7628_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + u32 rxd_info; + int length; + int idx; + + idx = priv->rx_dma_idx; + + rxd_info = priv->rx_ring[idx].rxd2; + if ((rxd_info & RX_DMA_DONE) == 0) + return -EAGAIN; + + length = FIELD_GET(RX_DMA_PLEN0, priv->rx_ring[idx].rxd2); + if (length == 0 || length > MTK_QDMA_PAGE_SIZE) { + printf("%s: invalid length (%d bytes)\n", __func__, length); + return -EIO; + } + + *packetp = priv->rx_buf[idx]; + invalidate_dcache_range((u32)*packetp, (u32)*packetp + length); + + priv->rx_ring[idx].rxd4 = 0; + priv->rx_ring[idx].rxd2 = RX_DMA_LSO; + + /* Make sure the writes executed at this place */ + wmb(); + + /* Move point to next RXD which wants to alloc */ + writel(idx, base + RX_CALC_IDX0); + + /* Update to Next packet point that was received */ + idx = (idx + 1) % NUM_RX_DESC; + + priv->rx_dma_idx = idx; + + return length; +} + +static int phy_link_up(struct mt7628_eth_dev *priv) +{ + u32 val; + + mii_mgr_read(priv, 0x00, MII_BMSR, &val); + return !!(val & BMSR_LSTATUS); +} + +static int mt7628_eth_start(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + void __iomem *base = priv->base; + uchar packet[MTK_QDMA_PAGE_SIZE]; + uchar *packetp; + int i; + + for (i = 0; i < NUM_RX_DESC; i++) { + memset((void *)&priv->rx_ring[i], 0, sizeof(priv->rx_ring[0])); + priv->rx_ring[i].rxd2 |= RX_DMA_LSO; + priv->rx_ring[i].rxd1 = CPHYSADDR(priv->rx_buf[i]); + } + + for (i = 0; i < NUM_TX_DESC; i++) { + memset((void *)&priv->tx_ring[i], 0, sizeof(priv->tx_ring[0])); + priv->tx_ring[i].txd2 = TX_DMA_LS0 | TX_DMA_DONE; + priv->tx_ring[i].txd4 = FIELD_PREP(TX_DMA_PN, 1); + } + + priv->rx_dma_idx = 0; + priv->tx_dma_idx = 0; + + /* Make sure the writes executed at this place */ + wmb(); + + /* disable delay interrupt */ + writel(0, base + DLY_INT_CFG); + + clrbits_le32(base + PDMA_GLO_CFG, 0xffff0000); + + /* Tell the adapter where the TX/RX rings are located. */ + writel(CPHYSADDR(&priv->rx_ring[0]), base + RX_BASE_PTR0); + writel(CPHYSADDR((u32)&priv->tx_ring[0]), base + TX_BASE_PTR0); + + writel(NUM_RX_DESC, base + RX_MAX_CNT0); + writel(NUM_TX_DESC, base + TX_MAX_CNT0); + + writel(priv->tx_dma_idx, base + TX_CTX_IDX0); + writel(RST_DTX_IDX0, base + PDMA_RST_IDX); + + writel(NUM_RX_DESC - 1, base + RX_CALC_IDX0); + writel(RST_DRX_IDX0, base + PDMA_RST_IDX); + + /* Make sure the writes executed at this place */ + wmb(); + eth_dma_start(priv); + + /* Check if link is not up yet */ + if (!phy_link_up(priv)) { + /* Wait for link to come up */ + + printf("Waiting for link to come up ."); + for (i = 0; i < (LINK_TIMEOUT / LINK_DELAY_TIME); i++) { + mdelay(LINK_DELAY_TIME); + if (phy_link_up(priv)) { + mdelay(100); /* Ensure all is ready */ + break; + } + + printf("."); + } + + if (phy_link_up(priv)) + printf(" done\n"); + else + printf(" timeout! Trying anyways\n"); + } + + /* + * The integrated switch seems to queue some received ethernet + * packets in some FIFO. Lets read the already queued packets + * out by using the receive routine, so that these old messages + * are dropped before the new xfer starts. + */ + packetp = &packet[0]; + while (mt7628_eth_recv(dev, 0, &packetp) != -EAGAIN) + ; + + return 0; +} + +static void mt7628_eth_stop(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + + eth_dma_stop(priv); +} + +static int mt7628_eth_probe(struct udevice *dev) +{ + struct mt7628_eth_dev *priv = dev_get_priv(dev); + struct udevice *syscon; + struct mii_dev *bus; + int ret; + int i; + + /* Save frame-engine base address for later use */ + priv->base = dev_remap_addr_index(dev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + /* Save switch base address for later use */ + priv->eth_sw_base = dev_remap_addr_index(dev, 1); + if (IS_ERR(priv->eth_sw_base)) + return PTR_ERR(priv->eth_sw_base); + + /* Get system controller regmap */ + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + "syscon", &syscon); + if (ret) { + pr_err("unable to find syscon device\n"); + return ret; + } + + priv->sysctrl_regmap = syscon_get_regmap(syscon); + if (!priv->sysctrl_regmap) { + pr_err("unable to find regmap\n"); + return -ENODEV; + } + + /* Put rx and tx rings into KSEG1 area (uncached) */ + priv->tx_ring = (struct fe_tx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->tx_ring) * NUM_TX_DESC)); + priv->rx_ring = (struct fe_rx_dma *) + KSEG1ADDR(memalign(ARCH_DMA_MINALIGN, + sizeof(*priv->rx_ring) * NUM_RX_DESC)); + + for (i = 0; i < NUM_RX_DESC; i++) + priv->rx_buf[i] = memalign(PKTALIGN, MTK_QDMA_PAGE_SIZE); + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = mt7628_mdio_read; + bus->write = mt7628_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + bus->priv = (void *)priv; + + ret = mdio_register(bus); + if (ret) + return ret; + + /* Switch configuration */ + rt305x_esw_init(priv); + + return 0; +} + +static const struct eth_ops mt7628_eth_ops = { + .start = mt7628_eth_start, + .send = mt7628_eth_send, + .recv = mt7628_eth_recv, + .stop = mt7628_eth_stop, + .write_hwaddr = mt7628_eth_write_hwaddr, +}; + +static const struct udevice_id mt7628_eth_ids[] = { + { .compatible = "mediatek,mt7628-eth" }, + { } +}; + +U_BOOT_DRIVER(mt7628_eth) = { + .name = "mt7628_eth", + .id = UCLASS_ETH, + .of_match = mt7628_eth_ids, + .probe = mt7628_eth_probe, + .ops = &mt7628_eth_ops, + .priv_auto_alloc_size = sizeof(struct mt7628_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; -- 2.19.1

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[U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs standard 3-byte mode)
by Rajat Srivastava 26 Oct '18

26 Oct '18

Hi Stefan Sorry for top-posting. Why can't we read SFDP parameters from flash and auto-detect 3-byte/4-byte addressing mode? Using address width information we can support both types of flash i.e. flashes supporting 3-byte addressing mode as well as flashes supporting 4-byte addressing mode. I've floated a similar patch in U-boot that reads and parses SFDP parameters from flash and auto-detects its addressing mode. It send commands according to the address width it detects. Please find the patch set at: https://patchwork.ozlabs.org/cover/985326/ https://patchwork.ozlabs.org/patch/985327/ https://patchwork.ozlabs.org/patch/985329/ https://patchwork.ozlabs.org/patch/985328/ Thanks Rajat > -----Original Message----- > From: U-Boot <u-boot-bounces(a)lists.denx.de> On Behalf Of Stefan Roese > Sent: Thursday, October 11, 2018 8:20 PM > To: u-boot(a)lists.denx.de > Cc: Jagan Teki <jagan(a)openedev.com> > Subject: [U-Boot] [PATCH v3] sf: Add auto detection of 4-byte mode (vs > standard 3-byte mode) > > Some SPI NOR chips only support 4-byte mode addressing. Here the > default 3- byte mode does not work and leads to incorrect accesses. > This patch now reads the 4-byte mode status bit (in this case in the > CR register of the Macronix SPI > NOR) and configures the SPI transfers accordingly. > > This was noticed on the LinkIt Smart 7688 modul, which is equipped > with an Macronix MX25L25635F device. But this device does *NOT* > support switching to 3-byte mode via the EX4B command. > > This should also work when the bootrom configures the SPI flash to > 4-byte mode and runs U-Boot after this. U-Boot should dectect this > mode (if the 4-byte mode detection is available for this chip) and use the correct OPs in this case. > > Signed-off-by: Stefan Roese <sr(a)denx.de> > Cc: Jagan Teki <jagan(a)openedev.com> > Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> > --- > v3: > - Rebased on latest version (merge conflict because of new patches > from Simon Glass) > - Added Tested-by tag from Simon Goldschmidt > > v2: > - Integrated STMICRO 4-byte detection from Simon > > drivers/mtd/spi/sf_internal.h | 3 +- > drivers/mtd/spi/spi_flash.c | 131 ++++++++++++++++++++++++++++------ > include/spi_flash.h | 5 ++ > 3 files changed, 118 insertions(+), 21 deletions(-) > > diff --git a/drivers/mtd/spi/sf_internal.h > b/drivers/mtd/spi/sf_internal.h index > 4f63cacc64..eb076401d1 100644 > --- a/drivers/mtd/spi/sf_internal.h > +++ b/drivers/mtd/spi/sf_internal.h > @@ -26,7 +26,8 @@ enum spi_nor_option_flags { }; > > #define SPI_FLASH_3B_ADDR_LEN 3 > -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) > +#define SPI_FLASH_4B_ADDR_LEN 4 > +#define SPI_FLASH_CMD_MAX_LEN (1 + > SPI_FLASH_4B_ADDR_LEN) > #define SPI_FLASH_16MB_BOUN 0x1000000 > > /* CFI Manufacture ID's */ > diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c > index 9230060364..b22eea2d1c 100644 > --- a/drivers/mtd/spi/spi_flash.c > +++ b/drivers/mtd/spi/spi_flash.c > @@ -20,12 +20,19 @@ > > #include "sf_internal.h" > > -static void spi_flash_addr(u32 addr, u8 *cmd) > +static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 > +*cmd) > { > /* cmd[0] is actual command */ > - cmd[1] = addr >> 16; > - cmd[2] = addr >> 8; > - cmd[3] = addr >> 0; > + if (flash->in_4byte_mode) { > + cmd[1] = addr >> 24; > + cmd[2] = addr >> 16; > + cmd[3] = addr >> 8; > + cmd[4] = addr >> 0; > + } else { > + cmd[1] = addr >> 16; > + cmd[2] = addr >> 8; > + cmd[3] = addr >> 0; > + } > } > > static int read_sr(struct spi_flash *flash, u8 *rs) @@ -110,6 +117,72 > @@ static int write_cr(struct spi_flash *flash, u8 wc) } #endif > > +#if defined(CONFIG_SPI_FLASH_MACRONIX) > +static bool flash_in_4byte_mode_macronix(struct spi_flash *flash) { > + int ret; > + u8 cr; > + u8 cmd; > + > + cmd = 0x15; /* Macronix: read configuration register RDCR */ > + ret = spi_flash_read_common(flash, &cmd, 1, &cr, 1); > + if (ret < 0) { > + debug("SF: fail to read config register\n"); > + return false; > + } > + > + /* Return true, if 4-byte mode is enabled */ > + if (cr & BIT(5)) > + return true; > + > + return false; > +} > +#else > +static bool flash_in_4byte_mode_macronix(struct spi_flash *flash) { > + return false; > +} > +#endif > + > +#if defined(CONFIG_SPI_FLASH_STMICRO) static bool > +flash_in_4byte_mode_stmicro(struct spi_flash *flash) { > + int ret; > + u8 fsr; > + u8 cmd; > + > + cmd = 0x70; /* STMicro/Micron: read flag status register */ > + ret = spi_flash_read_common(flash, &cmd, 1, &fsr, 1); > + if (ret < 0) { > + debug("SF: fail to read config register\n"); > + return false; > + } > + > + /* Return true, if 4-byte mode is enabled */ > + if (fsr & BIT(0)) > + return true; > + > + return false; > +} > +#else > +static bool flash_in_4byte_mode_stmicro(struct spi_flash *flash) { > + return false; > +} > +#endif > + > +static bool flash_in_4byte_mode(struct spi_flash *flash, > + const struct spi_flash_info *info) { > + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) > + return flash_in_4byte_mode_macronix(flash); > + > + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO) > + return flash_in_4byte_mode_stmicro(flash); > + > + return false; > +} > + > #ifdef CONFIG_SPI_FLASH_BAR > /* > * This "clean_bar" is necessary in a situation when one was > accessing @@ - > 314,7 +387,7 @@ int spi_flash_write_common(struct spi_flash *flash, > const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, > u32 offset, size_t > len) { > u32 erase_size, erase_addr; > - u8 cmd[SPI_FLASH_CMD_LEN]; > + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; > int ret = -1; > > erase_size = flash->erase_size; > @@ -344,12 +417,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash > *flash, > u32 offset, size_t len) > if (ret < 0) > return ret; > #endif > - spi_flash_addr(erase_addr, cmd); > + spi_flash_addr(flash, erase_addr, cmd); > > debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], > cmd[2], cmd[3], erase_addr); > > - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, > 0); > + ret = spi_flash_write_common(flash, cmd, flash->cmdlen, > + NULL, 0); > if (ret < 0) { > debug("SF: erase failed\n"); > break; > @@ -373,7 +447,7 @@ int spi_flash_cmd_write_ops(struct spi_flash > *flash, > u32 offset, > unsigned long byte_addr, page_size; > u32 write_addr; > size_t chunk_len, actual; > - u8 cmd[SPI_FLASH_CMD_LEN]; > + u8 cmd[SPI_FLASH_CMD_MAX_LEN]; > int ret = -1; > > page_size = flash->page_size; > @@ -404,15 +478,15 @@ int spi_flash_cmd_write_ops(struct spi_flash > *flash, > u32 offset, > > if (spi->max_write_size) > chunk_len = min(chunk_len, > - spi->max_write_size - sizeof(cmd)); > + spi->max_write_size - flash->cmdlen); > > - spi_flash_addr(write_addr, cmd); > + spi_flash_addr(flash, write_addr, cmd); > > debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = > %zu\n", > buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); > > - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), > - buf + actual, chunk_len); > + ret = spi_flash_write_common(flash, cmd, flash->cmdlen, > + buf + actual, chunk_len); > if (ret < 0) { > debug("SF: write failed\n"); > break; > @@ -469,9 +543,11 @@ int spi_flash_cmd_read_ops(struct spi_flash > *flash, > u32 offset, { > struct spi_slave *spi = flash->spi; > u8 cmdsz; > - u32 remain_len, read_len, read_addr; > + u64 remain_len; > + u32 read_len, read_addr; > int bank_sel = 0; > int ret = 0; > + int shift; > > /* Handle memory-mapped SPI */ > if (flash->memory_map) { > @@ -487,7 +563,7 @@ int spi_flash_cmd_read_ops(struct spi_flash > *flash, u32 offset, > return 0; > } > > - cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; > + cmdsz = flash->cmdlen + flash->dummy_byte; > u8 cmd[cmdsz]; > > cmd[0] = flash->read_cmd; > @@ -504,8 +580,13 @@ int spi_flash_cmd_read_ops(struct spi_flash > *flash, > u32 offset, > return log_ret(ret); > bank_sel = flash->bank_curr; > #endif > - remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * > - (bank_sel + 1)) - offset; > + shift = flash->shift; > + if (flash->in_4byte_mode) > + shift += 8; > + > + remain_len = (((u64)SPI_FLASH_16MB_BOUN << shift) * > + (bank_sel + 1)) - offset; > + > if (len < remain_len) > read_len = len; > else > @@ -514,7 +595,7 @@ int spi_flash_cmd_read_ops(struct spi_flash > *flash, u32 offset, > if (spi->max_read_size) > read_len = min(read_len, spi->max_read_size); > > - spi_flash_addr(read_addr, cmd); > + spi_flash_addr(flash, read_addr, cmd); > > ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); > if (ret < 0) { > @@ -1155,6 +1236,13 @@ int spi_flash_scan(struct spi_flash *flash) > write_sr(flash, sr); > } > > + /* Set default value for cmd length */ > + flash->cmdlen = 1 + SPI_FLASH_3B_ADDR_LEN; > + if (flash_in_4byte_mode(flash, info)) { > + flash->in_4byte_mode = true; > + flash->cmdlen = 1 + SPI_FLASH_4B_ADDR_LEN; > + } > + > flash->name = info->name; > flash->memory_map = spi->memory_map; > > @@ -1306,14 +1394,17 @@ int spi_flash_scan(struct spi_flash *flash) > print_size(flash->size, ""); > if (flash->memory_map) > printf(", mapped at %p", flash->memory_map); > + if (flash->in_4byte_mode) > + printf(" (4-byte mode)"); > puts("\n"); > #endif > > #ifndef CONFIG_SPI_FLASH_BAR > - if (((flash->dual_flash == SF_SINGLE_FLASH) && > - (flash->size > SPI_FLASH_16MB_BOUN)) || > + if ((((flash->dual_flash == SF_SINGLE_FLASH) && > + (flash->size > SPI_FLASH_16MB_BOUN)) || > ((flash->dual_flash > SF_SINGLE_FLASH) && > - (flash->size > SPI_FLASH_16MB_BOUN << 1))) { > + (flash->size > SPI_FLASH_16MB_BOUN << 1))) && > + !flash->in_4byte_mode) { > puts("SF: Warning - Only lower 16MiB accessible,"); > puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); > } > diff --git a/include/spi_flash.h b/include/spi_flash.h index > 0ec98fb55d..b5bc4a85f6 100644 > --- a/include/spi_flash.h > +++ b/include/spi_flash.h > @@ -36,6 +36,8 @@ struct spi_slave; > * @dual_flash: Indicates dual flash memories - dual stacked, parallel > * @shift: Flash shift useful in dual parallel > * @flags: Indication of spi flash flags > + * @in_4byte_mode: True if flash is detected to be in 4-byte mode > + * @cmdlen: CMD length (3-byte vs 4-byte mode) > * @size: Total flash size > * @page_size: Write (page) size > * @sector_size: Sector size > @@ -69,6 +71,9 @@ struct spi_flash { > u8 shift; > u16 flags; > > + bool in_4byte_mode; > + int cmdlen; > + > u32 size; > u32 page_size; > u32 sector_size; > -- > 2.19.1 > > _______________________________________________ > U-Boot mailing list > U-Boot(a)lists.denx.de > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flis > ts.de > nx.de%2Flistinfo%2Fu- > boot&data=02%7C01%7Cprabhakar.kushwaha%40nxp.com%7C532d6ed3 > ad764b27306b08d62f88d688%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0 > %7C0%7C636748662097523237&sdata=FpR4s4evDeod9zQPSTMSjigIIAn > mOj50aFqqH21Ofms%3D&reserved=0

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[U-Boot] [PATCH v2 0/6] sunxi: extend SPL header to propagate DRAM size and H6 3GiB DRAM support
by Icenowy Zheng 26 Oct '18

26 Oct '18

This series tries to solve three issues we currently have on Allwinner boards: - The DRAM sizing routine can only cope with power-of-two sized DRAM. - The DRAM sizing routine steps through all DRAM, possibly hitting secure memory. - The SPL header versioning is quite strict and tends to break every time we need to update it. - On some Allwinner SoCs the maximum supported DRAM size of the DRAM controller is bigger than the accessible DRAM size of the CPU. So Andre Przywara adapted something along the lines of semantic versioning[1], where we can add backwards-compatible changes to the SPL header without breaking every tool. The second patch and the third patches introduces the version schema and does necessary refactors, then the fourth and the fifth patches prepare for 3GiB memory support. The sixth patch finally enables the SPL header to store the the DRAM size, and let U-Boot binary check which range is accessible when picking the data. The first patch is a prepare for the other patches, as without it newly introduced code will make H6 SPL overflow, which makes the patchset not possible to test, as the only available 3GiB DRAM device now is the 3GiB version of Pine H64 sample. Andre Przywara (3): sunxi: Extend SPL header versioning sunxi: board.c: refactor SPL header checks sunxi: store DRAM size in SPL header Icenowy Zheng (3): sunxi: disable Pine A64 model detection code on other boards sunxi: map DRAM part with 3G size sunxi: add Kconfig option for the maximum accessible DRAM arch/arm/include/asm/arch-sunxi/spl.h | 22 +++++--- arch/arm/mach-sunxi/Kconfig | 18 +++++++ arch/arm/mach-sunxi/board.c | 2 +- board/sunxi/board.c | 74 ++++++++++++++++++++++----- configs/pine64_plus_defconfig | 1 + 5 files changed, 97 insertions(+), 20 deletions(-) -- 2.18.1

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[U-Boot] [PATCH] MAINTAINERS: add NXP linux team maillist as i.MX reviewer
by Peng Fan 26 Oct '18

26 Oct '18

Add NXP linux team upstream maillist as reviewer Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf8f73f200..b39b6fc739 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -121,6 +121,7 @@ F: drivers/spi/bcmstb_spi.c ARM FREESCALE IMX M: Stefano Babic <sbabic(a)denx.de> M: Fabio Estevam <fabio.estevam(a)nxp.com> +R: NXP Linux Team <linux-imx(a)nxp.com> S: Maintained T: git git://git.denx.de/u-boot-imx.git F: arch/arm/cpu/arm1136/mx*/ -- 2.14.1

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[U-Boot] [PATCH] ARM: dts: fsl-imx8qxp-mek: Move regulator outside "simple-bus"
by Fabio Estevam 26 Oct '18

26 Oct '18

Commit 3c28576bb0f0 ("arm: dts: imx8qxp: fix build warining") fixed the dts warning by removing the unnecessary #address-cells/#size-cells, but the recommendation for regulators is not to place them under "simple-bus", so move the reg_usdhc2_vmmc regulator accordingly. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- arch/arm/dts/fsl-imx8qxp-mek.dts | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts index c14e184..adab494 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek.dts +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -16,18 +16,14 @@ stdout-path = &lpuart0; }; - regulators { - compatible = "simple-bus"; - - reg_usdhc2_vmmc: usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; - off-on-delay = <3480>; - enable-active-high; - }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + off-on-delay = <3480>; + enable-active-high; }; }; -- 2.7.4

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[U-Boot] [PATCH] mx8mq_evk: README: Delete file introduced by mistake
by Fabio Estevam 26 Oct '18

26 Oct '18

board/freescale/mx8mq_evk/README has been introduced by mistake in commit d0dd73974c61 ("imx: add i.MX8QXP MEK board support") Remove it for now as this should be introduced when mx8mq_evk support is in place. Reported-by: Tim Harvey <tharvey(a)gateworks.com> Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- board/freescale/mx8mq_evk/README | 81 ---------------------------------------- 1 file changed, 81 deletions(-) delete mode 100644 board/freescale/mx8mq_evk/README diff --git a/board/freescale/mx8mq_evk/README b/board/freescale/mx8mq_evk/README deleted file mode 100644 index cd7e67e..0000000 --- a/board/freescale/mx8mq_evk/README +++ /dev/null @@ -1,81 +0,0 @@ -U-Boot for the NXP i.MX8MQ EVK board - -Quick Start -=========== - -- Build U-Boot -- Build the ARM Trusted firmware binary -- Get DDR firmware and mkimage tool -- Generate flash.bin using imx-mkimage -- Flash the binary into the SD card -- Boot - -Build U-Boot -============ - -$ make mx8mq_evk_defconfig -$ make - -Get and Build the ARM Trusted firmware -====================================== - -$ git clone https://source.codeaurora.org/external/imx/imx-atf -$ cd imx-atf/ -$ git checkout origin/imx_4.9.51_imx8m_beta -$ make PLAT=imx8mq bl31 - -Get the DDR firmware and mkimage tool -============================== - -$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.2.bin -$ chmod +x firmware-imx-7.2.bin -$ ./firmware-imx-7.2.bin - -Download the imx-mkimage tool: - -$ git clone https://source.codeaurora.org/external/imx/imx-mkimage/ -$ cd imx-mkimage/ -$ git checkout origin/imx_4.9.51_imx8m_beta - - -Generate flash.bin using imx-mkimage -==================================== - -Copy the following binaries to imx-mkimage/iMX8M folder: - -$ cp imx-atf/build/imx8mq/release/bl31.bin imx-mkimage/iMX8M/ -$ cp u-boot/u-boot-nodtb.bin imx-mkimage/iMX8M/ -$ cp u-boot/spl/u-boot-spl.bin imx-mkimage/iMX8M/ -$ cp u-boot/arch/arm/dts/fsl-imx8mq-evk.dtb imx-mkimage/iMX8M/ - -Copy the following firmwares to imx-mkimage/iMX8 folder : - -$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem.bin imx-mkimage/iMX8M/ -$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem.bin imx-mkimage/iMX8M/ -$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem.bin imx-mkimage/iMX8M/ -$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem.bin imx-mkimage/iMX8M/ - -If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M. - -Before generating the flash.bin, transfer the mkimage generated by U-Boot to iMX8M folder: - -$ cp u-boot/tools/mkimage imx-mkimage/iMX8M/ -$ mv imx-mkimage/iMX8M/mkimage imx-mkimage/iMX8M/mkimage_uboot - -$ cd imx-mkimage/ -$ make SOC=iMX8M flash_spl_uboot - -Or for using HDMI: - -$ make SOC=iMX8M flash_hdmi_spl_uboot - -Flash the binary into the SD card -================================= - -Burn the flash.bin binary to SD card offset 33KB: - -$ sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33 - -Boot -==== -Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD. -- 2.7.4

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