October 2018 - U-Boot

[U-Boot] [PATCH 1/1] efi_selftest: rename setup_ok
by Heinrich Schuchardt 25 Oct '18

25 Oct '18

The variable name setup_ok might suggest a boolean with true indicating OK. Let's avoid the misleading name. %s/setup_ok/setup_status/g Suggested-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_selftest/efi_selftest.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/efi_selftest/efi_selftest.c b/lib/efi_selftest/efi_selftest.c index fc7866365d..5b01610eca 100644 --- a/lib/efi_selftest/efi_selftest.c +++ b/lib/efi_selftest/efi_selftest.c @@ -18,7 +18,7 @@ static const struct efi_boot_services *boottime; static const struct efi_runtime_services *runtime; static efi_handle_t handle; static u16 reset_message[] = L"Selftest completed"; -static int *setup_ok; +static int *setup_status; /* * Exit the boot services. @@ -199,8 +199,8 @@ void efi_st_do_tests(const u16 *testname, unsigned int phase, if (test->phase != phase) continue; if (steps & EFI_ST_SETUP) - setup_ok[i] = setup(test, failures); - if (steps & EFI_ST_EXECUTE && setup_ok[i] == EFI_ST_SUCCESS) + setup_status[i] = setup(test, failures); + if (steps & EFI_ST_EXECUTE && setup_status[i] == EFI_ST_SUCCESS) execute(test, failures); if (steps & EFI_ST_TEARDOWN) teardown(test, failures); @@ -278,7 +278,7 @@ efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle, ret = boottime->allocate_pool(EFI_RUNTIME_SERVICES_DATA, sizeof(int) * ll_entry_count(struct efi_unit_test, efi_unit_test), - (void **)&setup_ok); + (void **)&setup_status); if (ret != EFI_SUCCESS) { efi_st_error("Allocate pool failed\n"); return ret; -- 2.19.1

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[U-Boot] [PATCH v11 01/16] test: regmap: Increase size of syscon0 memory
by Mario Six 25 Oct '18

25 Oct '18

The upcoming changes to the regmap interface will contain a proper check for plausibility when reading/writing from/to a register map. To still have the current tests pass, increase the size of the memory region for the syscon0 device, since one of the tests reads and writes beyond this range. Reviewed-by: Anatolij Gustschin <agust(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- v10 -> v11: No changes v9 -> v10: No changes v8 -> v9: No changes v7 -> v8: No changes v6 -> v7: No changes v5 -> v6: * Fix the test that checks the changed size v4 -> v5: No changes v3 -> v4: No changes v2 -> v3: New in v3 --- arch/sandbox/dts/test.dts | 2 +- test/dm/regmap.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 420b72f4db..cc3b2e7c2a 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -521,7 +521,7 @@ syscon@0 { compatible = "sandbox,syscon0"; - reg = <0x10 4>; + reg = <0x10 16>; }; syscon@1 { diff --git a/test/dm/regmap.c b/test/dm/regmap.c index d4b86b3b03..b28d6a6cd1 100644 --- a/test/dm/regmap.c +++ b/test/dm/regmap.c @@ -25,7 +25,7 @@ static int dm_test_regmap_base(struct unit_test_state *uts) ut_assertok_ptr(map); ut_asserteq(1, map->range_count); ut_asserteq(0x10, map->ranges[0].start); - ut_asserteq(4, map->ranges[0].size); + ut_asserteq(16, map->ranges[0].size); ut_asserteq(0x10, map_to_sysmem(regmap_get_range(map, 0))); ut_assertok(uclass_get_device(UCLASS_SYSCON, 1, &dev)); -- 2.18.1

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[U-Boot] [PATCH] net: fec_mxc: add support for i.MX8X
by Anatolij Gustschin 24 Oct '18

24 Oct '18

Add compatible property and enable the FEC ipg clock when probing on i.MX8X. Add specific function for reading FEC clock rate via clock driver when configuring MII speed register. Allow FEC_MXC selection for i.MX8. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/net/Kconfig | 2 +- drivers/net/fec_mxc.c | 59 ++++++++++++++++++++++++++++++++++++++++--- drivers/net/fec_mxc.h | 4 +++ 3 files changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f1f0e2d94e..39687431fb 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -176,7 +176,7 @@ config FEC_MXC_MDIO_BASE config FEC_MXC bool "FEC Ethernet controller" - depends on MX5 || MX6 || MX7 + depends on MX5 || MX6 || MX7 || IMX8 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 5a1a8bc897..96fc733116 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -122,6 +122,32 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, return val; } +static int fec_get_clk_rate(void *udev, int idx) +{ +#if IS_ENABLED(CONFIG_IMX8) + struct fec_priv *fec; + struct udevice *dev; + int ret; + + dev = udev; + if (!dev) { + ret = uclass_get_device(UCLASS_ETH, idx, &dev); + if (ret < 0) { + debug("Can't get FEC udev: %d\n", ret); + return ret; + } + } + + fec = dev_get_priv(dev); + if (fec) + return fec->clk_rate; + + return -EINVAL; +#else + return imx_get_fecclk(); +#endif +} + static void fec_mii_setspeed(struct ethernet_regs *eth) { /* @@ -139,9 +165,20 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) * Given that ceil(clkrate / 5000000) <= 64, the calculation for * holdtime cannot result in a value greater than 3. */ - u32 pclk = imx_get_fecclk(); - u32 speed = DIV_ROUND_UP(pclk, 5000000); - u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; + u32 pclk; + u32 speed; + u32 hold; + int ret; + + ret = fec_get_clk_rate(NULL, 0); + if (ret < 0) { + printf("Can't find FEC0 clk rate: %d\n", ret); + return; + } + pclk = ret; + speed = DIV_ROUND_UP(pclk, 5000000); + hold = DIV_ROUND_UP(pclk, 100000000) - 1; + #ifdef FEC_QUIRK_ENET_MAC speed--; #endif @@ -1268,6 +1305,21 @@ static int fecmxc_probe(struct udevice *dev) uint32_t start; int ret; + if (IS_ENABLED(CONFIG_IMX8)) { + ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); + if (ret < 0) { + debug("Can't get FEC ipg clk: %d\n", ret); + return ret; + } + ret = clk_enable(&priv->ipg_clk); + if (ret < 0) { + debug("Can't enable FEC ipg clk: %d\n", ret); + return ret; + } + + priv->clk_rate = clk_get_rate(&priv->ipg_clk); + } + ret = fec_alloc_descs(priv); if (ret) return ret; @@ -1372,6 +1424,7 @@ static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx6sx-fec" }, { .compatible = "fsl,imx6ul-fec" }, { .compatible = "fsl,imx53-fec" }, + { .compatible = "fsl,imx7d-fec" }, { } }; diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index fd89443205..75ba55b69f 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -16,6 +16,8 @@ #ifndef __FEC_MXC_H #define __FEC_MXC_H +#include <clk.h> + /* Layout description of the FEC */ struct ethernet_regs { /* [10:2]addr = 00 */ @@ -257,6 +259,8 @@ struct fec_priv { #ifdef CONFIG_DM_ETH u32 interface; #endif + struct clk ipg_clk; + u32 clk_rate; }; void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); -- 2.17.1

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[U-Boot] [PATCH 1/2] net: mvpp2: fix polarity of PHY reset signal
by Baruch Siach 24 Oct '18

24 Oct '18

The dm_gpio_set_value() call sets the logical level of the GPIO signal. That is, it takes the GPIO_ACTIVE_{LOW,HIGH} property into account. The driver needs to assert the reset, and then deassert it. Not the other way around. Cc: Stefan Chulski <stefanc(a)marvell.com> Signed-off-by: Baruch Siach <baruch(a)tkos.co.il> --- drivers/net/mvpp2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index 62c0c2be0626..b3b1fe1a0c41 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -4805,9 +4805,9 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port) static void mvpp2_gpio_init(struct mvpp2_port *port) { if (dm_gpio_is_valid(&port->phy_reset_gpio)) { - dm_gpio_set_value(&port->phy_reset_gpio, 0); - udelay(1000); dm_gpio_set_value(&port->phy_reset_gpio, 1); + udelay(1000); + dm_gpio_set_value(&port->phy_reset_gpio, 0); } if (dm_gpio_is_valid(&port->phy_tx_disable_gpio)) -- 2.19.1

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[U-Boot] [PATCH] net/phy: Add phy-id for IN112525_S03
by Priyanka Jain 24 Oct '18

24 Oct '18

Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- include/phy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/phy.h b/include/phy.h index 52bf997..ef5ca7e 100644 --- a/include/phy.h +++ b/include/phy.h @@ -315,5 +315,6 @@ static inline bool phy_interface_is_sgmii(struct phy_device *phydev) /* PHY UIDs for various PHYs that are referenced in external code */ #define PHY_UID_CS4340 0x13e51002 #define PHY_UID_TN2020 0x00a19410 +#define PHY_UID_IN112525_S03 0x02107440 #endif -- 1.9.1

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[U-Boot] [PATCH 0/4] net: dm: fec: Fixes and improvements
by Martin Fuzzey 24 Oct '18

24 Oct '18

A few fixes and improvements for the FEC driver. They are functionally independent but included in a series to avoid conflicts if merged out of order as they touch the same files. Martin Fuzzey (4): net: dm: fec: Fix time unit error in phy-reset-duration net: dm: fec: Fix phy-reset-duration clamping and defaults net: dm: fec: Support the phy-supply binding net: dm: fec: Obtain the transceiver type from the DT drivers/net/fec_mxc.c | 60 ++++++++++++++++++++++++++++++++++++++++----------- drivers/net/fec_mxc.h | 3 +++ 2 files changed, 51 insertions(+), 12 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] miiphy: Add function to retrieve MDIO bus list head
by Pankaj Bansal 24 Oct '18

24 Oct '18

In upcoming freescale board LX2160AQDS, the MDIO bus is muxed. i.e. same MDIO bus can be routed to eight different slots depending on mux register settings. To support this mdio mux behavior, we add each MDIO bus mux as a separate MDIO bus. Now, various phy devices can be attached to each of these slots(mux). The information about these devices is passed to OS via device tree. To do the fdt fixups related to MDIO bus, its necessary that MDIO bus list is accessed.Therefore, add a function to retrieve the list head. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> --- common/miiphyutil.c | 5 +++++ include/miiphy.h | 1 + 2 files changed, 6 insertions(+) diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 8d89751122..2db067876e 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -177,6 +177,11 @@ struct mii_dev *mdio_get_current_dev(void) return current_mii; } +struct list_head *mdio_get_list_head(void) +{ + return &mii_devs; +} + struct phy_device *mdio_phydev_for_ethname(const char *ethname) { struct list_head *entry; diff --git a/include/miiphy.h b/include/miiphy.h index 2da28e311a..f11763affd 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -39,6 +39,7 @@ void miiphy_init(void); int miiphy_set_current_dev(const char *devname); const char *miiphy_get_current_dev(void); struct mii_dev *mdio_get_current_dev(void); +struct list_head *mdio_get_list_head(void); struct mii_dev *miiphy_get_dev_by_name(const char *devname); struct phy_device *mdio_phydev_for_ethname(const char *devname); -- 2.17.1

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[U-Boot] [PATCH] cmd: mii: don't check address for 'device' subcommand
by Hector Palacios 24 Oct '18

24 Oct '18

All mii operations require a valid PHY address except the 'device' command, which expects the PHY name rather than the address. Signed-off-by: Hector Palacios <hector.palacios(a)digi.com> --- cmd/mii.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/mii.c b/cmd/mii.c index ce7b393eeaae..c0c42a851f90 100644 --- a/cmd/mii.c +++ b/cmd/mii.c @@ -313,7 +313,7 @@ static int do_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) mask = simple_strtoul(argv[5], NULL, 16); } - if (addrhi > 31) { + if (addrhi > 31 && strncmp(op, "de", 2)) { printf("Incorrect PHY address. Range should be 0-31\n"); return CMD_RET_USAGE; }

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[U-Boot] [PATCH 0/5] sunxi: doc: Add fastboot example + misc cleanups
by Priit Laes 24 Oct '18

24 Oct '18

While writing a sample fastboot usage tutorial for sunxi, I also found bunch of discrepancies in the existing docs. Series also includes one simple constification patch that has been sitting in my tree for ages. Priit Laes (5): sunxi: Fix typos of spelling Allwinner sunxi: docs: Unify the formatting style and add some paragraph breaks sunxi: docs: Mention CONFIG_NAND requirement sunxi: display: Mark sunxi_rgb2yuv_coef array as const sunxi: doc: Add basic fastboot example arch/arm/mach-sunxi/dram_sun4i.c | 2 +- arch/arm/mach-sunxi/p2wi.c | 2 +- board/sunxi/README.fastboot | 98 ++++++++++++++++++++++++++++++- board/sunxi/README.nand | 24 +++---- board/sunxi/README.sunxi64 | 25 +++++--- drivers/video/sunxi/sunxi_display.c | 2 +- 6 files changed, 130 insertions(+), 23 deletions(-) create mode 100644 board/sunxi/README.fastboot base-commit: 3ae192c2a4d52a755031e93fa6cc3a31ba90f29f -- git-series 0.9.1

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[U-Boot] [PATCH 0/5] Get socfpga gen5 SPL working again.
by Simon Goldschmidt 24 Oct '18

24 Oct '18

Socfpga gen5 SPL has been broken since moving to DM serial with v2018.07.. Also, U-Boot console output has been broken since then. This series fixes this and makes some related small improvements. Simon Goldschmidt (5): arm: socfpga: fix SPL on gen5 after moving to DM serial arm: socfpga: fix device trees to work with DM serial arm: socfpga: cyclone5: handle debug uart board_init.c: fix simple malloc by storing malloc_limit malloc_simple: calloc: don't call memset if malloc failed arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/socfpga_arria5_socdk.dts | 1 + arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 1 + arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 1 + arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 1 + arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 1 + arch/arm/dts/socfpga_cyclone5_is1.dts | 1 + arch/arm/dts/socfpga_cyclone5_socdk.dts | 1 + arch/arm/dts/socfpga_cyclone5_sockit.dts | 1 + arch/arm/dts/socfpga_cyclone5_socrates.dts | 6 ++++++ arch/arm/dts/socfpga_cyclone5_sr1500.dts | 1 + arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 1 + arch/arm/mach-socfpga/reset_manager_gen5.c | 5 +++-- arch/arm/mach-socfpga/spl_gen5.c | 16 +++++++++++++--- common/init/board_init.c | 1 + common/malloc_simple.c | 3 ++- 16 files changed, 36 insertions(+), 6 deletions(-) -- 2.17.1

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