October 2018 - U-Boot

[U-Boot] [PATCH v1 0/3] dts: arm: socfpga: merge gen5 devicetrees from linux
by Simon Goldschmidt 31 Oct '18

31 Oct '18

This series merges socfpga gen5 dts and dtsi files from linux while keeping U-Boot behaviour. Changes in those files that need fixing (mostly in -u-boot.dtsi board files) are: - watchdog is now enabled - ethernet, spi and i2c aliases removed from socfpga.dtsi - gpio bank names not available - mmc disabled - qspi compatible string different - 'clock-frequency' removed from uarts These changes are mostly handled in changed dts files or U-Boot specific dtsi files except for: - added compatible "cdns,qspi-nor" to cadence_qspi.c - allow binding dwapb_gpio driver without "bank-name" property (gpios still work, only access via bank name fails) Simon Goldschmidt (3): gpio: dwapb_gpio: fix binding without bank-name property spi: cadence_qspi: use "cdns,qspi-nor" as compatible dts: arm: socfpga: merge gen5 devicetrees from linux arch/arm/dts/socfpga.dtsi | 404 ++++++++++++------ arch/arm/dts/socfpga_arria5.dtsi | 11 +- arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi | 56 +++ arch/arm/dts/socfpga_arria5_socdk.dts | 97 +++-- arch/arm/dts/socfpga_cyclone5.dtsi | 9 +- arch/arm/dts/socfpga_cyclone5_dbm_soc1.dts | 17 +- .../socfpga_cyclone5_de0_nano_soc-u-boot.dtsi | 46 ++ .../arm/dts/socfpga_cyclone5_de0_nano_soc.dts | 69 +-- arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 16 + arch/arm/dts/socfpga_cyclone5_de1_soc.dts | 16 + arch/arm/dts/socfpga_cyclone5_is1.dts | 8 + .../dts/socfpga_cyclone5_socdk-u-boot.dtsi | 72 ++++ arch/arm/dts/socfpga_cyclone5_socdk.dts | 88 +++- .../dts/socfpga_cyclone5_sockit-u-boot.dtsi | 56 +++ arch/arm/dts/socfpga_cyclone5_sockit.dts | 149 +++++-- .../dts/socfpga_cyclone5_socrates-u-boot.dtsi | 60 +++ arch/arm/dts/socfpga_cyclone5_socrates.dts | 85 ++-- arch/arm/dts/socfpga_cyclone5_sr1500.dts | 12 + .../socfpga_cyclone5_vining_fpga-u-boot.dtsi | 60 +++ arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 222 ++++++++-- doc/device-tree-bindings/spi/spi-cadence.txt | 3 +- drivers/gpio/dwapb_gpio.c | 7 + drivers/spi/cadence_qspi.c | 3 +- 23 files changed, 1234 insertions(+), 332 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_de0_nano_soc-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi -- 2.17.1

2 8

[U-Boot] [PATCH 0/3] add support for VSC8584 and VSC8574 Microsemi PHYs
by Quentin Schulz 31 Oct '18

31 Oct '18

The VSC8584 and VSC8574 PHYs are 4-port PHYs that are 10/100/1000BASE-T, 100BASE-FX, 1000BASE-X and triple-speed copper SFP capable, can communicate with the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and can set the blinking pattern of each of its 4 LEDs, supports SyncE as well as HP Auto-MDIX detection. This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the MAC. They have also an internal Intel 8051 microcontroller whose firmware needs to be patched when the PHY is reset. If the 8051's firmware has the expected CRC, its patching can be skipped. The microcontroller can be accessed from any port of the PHY, though the CRC function can only be done through the PHY that is the base PHY of the package (internal address 0) due to a limitation of the firmware. The GPIO register bank is a set of registers that are common to all PHYs in the package. So any modification in any register of this bank affects all PHYs of the package. Thanks, Quentin Quentin Schulz (3): net: phy: mscc: add support for VSC8584 PHY net: phy: mscc: factorize part of config function for VSC8584 net: phy: mscc: add support for VSC8574 PHY drivers/net/phy/mscc.c | 977 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 977 insertions(+) -- 2.17.1

2 8

[U-Boot] [PATCH v2] sf: remove spi-flash chip names from SPL binary
by Simon Goldschmidt 31 Oct '18

31 Oct '18

The table of spi flash chips 'spi_flash_ids' currently includes chip names. The only usage of these is to print the name when the chip is probed. Since this message is not shown in SPL, we can remove the names from the SPL binary. Removing the chip names saves ~890 Byte from the SPL binary in my configuration (socfpga_socrates_defconfig, MACRONIX, SPANSION and STMICRO enabled). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- Changes in v2: - use CONFIG_SPL_BUILD directly instead of SPI_FLASH_INCLUDE_NAME - iterate spi_flash_ids list until info->sector_size == 0, remove the extra global 'const size_t spi_flash_ids_size' drivers/mtd/spi/sf_internal.h | 3 + drivers/mtd/spi/spi_flash.c | 6 +- drivers/mtd/spi/spi_flash_ids.c | 269 +++++++++++++++++--------------- 3 files changed, 147 insertions(+), 131 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 4f63cacc64..dab3a5bfbc 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -114,8 +114,11 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, #define SPI_FLASH_MAX_ID_LEN 6 struct spi_flash_info { +/* Exclude chip names for SPL to save space */ +#ifndef CONFIG_SPL_BUILD /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */ const char *name; +#endif /* * This array stores the ID bytes. diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index c159124259..e6d0fa5fcf 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -1069,7 +1069,7 @@ static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) } info = spi_flash_ids; - for (; info->name != NULL; info++) { + for (; info->sector_size != 0; info++) { if (info->id_len) { if (!memcmp(info->id, id, info->id_len)) return info; @@ -1160,7 +1160,11 @@ int spi_flash_scan(struct spi_flash *flash) write_sr(flash, sr); } +#ifndef CONFIG_SPL_BUILD flash->name = info->name; +#else + flash->name = "spi-flash"; +#endif flash->memory_map = spi->memory_map; if (info->flags & SST_WR) diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index e662e4b42e..dd3033b1b8 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -12,8 +12,16 @@ #include "sf_internal.h" +/* Exclude chip names for SPL to save space */ +#ifndef CONFIG_SPL_BUILD +#define INFO_NAME(_name) .name = _name, +#else +#define INFO_NAME(_name) +#endif + /* Used when the "_ext_id" is two bytes at most */ -#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ +#define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + INFO_NAME(_name) \ .id = { \ ((_jedec_id) >> 16) & 0xff, \ ((_jedec_id) >> 8) & 0xff, \ @@ -27,7 +35,8 @@ .page_size = 256, \ .flags = (_flags), -#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ +#define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + INFO_NAME(_name) \ .id = { \ ((_jedec_id) >> 16) & 0xff, \ ((_jedec_id) >> 8) & 0xff, \ @@ -44,150 +53,150 @@ const struct spi_flash_info spi_flash_ids[] = { #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ - {"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, - {"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, - {"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, - {"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, - {"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, - {"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, - {"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, - {"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, - {"at25df321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, - {"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, + {INFO("at45db011d", 0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, + {INFO("at45db021d", 0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, + {INFO("at45db041d", 0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, + {INFO("at45db081d", 0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, + {INFO("at45db161d", 0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("at45db321d", 0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("at45db641d", 0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("at25df321a", 0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("at25df321", 0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("at26df081a", 0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ - {"en25q32b", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) }, - {"en25q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, - {"en25q128b", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) }, - {"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, + {INFO("en25q32b", 0x1c3016, 0x0, 64 * 1024, 64, 0) }, + {INFO("en25q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("en25q128b", 0x1c3018, 0x0, 64 * 1024, 256, 0) }, + {INFO("en25s64", 0x1c3817, 0x0, 64 * 1024, 128, 0) }, #endif #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ - {"gd25q16c", INFO(0xc84015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, - {"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024, 64, SECT_4K) }, - {"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("gd25q16c", 0xc84015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("gd25q64b", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("gd25q32b", 0xc84016, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("gd25lq32", 0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ - {"is25lq040b", INFO(0x9d4013, 0x0, 64 * 1024, 8, 0) }, - {"is25lp032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) }, - {"is25lp064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) }, - {"is25lp128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) }, - {"is25lp256", INFO(0x9d6019, 0x0, 64 * 1024, 512, 0) }, - {"is25wp032", INFO(0x9d7016, 0x0, 64 * 1024, 64, RD_FULL | SECT_4K) }, - {"is25wp064", INFO(0x9d7017, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, - {"is25wp128", INFO(0x9d7018, 0x0, 64 * 1024, 256, RD_FULL | SECT_4K) }, + {INFO("is25lq040b", 0x9d4013, 0x0, 64 * 1024, 8, 0) }, + {INFO("is25lp032", 0x9d6016, 0x0, 64 * 1024, 64, 0) }, + {INFO("is25lp064", 0x9d6017, 0x0, 64 * 1024, 128, 0) }, + {INFO("is25lp128", 0x9d6018, 0x0, 64 * 1024, 256, 0) }, + {INFO("is25lp256", 0x9d6019, 0x0, 64 * 1024, 512, 0) }, + {INFO("is25wp032", 0x9d7016, 0x0, 64 * 1024, 64, RD_FULL | SECT_4K) }, + {INFO("is25wp064", 0x9d7017, 0x0, 64 * 1024, 128, RD_FULL | SECT_4K) }, + {INFO("is25wp128", 0x9d7018, 0x0, 64 * 1024, 256, RD_FULL | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ - {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) }, - {"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, - {"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, - {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, - {"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, - {"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, - {"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"mx25l25635f", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, - {"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, - {"mx25l1633e", INFO(0xc22415, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"mx25u6435f", INFO(0xc22537, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP) }, - {"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"mx25u1635e", INFO(0xc22535, 0x0, 64 * 1024, 32, SECT_4K) }, - {"mx25u25635f", INFO(0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, - {"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, - {"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, + {INFO("mx25l2006e", 0xc22012, 0x0, 64 * 1024, 4, 0) }, + {INFO("mx25l4005", 0xc22013, 0x0, 64 * 1024, 8, 0) }, + {INFO("mx25l8005", 0xc22014, 0x0, 64 * 1024, 16, 0) }, + {INFO("mx25l1605d", 0xc22015, 0x0, 64 * 1024, 32, 0) }, + {INFO("mx25l3205d", 0xc22016, 0x0, 64 * 1024, 64, 0) }, + {INFO("mx25l6405d", 0xc22017, 0x0, 64 * 1024, 128, 0) }, + {INFO("mx25l12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("mx25l25635f", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {INFO("mx25l51235f", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {INFO("mx25l1633e", 0xc22415, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("mx25u6435f", 0xc22537, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP) }, + {INFO("mx25l12855e", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("mx25u1635e", 0xc22535, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("mx25u25635f", 0xc22539, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {INFO("mx66u51235f", 0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {INFO("mx66l1g45g", 0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ - {"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, - {"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) }, - {"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) }, - {"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) }, - {"s25fl208k", INFO(0x014014, 0x0, 64 * 1024, 16, 0) }, - {"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 32, 0) }, - {"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) }, - {"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, - {"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"s25fl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) }, - {"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, - {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, - {"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, - {"s25fs256s_64k", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, - {"s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, - {"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, - {"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, - {"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl008a", 0x010213, 0x0, 64 * 1024, 16, 0) }, + {INFO("s25fl016a", 0x010214, 0x0, 64 * 1024, 32, 0) }, + {INFO("s25fl032a", 0x010215, 0x0, 64 * 1024, 64, 0) }, + {INFO("s25fl064a", 0x010216, 0x0, 64 * 1024, 128, 0) }, + {INFO("s25fl208k", 0x014014, 0x0, 64 * 1024, 16, 0) }, + {INFO("s25fl116k", 0x014015, 0x0, 64 * 1024, 32, 0) }, + {INFO("s25fl164k", 0x014017, 0x0140, 64 * 1024, 128, 0) }, + {INFO("s25fl128p_256k", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {INFO("s25fl128p_64k", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl032p", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL | WR_QPP) }, + {INFO("s25fl064p", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL | WR_QPP) }, + {INFO("s25fl128s_256k", 0x012018, 0x4d00, 256 * 1024, 64, RD_FULL | WR_QPP) }, + {INFO("s25fl128s_64k", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl256s_256k", 0x010219, 0x4d00, 256 * 1024, 128, RD_FULL | WR_QPP) }, + {INFO6("s25fs256s_64k", 0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("s25fl256s_64k", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL | WR_QPP) }, + {INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL | WR_QPP) }, + {INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL | WR_QPP) }, #endif #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ - {"m25p10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) }, - {"m25p20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) }, - {"m25p40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) }, - {"m25p80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) }, - {"m25p16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) }, - {"m25pE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) }, - {"m25pX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) }, - {"m25p32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) }, - {"m25p64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) }, - {"m25p128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) }, - {"m25pX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, - {"n25q016a", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, - {"n25q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q32a", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, - {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, - {"mt35xu512g", INFO6(0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) }, + {INFO("m25p10", 0x202011, 0x0, 32 * 1024, 4, 0) }, + {INFO("m25p20", 0x202012, 0x0, 64 * 1024, 4, 0) }, + {INFO("m25p40", 0x202013, 0x0, 64 * 1024, 8, 0) }, + {INFO("m25p80", 0x202014, 0x0, 64 * 1024, 16, 0) }, + {INFO("m25p16", 0x202015, 0x0, 64 * 1024, 32, 0) }, + {INFO("m25pE16", 0x208015, 0x1000, 64 * 1024, 32, 0) }, + {INFO("m25pX16", 0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | RD_DUAL) }, + {INFO("m25p32", 0x202016, 0x0, 64 * 1024, 64, 0) }, + {INFO("m25p64", 0x202017, 0x0, 64 * 1024, 128, 0) }, + {INFO("m25p128", 0x202018, 0x0, 256 * 1024, 64, 0) }, + {INFO("m25pX64", 0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("n25q016a", 0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("n25q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("n25q32a", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("n25q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("n25q64a", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("n25q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("n25q128a", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP) }, + {INFO("n25q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q256a", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q512a", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("n25q1024a", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("mt25qu02g", 0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO("mt25ql02g", 0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | WR_QPP | E_FSR | SECT_4K) }, + {INFO6("mt35xu512g", 0x2c5b1a, 0x104100, 128 * 1024, 512, E_FSR | SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ - {"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, - {"sst25vf080b", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, - {"sst25vf016b", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) }, - {"sst25vf032b", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) }, - {"sst25vf064c", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, - {"sst25wf512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) }, - {"sst25wf010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) }, - {"sst25wf020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) }, - {"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, - {"sst25wf040b", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, - {"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, - {"sst26wf016", INFO(0xbf2651, 0x0, 64 * 1024, 32, SECT_4K) }, - {"sst26wf032", INFO(0xbf2622, 0x0, 64 * 1024, 64, SECT_4K) }, - {"sst26wf064", INFO(0xbf2643, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("sst25vf040b", 0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, + {INFO("sst25vf080b", 0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, + {INFO("sst25vf016b", 0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | SST_WR) }, + {INFO("sst25vf032b", 0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | SST_WR) }, + {INFO("sst25vf064c", 0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("sst25wf512", 0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | SST_WR) }, + {INFO("sst25wf010", 0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | SST_WR) }, + {INFO("sst25wf020", 0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | SST_WR) }, + {INFO("sst25wf040", 0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | SST_WR) }, + {INFO("sst25wf040b", 0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, + {INFO("sst25wf080", 0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | SST_WR) }, + {INFO("sst26wf016", 0xbf2651, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("sst26wf032", 0xbf2622, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("sst26wf064", 0xbf2643, 0x0, 64 * 1024, 128, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ - {"w25p80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) }, - {"w25p16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) }, - {"w25p32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) }, - {"w25x40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, - {"w25x16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, - {"w25x32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, - {"w25x64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, - {"w25q80bl", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q16cl", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q32bv", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q64cv", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q128bv", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q80bw", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q16dw", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q16jv", INFO(0xef7015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q32dw", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q32jv", INFO(0xef7016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q64dw", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q64jv", INFO(0xef7017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q128fw", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q128jv", INFO(0xef7018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q256fw", INFO(0xef6019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, - {"w25q256jw", INFO(0xef7019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, + {INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, + {INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, + {INFO("w25x40", 0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, + {INFO("w25x16", 0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, + {INFO("w25x32", 0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, + {INFO("w25x64", 0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {INFO("w25q80bl", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q16cl", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q32bv", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q64cv", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q128bv", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q80bw", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q16dw", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q16jv", 0xef7015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q32dw", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q32jv", 0xef7016, 0x0, 64 * 1024, 64, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q64dw", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q64jv", 0xef7017, 0x0, 64 * 1024, 128, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q128fw", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q128jv", 0xef7018, 0x0, 64 * 1024, 256, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q256fw", 0xef6019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, + {INFO("w25q256jw", 0xef7019, 0x0, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) }, #endif {}, /* Empty entry to terminate the list */ /* -- 2.17.1

2 2

[U-Boot] [PATCH v4] sunxi: add support for Banana Pi M2 Zero board
by Icenowy Zheng 31 Oct '18

31 Oct '18

From: Jun Nie <jun.nie(a)linaro.org> Banana Pi M2 Zero is a board by Sinovoip with Allwinner H2+ SoC, 16-bit 512MiB DDR3 memory, a MicroSD slot, two MicroUSB ports (one OTG and one powering-only) and a miniHDMI port. Signed-off-by: Icenowy Zheng <icenowy(a)aosc.io> Signed-off-by: Jun Nie <jun.nie(a)linaro.org> --- Changes in v4: - Fixed MMC card detect on product batch boards. - Synced the device tree from the same commit with other H3/H2+ DTs. arch/arm/dts/Makefile | 1 + .../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 121 ++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/bananapi_m2_zero_defconfig | 13 ++ 4 files changed, 140 insertions(+) create mode 100644 arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts create mode 100644 configs/bananapi_m2_zero_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0de6234eec..c2de60e031 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -365,6 +365,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dts dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts new file mode 100644 index 0000000000..7d01f93226 --- /dev/null +++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy(a)aosc.io> + * + * Based on sun8i-h3-bananapi-m2-plus.dts, which is: + * Copyright (C) 2016 Chen-Yu Tsai <wens(a)csie.org> + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Banana Pi BPI-M2-Zero"; + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + pwr_led { + label = "bananapi-m2-zero:red:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + + sw4 { + label = "power"; + linux,code = <BTN_0>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + /* + * On the production batch of this board the card detect GPIO is + * high active (card inserted), although on the early samples it's + * low active. + */ + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <&reg_vcc3v3>; + vqmmc-supply = <&reg_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + /* + * There're two micro-USB connectors, one is power-only and another is + * OTG. The Vbus of these two connectors are connected together, so + * the external USB device will be powered just by the power input + * from the power-only USB port. + */ + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 2f95976445..390b119003 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -402,6 +402,11 @@ M: Icenowy Zheng <icenowy(a)aosc.io> S: Maintained F: configs/Sinovoip_BPI_M2_Plus_defconfig +SINOVOIP BPI M2 ZERO BOARD +M: Icenowy Zheng <icenowy(a)aosc.io> +S: Maintained +F: configs/Sinovoip_BPI_M2_Zero_defconfig + SINOVOIP BPI M3 A83T BOARD M: VishnuPatekar <vishnupatekar0510(a)gmail.com> S: Maintained diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig new file mode 100644 index 0000000000..91302eb49c --- /dev/null +++ b/configs/bananapi_m2_zero_defconfig @@ -0,0 +1,13 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +CONFIG_MMC0_CD_PIN="" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero" -- 2.18.1

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[U-Boot] [PATCH] cmd: mtdparts: Probe MTD devices in mtdparts_init()
by Stefan Roese 31 Oct '18

31 Oct '18

Calling "mtdparts" currently fails when its called before any other mtd command (or ubi command) has been called. The MTD devices are not probed at this point and therefore it fails e.g. with this message: => mtdparts Device spi-nand0 not found! This patch adds a call to mtd_probe_devices() to mtdparts_init() to solve this issue. This also fixes a problem when calling "ubi part" as first flash storage related command. Here also the warning from above is printed without this patch. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Miquel Raynal <miquel.raynal(a)bootlin.com> Cc: Boris Brezillon <boris.brezillon(a)bootlin.com> Cc: Jagan Teki <jagan(a)openedev.com> --- cmd/mtdparts.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index f7ed1a0779..d90e568143 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -73,6 +73,7 @@ #include <common.h> #include <command.h> #include <malloc.h> +#include <mtd.h> #include <jffs2/load_kernel.h> #include <linux/list.h> #include <linux/ctype.h> @@ -1726,6 +1727,9 @@ int mtdparts_init(void) char tmp_ep[PARTITION_MAXLEN + 1]; char tmp_parts[MTDPARTS_MAXLEN]; + /* First probe all MTD devices */ + mtd_probe_devices(); + debug("\n---mtdparts_init---\n"); if (!initialized) { INIT_LIST_HEAD(&mtdids); -- 2.19.1

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[U-Boot] [PATCH] arm: socfpga: imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
by Simon Goldschmidt 30 Oct '18

30 Oct '18

Using imply for SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION instead of select ensures we can build without partition support (used to build a network boot only version of SPL and U-Boot). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 326d5c0daa..1f3fa1575a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -807,7 +807,6 @@ config ARCH_SOCFPGA select SPL_SPI_SUPPORT if DM_SPI select SPL_WATCHDOG_SUPPORT select SUPPORT_SPL - select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE select SYS_NS16550 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 imply CMD_DM @@ -817,6 +816,7 @@ config ARCH_SOCFPGA imply DM_SPI_FLASH imply FAT_WRITE imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION + imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" -- 2.17.1

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[U-Boot] [PATCH 1/2] powerpc: t1040: Correct RCW MAC2_GMII_SEL value
by Bin Meng 30 Oct '18

30 Oct '18

Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/powerpc/include/asm/immap_85xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7995093..8ec2a38 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1789,7 +1789,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 -#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 -- 2.7.4

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[U-Boot] [PATCH v2] fsl/usb: Workaround for USB erratum-A005275
by Chris Packham 30 Oct '18

30 Oct '18

Workaround makes FS as default mode on all affected socs. Add support to check erratum-A005275 validity for an soc. This info is required to determine whether a given soc is affected by this erratum. Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used to enable workaround for the errata Force FS mode as default by: - making EPS as FS - setting PFSC bit to disable HS chirping This workaround can be disabled by mentioning "no_erratum_a005275" in hwconfig string Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- This is based on a patch form Freescale's public git repo[1]. I'm not sure why it never made it upstream but I have P2041RDB boards that are affected as well as custom designs using the same SoC. I've cleaned things up a bit to fit with the other errata. [1] - http://git.freescale.com/git/cgit.cgi/ppc/sdk/u-boot.git/commit/?h=sdk-v1.4… Changes in v2: - Fix compile error when using DM_USB (thanks Marek) arch/powerpc/cpu/mpc85xx/Kconfig | 8 ++++++++ arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 ++++ drivers/usb/common/fsl-errata.c | 28 +++++++++++++++++++++++++++ drivers/usb/host/ehci-fsl.c | 7 +++++++ drivers/usb/host/ehci-hcd.c | 12 +++++++++++- drivers/usb/host/ehci.h | 4 ++++ include/fsl_usb.h | 1 + 7 files changed, 63 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7d139fffa24a..309ca294601b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -659,6 +659,7 @@ config ARCH_P1010 select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A005125 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_A007075 select SYS_FSL_ERRATUM_ESDHC111 @@ -821,6 +822,7 @@ config ARCH_P2041 select FSL_LAW select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_CPU_A003999 select SYS_FSL_ERRATUM_DDR_A003 @@ -845,6 +847,7 @@ config ARCH_P3041 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A005812 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_CPU_A003999 @@ -910,6 +913,7 @@ config ARCH_P5020 select FSL_LAW select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_DDR_A003 select SYS_FSL_ERRATUM_DDR_A003474 @@ -935,6 +939,7 @@ config ARCH_P5040 select SYS_FSL_DDR_VER_44 select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004699 + select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A005812 select SYS_FSL_ERRATUM_A006261 select SYS_FSL_ERRATUM_DDR_A003 @@ -1303,6 +1308,9 @@ config SYS_FSL_ERRATUM_A005812 config SYS_FSL_ERRATUM_A005871 bool +config SYS_FSL_ERRATUM_A005275 + bool + config SYS_FSL_ERRATUM_A006261 bool diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index eda2e7e63d76..e455d8baf584 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -307,6 +307,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) puts("Work-around for Erratum I2C-A004447 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005275 + if (has_erratum_a005275()) + puts("Work-around for Erratum A005275 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) puts("Work-around for Erratum A006261 enabled\n"); diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index 386130d7a1f6..9eb1d2306725 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <hwconfig.h> #include <fsl_errata.h> #include<fsl_usb.h> #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \ @@ -44,6 +45,33 @@ bool has_dual_phy(void) return false; } +bool has_erratum_a005275(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + if (hwconfig("no_erratum_a005275")) + return false; + + switch (soc) { +#ifdef CONFIG_PPC + case SVR_P3041: + case SVR_P2041: + case SVR_P2040: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + case SVR_P5010: + case SVR_P5020: + case SVR_P5021: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); + case SVR_P5040: + case SVR_P1010: + return IS_SVR_REV(svr, 1, 0); +#endif + } + + return false; +} + bool has_erratum_a006261(void) { u32 svr = get_svr(); diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index a04f6a31c8e4..a8fb2b8ac3b5 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -93,6 +93,7 @@ static int ehci_fsl_probe(struct udevice *dev) struct usb_ehci *ehci = NULL; struct ehci_hccr *hccr; struct ehci_hcor *hcor; + struct ehci_ctrl *ehci_ctrl = &priv->ehci; /* * Get the base address for EHCI controller from the device node @@ -107,6 +108,8 @@ static int ehci_fsl_probe(struct udevice *dev) hcor = (struct ehci_hcor *) ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275(); + if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0) return -ENXIO; @@ -145,6 +148,8 @@ U_BOOT_DRIVER(ehci_fsl) = { int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { + struct ehci_ctrl *ehci_ctrl = container_of(hccr, + struct ehci_ctrl, hccr); struct usb_ehci *ehci = NULL; switch (index) { @@ -163,6 +168,8 @@ int ehci_hcd_init(int index, enum usb_init_type init, *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275(); + return ehci_fsl_init(index, ehci, *hccr, *hcor); } diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 199b3a8b264d..d1d8f08d9867 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -409,9 +409,15 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) | QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) | QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) | - QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) | QH_ENDPT1_DEVADDR(usb_pipedevice(pipe)); + + /* Force FS for fsl HS quirk */ + if (!ctrl->has_fsl_erratum_a005275) + endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)); + else + endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED)); + qh->qh_endpt1 = cpu_to_hc32(endpt); endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0); qh->qh_endpt2 = cpu_to_hc32(endpt); @@ -832,6 +838,10 @@ static int ehci_submit_root(struct usb_device *dev, unsigned long pipe, } else { int ret; + /* Disable chirp for HS erratum */ + if (ctrl->has_fsl_erratum_a005275) + reg |= PORTSC_FSL_PFSC; + reg |= EHCI_PS_PR; reg &= ~EHCI_PS_PE; ehci_writel(status_reg, reg); diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 7945016624da..6c359af90c94 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -8,6 +8,7 @@ #ifndef USB_EHCI_H #define USB_EHCI_H +#include <stdbool.h> #include <usb.h> #include <generic-phy.h> @@ -66,6 +67,8 @@ struct ehci_hcor { #define PORTSC_PSPD_FS 0x0 #define PORTSC_PSPD_LS 0x1 #define PORTSC_PSPD_HS 0x2 +#define PORTSC_FSL_PFSC BIT(24) /* PFSC bit to disable HS chirping */ + uint32_t or_systune; } __attribute__ ((packed, aligned(4))); @@ -251,6 +254,7 @@ struct ehci_ctrl { uint32_t *periodic_list; int periodic_schedules; int ntds; + bool has_fsl_erratum_a005275; /* Freescale HS silicon quirk */ struct ehci_ops ops; void *priv; /* client's private data */ }; diff --git a/include/fsl_usb.h b/include/fsl_usb.h index e9e1dd69053e..c0f076b06daf 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -87,6 +87,7 @@ struct ccsr_usb_phy { /* USB Erratum Checking code */ #if defined(CONFIG_PPC) || defined(CONFIG_ARM) bool has_dual_phy(void); +bool has_erratum_a005275(void); bool has_erratum_a006261(void); bool has_erratum_a007075(void); bool has_erratum_a007798(void); -- 2.19.0

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[U-Boot] [ANN] U-Boot v2018.11-rc3 released
by Tom Rini 30 Oct '18

30 Oct '18

Hey all, It's two weeks until v2018.11 release and today I've put out rc3. The delta is pretty reasonable and at this point I can really hold things to either obviously correct fixes or bugfixes/regression fixes/Kconfig migrations that can be proven out. Thanks all! -- Tom

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[U-Boot] [PATCH] arm: socfpga: Fix bootcounter located at the end of internal SRAM
by Stefan Roese 30 Oct '18

30 Oct '18

Commit 768f23dc8ae3 ("ARM: socfpga: Put stack at the end of SRAM") broke those socfpga boards that keep the bootcounter at the end of the internal SRAM as the bootcounter needs 8 bytes by default and thus the very first SPL call to board_init_f_alloc_reserve overwrites the bootcounter. This patch allows to move the initial stack pointer down a bit by checking if CONFIG_SYS_BOOTCOUNT_ADDR is located in the internal SRAM area and then using this address as location for the start of the stack pointer. No new macros / defines are added by this approach. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- include/configs/socfpga_common.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2330143cf1..bd8f5c8c41 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -31,8 +31,21 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ #endif + +/* + * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal + * SRAM as bootcounter storage. Make sure to not put the stack directly + * at this address to not overwrite the bootcounter by checking, if the + * bootcounter address is located in the internal SRAM. + */ +#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ + (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE))) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_BOOTCOUNT_ADDR +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) +#endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -- 2.19.1

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