June 2017 - U-Boot

[U-Boot] [PATCH v3 00/35] dm: tegra: Move nyan-big, jetson-tk1, beaver to livetree
by Simon Glass 12 Jul '17

12 Jul '17

This moves three entire boards to use a live device tree as an example of the impact. Nyan-big was chosen because I can easily and boot U-Boot without any media swapping, etc. Beaver is enabled as well since it failed to boot with serial v1 due to a disabled console node. Jetson-TK1 is chosen because I found some USB problems in the v2 patches. Total code size impact on this board is approximately 9KB on U-Boot and 64 bytes on SPL: 27: dm: tegra: nyan-big: Move to livetree arm: (for 1/1 boards) all +9264.0 bss -16.0 data +44.0 rodata +92.0 spl/u-boot-spl:all +326.0 spl/u-boot-spl:rodata +262.0 spl/u-boot-spl:text +64.0 text +9144.0 Tegra does not use Thumb2, which would likely reduce the code size by about 25%, indicating a code-size impact of perhaps 7KB. Boot time is affected slightly. For nyan-big the times with flat tree are: 2,108 dm_r 7,924 dm_spl 120,724 dm_f 171,816 lcd With the livetree: 721 dm_r 3,764 of_live 7,990 dm_spl 120,736 dm_f 168,215 lcd As expected the spl and pre-relocation times are not affected. In the post-relocation case, the live tree must be built, which here takes about 3.8ms. Driver-model device creation takes a bit of 1ms less time with the livetree, so all up the cost is about 2.4ms. After DM init there appears to be a slight reduction in the time taken to set up devices (from 327ms to 319ms) so overall the live tree does not appear to be any slower. This is because pre-parsing the device tree makes reading it later faster. The use of livetree is controlled by a the CONFIG_OF_LIVE option. When enabled, U-Boot builds a livetree immediately after relocation and uses it from then on. This series is available at u-boot-dm/livet-working Changes in v3: - Add new patch to add ofnode_read_string_count() - Add new patch to add dev_read_resource() - Add new patch to add dev_read_enabled() - Add new patch with functions to obtain node's address/size cells - Update commit message, enable for all tegra124 boards not just nyan-big - Fix up the implementation which had node instead of subnode in one place - Add new patch to convert tegra PCI to device tree - Enable livetree for jetson-tk1 also Changes in v2: - Add new patch to enable bootstage for nyan-big - Add new patch to ensure that the console UART is enabled - Enable livetree for beaver also - Add timing information Simon Glass (35): dm: core: Add ofnode_read_string_count() dm: core: Add dev_read_resource() to read device resources dm: core: Add dev_read_enabled() to check if a device is enabled dm: core: Add functions to obtain node's address/size cells tegra: video: Time the LCD init tegra: nyan-big: Enable the debug UART dm: Fix error handling when unflattening the DT tegra: nyan-big: Enable bootstage dm: video: Sync display on backspace dm: video: Update pwm_backlight to support livetree video: simple-panel: Add a little more debugging tegra: Fix up include file ordering tegra: spl: Enable debug UART tegra: tegra124: Add a PMC syscon driver dm: tegra: Convert USB setup to livetree dm: tegra: Convert clock_decode_periph_id() to support livetree dm: video: tegra124: Convert to livetree tegra: dts: Move stdout-path to /chosen dm: tegra: gpio: Convert to support livetree dm: tegra: usb: Convert to livetree dm: tegra: spi: Convert to livetree dm: tegra: i2c: Convert to livetree dm: tegra: pwm: Convert to livetree dm: tegra: mmc: Convert to livetree dm: tegra: pci: Convert to livetree power: Add a regulator driver for the as3722 PMIC power: Add a GPIO driver for the as3722 PMIC dm: power: Convert as3722 to driver model dm: serial: ns16550: Convert to livetree dm: serial: Separate out the core serial-device finding code dm: serial: Add livetree support tegra: Show a debug message if the LCD PMIC fails to start fdtdec: Drop old compatible values tegra: fdt: Ensure that the console UART is enabled dm: tegra: Move nyan-big, jetson-tk1, beaver to livetree arch/arm/dts/tegra114-dalmore.dts | 4 + arch/arm/dts/tegra124-cei-tk1-som.dts | 4 + arch/arm/dts/tegra124-jetson-tk1.dts | 4 + arch/arm/dts/tegra124-nyan-big.dts | 5 +- arch/arm/dts/tegra124-venice2.dts | 4 + arch/arm/dts/tegra186-p2771-0000.dtsi | 4 + arch/arm/dts/tegra20-colibri.dts | 4 + arch/arm/dts/tegra20-harmony.dts | 4 + arch/arm/dts/tegra20-trimslice.dts | 4 + arch/arm/dts/tegra20-whistler.dts | 4 + arch/arm/dts/tegra210-e2220-1170.dts | 4 + arch/arm/dts/tegra210-p2371-0000.dts | 4 + arch/arm/dts/tegra210-p2371-2180.dts | 4 + arch/arm/dts/tegra210-p2571.dts | 4 + arch/arm/dts/tegra30-apalis.dts | 4 + arch/arm/dts/tegra30-beaver.dts | 4 + arch/arm/dts/tegra30-cardhu.dts | 4 + arch/arm/dts/tegra30-colibri.dts | 4 + arch/arm/dts/tegra30-tec-ng.dts | 4 + arch/arm/include/asm/arch-tegra/clock.h | 2 +- arch/arm/include/asm/arch-tegra/tegra.h | 5 + arch/arm/include/asm/arch-tegra/xusb-padctl.h | 2 +- arch/arm/mach-tegra/Kconfig | 2 + arch/arm/mach-tegra/board2.c | 34 ++- arch/arm/mach-tegra/clock.c | 9 +- arch/arm/mach-tegra/spl.c | 4 + arch/arm/mach-tegra/tegra124/Makefile | 1 + arch/arm/mach-tegra/tegra124/pmc.c | 19 ++ arch/arm/mach-tegra/tegra124/xusb-padctl.c | 36 +++- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 40 +++- arch/arm/mach-tegra/xusb-padctl-common.c | 63 +++--- arch/arm/mach-tegra/xusb-padctl-common.h | 11 +- arch/arm/mach-tegra/xusb-padctl-dummy.c | 2 +- board/cei/cei-tk1-som/cei-tk1-som.c | 2 + board/nvidia/jetson-tk1/jetson-tk1.c | 2 + board/nvidia/nyan-big/nyan-big.c | 22 +- board/toradex/apalis-tk1/apalis-tk1.c | 6 + configs/apalis-tk1_defconfig | 3 + configs/beaver_defconfig | 1 + configs/cei-tk1-som_defconfig | 3 + configs/jetson-tk1_defconfig | 4 + configs/nyan-big_defconfig | 11 + drivers/core/Makefile | 2 +- drivers/core/of_access.c | 24 +++ drivers/core/ofnode.c | 28 ++- drivers/core/read.c | 21 ++ drivers/core/read_extra.c | 37 ++++ drivers/core/regmap.c | 4 +- drivers/gpio/tegra_gpio.c | 10 +- drivers/i2c/tegra_i2c.c | 6 +- drivers/mmc/tegra_mmc.c | 17 +- drivers/pci/pci-uclass.c | 6 +- drivers/pci/pci_tegra.c | 53 +++-- drivers/power/pmic/Makefile | 2 +- drivers/power/pmic/as3722.c | 292 +++++++++----------------- drivers/power/pmic/as3722_gpio.c | 120 +++++++++++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/as3722_regulator.c | 149 +++++++++++++ drivers/pwm/tegra_pwm.c | 2 +- drivers/serial/ns16550.c | 15 +- drivers/serial/serial-uclass.c | 92 ++++---- drivers/spi/tegra114_spi.c | 15 +- drivers/spi/tegra20_sflash.c | 2 +- drivers/spi/tegra20_slink.c | 2 +- drivers/spi/tegra210_qspi.c | 2 +- drivers/usb/host/ehci-tegra.c | 36 ++-- drivers/video/pwm_backlight.c | 22 +- drivers/video/simple_panel.c | 2 + drivers/video/tegra124/display.c | 10 +- drivers/video/tegra124/dp.c | 3 +- drivers/video/tegra124/sor.c | 25 +-- drivers/video/vidconsole-uclass.c | 1 + include/dm/of_access.h | 38 ++++ include/dm/ofnode.h | 32 ++- include/dm/read.h | 86 +++++++- include/fdtdec.h | 6 - include/power/as3722.h | 27 ++- lib/fdtdec.c | 6 - lib/of_live.c | 7 +- 80 files changed, 1091 insertions(+), 482 deletions(-) create mode 100644 arch/arm/mach-tegra/tegra124/pmc.c create mode 100644 drivers/core/read_extra.c create mode 100644 drivers/power/pmic/as3722_gpio.c create mode 100644 drivers/power/regulator/as3722_regulator.c -- 2.13.1.508.gb3defc5cc-goog

5 84

[U-Boot] [PATCH] arm: mach-keystone: Modify secure image size before copy
by Andrew F. Davis 11 Jul '17

11 Jul '17

The size of the secure image does not include the size of the header, subtract this out before we move the image or we grab extra data after the image. Signed-off-by: Andrew F. Davis <afd(a)ti.com> --- arch/arm/mach-keystone/mon.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c index 81009848d0..ebfb483a1b 100644 --- a/arch/arm/mach-keystone/mon.c +++ b/arch/arm/mach-keystone/mon.c @@ -114,12 +114,12 @@ void board_fit_image_post_process(void **p_image, size_t *p_size) } /* - * Overwrite the image headers after authentication - * and decryption. Update size to reflect removal - * of header. - */ - memcpy(image, image + KS2_HS_SEC_HEADER_LEN, *p_size); + * Overwrite the image headers after authentication + * and decryption. Update size to reflect removal + * of header. + */ *p_size -= KS2_HS_SEC_HEADER_LEN; + memcpy(image, image + KS2_HS_SEC_HEADER_LEN, *p_size); /* * Output notification of successful authentication to re-assure the -- 2.13.0

3 2

[U-Boot] [PATCHv6 1/3] ARM64: dts: hi3798cv200-poplar: add device tree bindings
by Jorge Ramirez-Ortiz 11 Jul '17

11 Jul '17

Pulled from Linux 4.12-rc3 Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz(a)linaro.org> --- arch/arm/dts/hi3798cv200-poplar.dts | 162 +++++++++++++ arch/arm/dts/hi3798cv200.dtsi | 411 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 66 +++++ include/dt-bindings/reset/ti-syscon.h | 38 +++ 4 files changed, 677 insertions(+) create mode 100644 arch/arm/dts/hi3798cv200-poplar.dts create mode 100644 arch/arm/dts/hi3798cv200.dtsi create mode 100644 include/dt-bindings/clock/histb-clock.h create mode 100644 include/dt-bindings/reset/ti-syscon.h diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts new file mode 100644 index 0000000..b914287 --- /dev/null +++ b/arch/arm/dts/hi3798cv200-poplar.dts @@ -0,0 +1,162 @@ +/* + * DTS File for HiSilicon Poplar Development Board + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "hi3798cv200.dtsi" + +/ { + model = "HiSilicon Poplar Development Board"; + compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; + + aliases { + serial0 = &uart0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + + user-led0 { + label = "USER-LED0"; + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "USER-LED1"; + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "USER-LED2"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + user-led3 { + label = "USER-LED3"; + gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + }; +}; + +&gmac1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&eth_phy1>; + phy-mode = "rgmii"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; + + eth_phy1: phy@3 { + reg = <3>; + }; +}; + +&gpio1 { + status = "okay"; + gpio-line-names = "LS-GPIO-E", "", + "", "", + "", "LS-GPIO-F", + "", "LS-GPIO-J"; +}; + +&gpio2 { + status = "okay"; + gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", + "LS-GPIO-L", "LS-GPIO-G", + "LS-GPIO-K", "", + "", ""; +}; + +&gpio3 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "LS-GPIO-C", "", + "", "LS-GPIO-B"; +}; + +&gpio4 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "", "LS-GPIO-D", + "", ""; +}; + +&gpio5 { + status = "okay"; + gpio-line-names = "", "USER-LED-1", + "USER-LED-2", "", + "", "LS-GPIO-A", + "", ""; +}; + +&gpio6 { + status = "okay"; + gpio-line-names = "", "", + "", "USER-LED-0", + "", "", + "", ""; +}; + +&gpio10 { + status = "okay"; + gpio-line-names = "", "", + "", "", + "", "", + "USER-LED-3", ""; +}; + +&i2c0 { + status = "okay"; + label = "LS-I2C0"; +}; + +&i2c2 { + status = "okay"; + label = "LS-I2C1"; +}; + +&ir { + status = "okay"; +}; + +&spi0 { + status = "okay"; + label = "LS-SPI0"; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + label = "LS-UART0"; +}; +/* No optional LS-UART1 on Low Speed Expansion Connector. */ diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi new file mode 100644 index 0000000..75865f8 --- /dev/null +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -0,0 +1,411 @@ +/* + * DTS File for HiSilicon Hi3798cv200 SoC. + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <dt-bindings/clock/histb-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/ti-syscon.h> + +/ { + compatible = "hisilicon,hi3798cv200"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ + <0x0 0xf1002000 0x0 0x100>; /* GICC */ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + soc: soc@f0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xf0000000 0x10000000>; + + crg: clock-reset-controller@8a22000 { + compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; + reg = <0x8a22000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + + gmacphyrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = + <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | + DEASSERT_SET|STATUS_NONE)>, + <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | + DEASSERT_SET|STATUS_NONE)>; + }; + }; + + sysctrl: system-controller@8000000 { + compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; + reg = <0x8000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + uart0: serial@8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b00000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl HISTB_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@8b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x8b02000 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@8b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b10000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C0_CLK>; + status = "disabled"; + }; + + i2c1: i2c@8b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b11000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C1_CLK>; + status = "disabled"; + }; + + i2c2: i2c@8b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b12000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C2_CLK>; + status = "disabled"; + }; + + i2c3: i2c@8b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b13000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C3_CLK>; + status = "disabled"; + }; + + i2c4: i2c@8b14000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0x8b14000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C4_CLK>; + status = "disabled"; + }; + + spi0: spi@8b1a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x8b1a000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + cs-gpios = <&gpio7 1 0>; + clocks = <&crg HISTB_SPI0_CLK>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emmc: mmc@9830000 { + compatible = "snps,dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + gpio0: gpio@8b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b20000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio1: gpio@8b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b21000 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio2: gpio@8b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b22000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio3: gpio@8b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b23000 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio4: gpio@8b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b24000 0x1000>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio5: gpio@8004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8004000 0x1000>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio6: gpio@8b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b26000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio7: gpio@8b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b27000 0x1000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio8: gpio@8b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b28000 0x1000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio9: gpio@8b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b29000 0x1000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio10: gpio@8b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2a000 0x1000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio11: gpio@8b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2b000 0x1000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio12: gpio@8b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x8b2c000 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gmac0: ethernet@9840000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9840000 0x1000>, + <0x984300c 0x4>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 8>, + <&crg 0xcc 10>, + <&gmacphyrst 0>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + gmac1: ethernet@9841000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0x9841000 0x1000>, + <0x9843010 0x4>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH1_MAC_CLK>, + <&crg HISTB_ETH1_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 9>, + <&crg 0xcc 11>, + <&gmacphyrst 1>; + reset-names = "mac_core", "mac_ifc", "phy"; + status = "disabled"; + }; + + ir: ir@8001000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0x8001000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl HISTB_IR_CLK>; + status = "disabled"; + }; + }; +}; diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h new file mode 100644 index 0000000..181c0f0 --- /dev/null +++ b/include/dt-bindings/clock/histb-clock.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __DTS_HISTB_CLOCK_H +#define __DTS_HISTB_CLOCK_H + +/* clocks provided by core CRG */ +#define HISTB_OSC_CLK 0 +#define HISTB_APB_CLK 1 +#define HISTB_AHB_CLK 2 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 +#define HISTB_SCI_CLK 15 +#define HISTB_FMC_CLK 16 +#define HISTB_MMC_BIU_CLK 17 +#define HISTB_MMC_CIU_CLK 18 +#define HISTB_MMC_DRV_CLK 19 +#define HISTB_MMC_SAMPLE_CLK 20 +#define HISTB_SDIO0_BIU_CLK 21 +#define HISTB_SDIO0_CIU_CLK 22 +#define HISTB_SDIO0_DRV_CLK 23 +#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_PCIE_AUX_CLK 25 +#define HISTB_PCIE_PIPE_CLK 26 +#define HISTB_PCIE_SYS_CLK 27 +#define HISTB_PCIE_BUS_CLK 28 +#define HISTB_ETH0_MAC_CLK 29 +#define HISTB_ETH0_MACIF_CLK 30 +#define HISTB_ETH1_MAC_CLK 31 +#define HISTB_ETH1_MACIF_CLK 32 +#define HISTB_COMBPHY1_CLK 33 + + +/* clocks provided by mcu CRG */ +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6 + +#endif /* __DTS_HISTB_CLOCK_H */ diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h new file mode 100644 index 0000000..884fd91 --- /dev/null +++ b/include/dt-bindings/reset/ti-syscon.h @@ -0,0 +1,38 @@ +/* + * TI Syscon Reset definitions + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +#define __DT_BINDINGS_RESET_TI_SYSCON_H__ + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define ASSERT_NONE (1 << 0) +#define DEASSERT_NONE (1 << 1) +#define STATUS_NONE (1 << 2) + +/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET (1 << 3) +#define DEASSERT_SET (1 << 4) +#define STATUS_SET (1 << 5) + +/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5) + +#endif -- 2.7.4

4 11

[U-Boot] [PATCH 0/2] stm32 pinctrl improvements
by patrice.chotard＠st.com 11 Jul '17

11 Jul '17

From: Patrice Chotard <patrice.chotard(a)st.com> This series improves the stm32 pinctrl driver by adding: _ pinmux list support _ set_state ops callback support Christophe Kerello (2): pinctrl: stm32: handle a configuration list pinctrl: stm32: add set_state ops drivers/pinctrl/pinctrl_stm32.c | 62 ++++++++++++++++++++++++++++++++--------- 1 file changed, 49 insertions(+), 13 deletions(-) -- 1.9.1

2 4

[U-Boot] [PATCH v4 00/30]
by Franklin S Cooper Jr 11 Jul '17

11 Jul '17

This patchset adds support for the new Keystone 2 Industrial Communication Engine board. This patchset includes the introduction of embedded FIT images in U-boot. This creates a FIT image of dtb files that enables board specific code to select which DTB to use at runtime. Initially during boot a generic DTB is required that enables board detection to occur and once it has can later be swapped out for the correct dtb. Version 4 changes: Rebased on top of master. Tweaks done to patches 2 and 3 since functions have been added and tweaked in spl_fit.c. Left reviewed by as is since changes weren't drastic. Version 3 changes: Fixed minor comments that were missed in rev 2. Version 2 changes: Some patches were dropped since equivalent changes have already be incorporated in upstream already. The addition davinci i2c device model in upstream resulted in some patches having to be added or tweaked. The DT for K2G ICE is based on the version that has been accepted into Linux mainline https://lkml.org/lkml/2017/5/22/28 Franklin S Cooper Jr (29): spl: fit: Break out some functions into a common file boot_fit: Create helper functions that can be used to select DTB out of FIT fdt: Enable selecting correct DTB from appended FIT Image ti: common: board_detect: Add function to determine if EEPROM was read dts: Allow OF_LIST to depend on FIT_EMBED ARM: dts: k2g: Introduce U-boot specific dtsi file arm: dts: Add new "generic" 66AK2Gx device tree file. board_f: Add new function to allow runtime DTB selection Makefile: Build additional binaries for dtb FIT blobs appended to U-boot ARM: keystone2: Allow to build with all image formats ARM: k2g: Define embedded_dtb_select for runtime DTB selection in U-boot ARM: keystone2: Define board_fit_config_name_match for Keystone 2 boards ks2_evm: Add EEPROM based board detection defconfig: keystone2: Enable U-boot runtime DTB detection ARM: keystone2: Add additional fields used for DDR3 configuration ARM: k2g: Program DDR PHY MR2 register with the default value ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables ks2_evm: Add EEPROM based board detection helper functions ARM: k2g: Add pinmux support for K2G ICE evm ARM: k2g: Add DDR3 configuration for K2G ICE evm board: ks2: Use board detection to wrap code not specific to K2G ICE evm ARM: k2g: Use board detection to wrap K2G GP specific calls ARM: k2g: Update board_name u-boot env variable at runtime ARM: dts: keystone-k2g: Remove skeleton.dtsi ARM: dts: keystone-k2g-evm: Add unit address to memory node ARM: dts: k2g: Disable netcp by default ARM: dts: k2g: Add DT support for K2G Industrial Communication Engine evm ARM: k2g: Add K2G ICE DTB to the list of possible DTBs defconfig: k2g_evm_defconfig: Add K2G ICE to OF_LIST Nishanth Menon (1): ti: common: board_detect: Allow settings board detection variables manually .gitignore | 1 + Makefile | 18 +++++- arch/arm/dts/Makefile | 4 +- arch/arm/dts/keystone-k2g-evm-u-boot.dtsi | 19 ++++++ arch/arm/dts/keystone-k2g-evm.dts | 9 +++ arch/arm/dts/keystone-k2g-generic-u-boot.dtsi | 19 ++++++ arch/arm/dts/keystone-k2g-generic.dts | 28 +++++++++ arch/arm/dts/keystone-k2g-ice-u-boot.dtsi | 19 ++++++ arch/arm/dts/keystone-k2g-ice.dts | 36 +++++++++++ arch/arm/dts/keystone-k2g-netcp.dtsi | 1 + arch/arm/dts/keystone-k2g.dtsi | 8 +-- arch/arm/mach-keystone/config.mk | 4 +- arch/arm/mach-keystone/ddr3.c | 35 ++++++++--- arch/arm/mach-keystone/include/mach/ddr3.h | 14 +++++ arch/arm/mach-keystone/include/mach/hardware.h | 3 + board/ti/common/board_detect.c | 34 ++++++++++ board/ti/common/board_detect.h | 26 ++++++++ board/ti/ks2_evm/board.c | 21 +++++-- board/ti/ks2_evm/board.h | 21 +++++++ board/ti/ks2_evm/board_k2e.c | 10 +++ board/ti/ks2_evm/board_k2g.c | 86 +++++++++++++++++++++++--- board/ti/ks2_evm/board_k2hk.c | 10 +++ board/ti/ks2_evm/board_k2l.c | 10 +++ board/ti/ks2_evm/ddr3_k2g.c | 78 ++++++++++++++++++++++- board/ti/ks2_evm/mux-k2g.h | 45 +++++++++++++- common/Kconfig | 16 +++++ common/Makefile | 2 + common/board_f.c | 3 + common/boot_fit.c | 80 ++++++++++++++++++++++++ common/common_fit.c | 62 +++++++++++++++++++ common/spl/spl_fit.c | 54 +--------------- configs/k2e_evm_defconfig | 3 + configs/k2g_evm_defconfig | 3 + configs/k2hk_evm_defconfig | 3 + configs/k2l_evm_defconfig | 3 + dts/Kconfig | 11 ++-- include/boot_fit.h | 9 +++ include/common.h | 4 ++ include/configs/k2g_evm.h | 13 +++- include/image.h | 10 +++ lib/fdtdec.c | 10 +++ 41 files changed, 749 insertions(+), 96 deletions(-) create mode 100644 arch/arm/dts/keystone-k2g-evm-u-boot.dtsi create mode 100644 arch/arm/dts/keystone-k2g-generic-u-boot.dtsi create mode 100644 arch/arm/dts/keystone-k2g-generic.dts create mode 100644 arch/arm/dts/keystone-k2g-ice-u-boot.dtsi create mode 100644 arch/arm/dts/keystone-k2g-ice.dts create mode 100644 common/boot_fit.c create mode 100644 common/common_fit.c create mode 100644 include/boot_fit.h -- 2.10.0

2 61

[U-Boot] [PATCH] ARM: dts: keystone-k2e-evm: Add U-boot specific dtsi file
by Franklin S Cooper Jr 11 Jul '17

11 Jul '17

With Davinci I2C switching to device model, K2E requires U-boot specific device tree entries. This is only required for I2C 1 which is needed extremely early during the boot process. Fixes: 1743d040b1df ("ARM: keystone: Enable DM_I2C by default") Signed-off-by: Franklin S Cooper Jr <fcooper(a)ti.com> --- arch/arm/dts/keystone-k2e-evm-u-boot.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 arch/arm/dts/keystone-k2e-evm-u-boot.dtsi diff --git a/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi new file mode 100644 index 0000000..072a758 --- /dev/null +++ b/arch/arm/dts/keystone-k2e-evm-u-boot.dtsi @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/{ + soc { + u-boot,dm-pre-reloc; + }; +}; + +&i2c1 { + u-boot,dm-pre-reloc; +}; -- 2.10.0

2 1

[U-Boot] [PATCH v6] mmc: gen_atmel_mci: add driver model support for mci
by Wenyou Yang 11 Jul '17

11 Jul '17

Add the driver model support for Atmel mci while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- Changes in v6: - Rebase the master branch (commit: 4f6d85bb51). Changes in v5: - Rebase on v2017.03. Changes in v4: - Remove unneeded #ifdef CONFIG_DM_MMC. Changes in v3: - Use unified #ifdef CONFIG_DM_MMC #else...#endif, instead of #ifndef CONFIG_DM_MMC #else...#endif. Changes in v2: - Change the return type of atmel_mci_setup_cfg() from int to void. - Add comments on the features depends on the IP version. - Add the error handle path of clock. - Fix the missing use priv->bus_clk_rate. - Return from mmc_bind() directly, instead of checking its return. drivers/mmc/Kconfig | 9 +++ drivers/mmc/gen_atmel_mci.c | 158 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 166 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 560391fae2..f285698272 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -365,6 +365,15 @@ config MMC_SUNXI This selects support for the SD/MMC Host Controller on Allwinner sunxi SoCs. +config GENERIC_ATMEL_MCI + bool "Atmel Multimedia Card Interface support" + depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91 + help + This enables support for Atmel High Speed Multimedia Card Interface + (HSMCI), which supports the MultiMedia Card (MMC) Specification V4.3, + the SD Memory Card Specification V2.0, the SDIO V2.0 specification + and CE-ATA V1.1. + endif config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 7dc4a5de74..c25d9ed96e 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <clk.h> #include <mmc.h> #include <part.h> #include <malloc.h> @@ -18,8 +19,11 @@ #include <asm/byteorder.h> #include <asm/arch/clk.h> #include <asm/arch/hardware.h> +#include <dm/device.h> #include "atmel_mci.h" +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_SYS_MMC_CLK_OD # define CONFIG_SYS_MMC_CLK_OD 150000 #endif @@ -37,6 +41,10 @@ struct atmel_mci_priv { struct atmel_mci *mci; unsigned int initialized:1; unsigned int curr_clk; +#ifdef CONFIG_DM_MMC + struct mmc mmc; + ulong bus_clk_rate; +#endif }; /* Read Atmel MCI IP version */ @@ -58,11 +66,19 @@ static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg) } /* Setup for MCI Clock and Block Size */ +#ifdef CONFIG_DM_MMC +static void mci_set_mode(struct atmel_mci_priv *priv, u32 hz, u32 blklen) +{ + struct mmc *mmc = &priv->mmc; + u32 bus_hz = priv->bus_clk_rate; +#else static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen) { struct atmel_mci_priv *priv = mmc->priv; - atmel_mci_t *mci = priv->mci; u32 bus_hz = get_mci_clk_rate(); +#endif + + atmel_mci_t *mci = priv->mci; u32 clkdiv = 255; unsigned int version = atmel_mci_get_version(mci); u32 clkodd = 0; @@ -202,10 +218,18 @@ io_fail: * Sends a command out on the bus and deals with the block data. * Takes the mmc pointer, a command pointer, and an optional data pointer. */ +#ifdef CONFIG_DM_MMC +static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static int mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct atmel_mci_priv *priv = mmc->priv; +#endif atmel_mci_t *mci = priv->mci; u32 cmdr; u32 error_flags = 0; @@ -335,17 +359,28 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) return 0; } +#ifdef CONFIG_DM_MMC +static int atmel_mci_set_ios(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else /* Entered into mmc structure during driver init */ static int mci_set_ios(struct mmc *mmc) { struct atmel_mci_priv *priv = mmc->priv; +#endif atmel_mci_t *mci = priv->mci; int bus_width = mmc->bus_width; unsigned int version = atmel_mci_get_version(mci); int busw; /* Set the clock speed */ +#ifdef CONFIG_DM_MMC + mci_set_mode(priv, mmc->clock, MMC_DEFAULT_BLKLEN); +#else mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN); +#endif /* * set the bus width and select slot for this interface @@ -374,10 +409,15 @@ static int mci_set_ios(struct mmc *mmc) return 0; } +#ifdef CONFIG_DM_MMC +static int atmel_mci_hw_init(struct atmel_mci_priv *priv) +{ +#else /* Entered into mmc structure during driver init */ static int mci_init(struct mmc *mmc) { struct atmel_mci_priv *priv = mmc->priv; +#endif atmel_mci_t *mci = priv->mci; /* Initialize controller */ @@ -392,11 +432,16 @@ static int mci_init(struct mmc *mmc) writel(~0UL, &mci->idr); /* Set default clocks and blocklen */ +#ifdef CONFIG_DM_MMC + mci_set_mode(priv, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); +#else mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); +#endif return 0; } +#ifndef CONFIG_DM_MMC static const struct mmc_ops atmel_mci_ops = { .send_cmd = mci_send_cmd, .set_ios = mci_set_ios, @@ -456,3 +501,114 @@ int atmel_mci_init(void *regs) return 0; } +#endif + +#ifdef CONFIG_DM_MMC +static const struct dm_mmc_ops atmel_mci_mmc_ops = { + .send_cmd = atmel_mci_send_cmd, + .set_ios = atmel_mci_set_ios, +}; + +static void atmel_mci_setup_cfg(struct atmel_mci_priv *priv) +{ + struct mmc_config *cfg; + u32 version; + + cfg = &priv->cfg; + cfg->name = "Atmel mci"; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + + /* + * If the version is above 3.0, the capabilities of the 8-bit + * bus width and high speed are supported. + */ + version = atmel_mci_get_version(priv->mci); + if ((version & 0xf00) >= 0x300) { + cfg->host_caps = MMC_MODE_8BIT | + MMC_MODE_HS | MMC_MODE_HS_52MHz; + } + + cfg->host_caps |= MMC_MODE_4BIT; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + cfg->f_min = priv->bus_clk_rate / (2 * 256); + cfg->f_max = priv->bus_clk_rate / 2; +} + +static int atmel_mci_enable_clk(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct clk clk; + ulong clk_rate; + int ret = 0; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) { + ret = -EINVAL; + goto failed; + } + + ret = clk_enable(&clk); + if (ret) + goto failed; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) { + ret = -EINVAL; + goto failed; + } + + priv->bus_clk_rate = clk_rate; + +failed: + clk_free(&clk); + + return ret; +} + +static int atmel_mci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct atmel_mci_priv *priv = dev_get_priv(dev); + struct mmc *mmc; + int ret; + + ret = atmel_mci_enable_clk(dev); + if (ret) + return ret; + + priv->mci = (struct atmel_mci *)dev_get_addr_ptr(dev); + + atmel_mci_setup_cfg(priv); + + mmc = &priv->mmc; + mmc->cfg = &priv->cfg; + mmc->dev = dev; + upriv->mmc = mmc; + + atmel_mci_hw_init(priv); + + return 0; +} + +static int atmel_mci_bind(struct udevice *dev) +{ + struct atmel_mci_priv *priv = dev_get_priv(dev); + + return mmc_bind(dev, &priv->mmc, &priv->cfg); +} + +static const struct udevice_id atmel_mci_ids[] = { + { .compatible = "atmel,hsmci" }, + { } +}; + +U_BOOT_DRIVER(atmel_mci) = { + .name = "atmel-mci", + .id = UCLASS_MMC, + .of_match = atmel_mci_ids, + .bind = atmel_mci_bind, + .probe = atmel_mci_probe, + .priv_auto_alloc_size = sizeof(struct atmel_mci_priv), + .ops = &atmel_mci_mmc_ops, +}; +#endif -- 2.11.0

4 3

[U-Boot] [PATCH 0/6] AM43xx OP-TEE support
by Andrew F. Davis 10 Jul '17

10 Jul '17

Hello all, This series brings our firewall and OP-TEE support from DRA7xx/AM57xx family devices to the AM43xx class devices. We do this by factoring out code common code from omap5/ into common mach-omap2/ sources. Then add the hooks for the AM43xx boards. Thanks, Andrew Andrew F. Davis (6): arm: mach-omap2: Move omap5/sec-fxns.c into sec-common.c arm: mach-omap2: Factor out common FDT fixup suport arm: mach-omap2: fdt-common: Add OP-TEE node when firmware node is defined arm: mach-omap2: am33xx: Add FDT fixup suport for AM33xx/AM43xx boards board: ti: am43xx: Add TEE loading and firewall setup board: ti: am43xx: Add FDT fixup for HS devices arch/arm/include/asm/omap_common.h | 5 + arch/arm/include/asm/omap_sec_common.h | 6 + arch/arm/mach-omap2/Kconfig | 26 ++++ arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/am33xx/Makefile | 1 + arch/arm/mach-omap2/am33xx/fdt.c | 43 ++++++ arch/arm/mach-omap2/fdt-common.c | 168 +++++++++++++++++++++ arch/arm/mach-omap2/omap5/Kconfig | 26 ---- arch/arm/mach-omap2/omap5/Makefile | 1 - arch/arm/mach-omap2/omap5/fdt.c | 119 --------------- .../mach-omap2/{omap5/sec-fxns.c => sec-common.c} | 157 ++++++++++++++++++- board/ti/am43xx/board.c | 16 ++ configs/am43xx_hs_evm_defconfig | 4 + 13 files changed, 420 insertions(+), 154 deletions(-) create mode 100644 arch/arm/mach-omap2/am33xx/fdt.c create mode 100644 arch/arm/mach-omap2/fdt-common.c rename arch/arm/mach-omap2/{omap5/sec-fxns.c => sec-common.c} (64%) -- 2.13.0

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[U-Boot] [ANN] U-Boot v2017.07-rc2 released
by Tom Rini 10 Jul '17

10 Jul '17

Hey all, It's release day and v2017.07-rc2 is out. I'm mostly happy with the size of the changes here and I did remember to sync the defconfigs prior to tagging. If anyone has critical fixes I've missed or some Kconfig migrations (that I can prove out as correct), please speak up. Things look on track for -rc3 on July 3rd and release on July 10th. Thanks all! -- Tom

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[U-Boot] [PATCH] arm: zynq: Label whole PL part as fpga_full region
by Michal Simek 10 Jul '17

10 Jul '17

This will simplify dt overlay structure for the whole PL. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynq-7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 34fc6e5f8936..f993e19ef280 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -38,6 +38,14 @@ }; }; + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&devcfg>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; -- 1.9.1

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