June 2017 - U-Boot

[U-Boot] [PATCH 1/3] nds32: mmc: Support ftsdc010 DM.
by Andes 01 Jun '17

01 Jun '17

From: rick <rick(a)andestech.com> Support Andestech ftsdc010 SD/MMC device tree flow on AG101P/AE3XX platforms. Signed-off-by: rick <rick(a)andestech.com> --- drivers/mmc/Kconfig | 12 ++++ drivers/mmc/Makefile | 1 + drivers/mmc/ftsdc010_mci.c | 140 ++++++++++++++++++++++++++++++++++---------- drivers/mmc/ftsdc010_mci.h | 54 +++++++++++++++++ drivers/mmc/nds32_mmc.c | 139 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 316 insertions(+), 30 deletions(-) create mode 100644 drivers/mmc/ftsdc010_mci.h create mode 100644 drivers/mmc/nds32_mmc.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0dd4443..ca1376a 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -377,6 +377,18 @@ config GENERIC_ATMEL_MCI the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1. +config MMC_NDS32 + bool "Andestech SD/MMC controller support" + depends on DM_MMC && OF_CONTROL + help + This enables support for the Andestech SD/MMM controller, which is + based on Faraday IP. + +config FTSDC010 + bool "Ftsdc010 SD/MMC controller Support" + help + This SD/MMC controller is present in Andestech SoCs which is based on Faraday IP. + endif config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a078649..08a552a 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_S3C_SDI) += s3c_sdi.o obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o +obj-$(CONFIG_MMC_NDS32) += nds32_mmc.o # SDHCI obj-$(CONFIG_MMC_SDHCI) += sdhci.o diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 652a718..ec0bc6b 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -12,24 +12,15 @@ #include <part.h> #include <mmc.h> -#include <asm/io.h> +#include <linux/io.h> #include <linux/errno.h> #include <asm/byteorder.h> #include <faraday/ftsdc010.h> +#include "ftsdc010_mci.h" #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ -struct ftsdc010_chip { - void __iomem *regs; - uint32_t wprot; /* write protected (locked) */ - uint32_t rate; /* actual SD clock in Hz */ - uint32_t sclk; /* FTSDC010 source clock in Hz */ - uint32_t fifo; /* fifo depth in bytes */ - uint32_t acmd; - struct mmc_config cfg; /* mmc configuration */ -}; - static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) { struct ftsdc010_chip *chip = mmc->priv; @@ -127,9 +118,8 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) { int ret = -ETIMEDOUT; - uint32_t st, ts; - - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { + uint32_t st, timeout = 10000000; + while (timeout--) { st = readl(&regs->status); if (!(st & mask)) continue; @@ -147,10 +137,16 @@ static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) /* * u-boot mmc api */ - +#ifdef CONFIG_DM_MMC_OPS +static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { +#endif int ret = -EOPNOTSUPP; uint32_t len = 0; struct ftsdc010_chip *chip = mmc->priv; @@ -251,8 +247,14 @@ static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, return ret; } +#ifdef CONFIG_DM_MMC_OPS +static int ftsdc010_set_ios(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static int ftsdc010_set_ios(struct mmc *mmc) { +#endif struct ftsdc010_chip *chip = mmc->priv; struct ftsdc010_mmc __iomem *regs = chip->regs; @@ -274,20 +276,46 @@ static int ftsdc010_set_ios(struct mmc *mmc) return 0; } -static int ftsdc010_init(struct mmc *mmc) +#ifdef CONFIG_DM_MMC_OPS +static int ftsdc010_get_cd(struct udevice *dev) { + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else +static int ftsdc010_getcd(struct mmc *mmc) +{ +#endif struct ftsdc010_chip *chip = mmc->priv; struct ftsdc010_mmc __iomem *regs = chip->regs; - uint32_t ts; - if (readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT) - return -ENOMEDIUM; + return 0; + + return 1; +} +#ifdef CONFIG_DM_MMC_OPS +static int ftsdc010_get_wp(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else +static int ftsdc010_getwp(struct mmc *mmc) +{ +#endif + struct ftsdc010_chip *chip = mmc->priv; + struct ftsdc010_mmc __iomem *regs = chip->regs; if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) { printf("ftsdc010: write protected\n"); chip->wprot = 1; } + return 0; +} + +static int ftsdc010_init(struct mmc *mmc) +{ + struct ftsdc010_chip *chip = mmc->priv; + struct ftsdc010_mmc __iomem *regs = chip->regs; + uint32_t ts; + chip->fifo = (readl(&regs->feature) & 0xff) << 2; /* 1. chip reset */ @@ -311,11 +339,70 @@ static int ftsdc010_init(struct mmc *mmc) return 0; } +#ifdef CONFIG_DM_MMC_OPS +int ftsdc010_probe(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + return ftsdc010_init(mmc); +} + +const struct dm_mmc_ops dm_ftsdc010_ops = { + .send_cmd = ftsdc010_request, + .set_ios = ftsdc010_set_ios, + .get_cd = ftsdc010_get_cd, + .get_wp = ftsdc010_get_wp, +}; + +#else static const struct mmc_ops ftsdc010_ops = { .send_cmd = ftsdc010_request, .set_ios = ftsdc010_set_ios, + .getcd = ftsdc010_getcd, + .getwp = ftsdc010_getwp, .init = ftsdc010_init, }; +#endif + +void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, + uint caps, u32 max_clk, u32 min_clk) +{ + cfg->name = name; + cfg->f_min = min_clk; + cfg->f_max = max_clk; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->host_caps = caps; + if (buswidth == 8) { + cfg->host_caps |= MMC_MODE_8BIT; + cfg->host_caps &= ~MMC_MODE_4BIT; + } else { + cfg->host_caps |= MMC_MODE_4BIT; + cfg->host_caps &= ~MMC_MODE_8BIT; + } + cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; + cfg->part_type = PART_TYPE_DOS; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; +} + +void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg) +{ + switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) { + case FTSDC010_BWR_CAPS_4BIT: + cfg->host_caps |= MMC_MODE_4BIT; + break; + case FTSDC010_BWR_CAPS_8BIT: + cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; + break; + default: + break; + } +} + +#ifdef CONFIG_BLK +int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) +{ + return mmc_bind(dev, mmc, cfg); +} +#else int ftsdc010_mmc_init(int devid) { @@ -345,19 +432,11 @@ int ftsdc010_mmc_init(int devid) #endif chip->cfg.name = "ftsdc010"; +#ifndef CONFIG_DM_MMC_OPS chip->cfg.ops = &ftsdc010_ops; +#endif chip->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; - switch (readl(&regs->bwr) & FTSDC010_BWR_CAPS_MASK) { - case FTSDC010_BWR_CAPS_4BIT: - chip->cfg.host_caps |= MMC_MODE_4BIT; - break; - case FTSDC010_BWR_CAPS_8BIT: - chip->cfg.host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; - break; - default: - break; - } - + set_bus_width(regs , &chip->cfg); chip->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; chip->cfg.f_max = chip->sclk / 2; chip->cfg.f_min = chip->sclk / 0x100; @@ -373,3 +452,4 @@ int ftsdc010_mmc_init(int devid) return 0; } +#endif diff --git a/drivers/mmc/ftsdc010_mci.h b/drivers/mmc/ftsdc010_mci.h new file mode 100644 index 0000000..f74015e --- /dev/null +++ b/drivers/mmc/ftsdc010_mci.h @@ -0,0 +1,54 @@ +/* + * Faraday FTSDC010 Secure Digital Memory Card Host Controller + * + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul(a)andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <mmc.h> + +#ifndef __FTSDC010_MCI_H +#define __FTSDC010_MCI_H + +struct ftsdc010_chip { + void __iomem *regs; + uint32_t wprot; /* write protected (locked) */ + uint32_t rate; /* actual SD clock in Hz */ + uint32_t sclk; /* FTSDC010 source clock in Hz */ + uint32_t fifo; /* fifo depth in bytes */ + uint32_t acmd; + struct mmc_config cfg; /* mmc configuration */ + const char *name; + void *ioaddr; + unsigned int quirks; + unsigned int caps; + unsigned int version; + unsigned int clock; + unsigned int bus_hz; + unsigned int div; + int dev_index; + int dev_id; + int buswidth; + u32 fifoth_val; + struct mmc *mmc; + void *priv; + bool fifo_mode; +}; + + +#ifdef CONFIG_DM_MMC_OPS +/* Export the operations to drivers */ +int ftsdc010_probe(struct udevice *dev); +extern const struct dm_mmc_ops dm_ftsdc010_ops; +#endif +void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, + uint caps, u32 max_clk, u32 min_clk); +void set_bus_width(struct ftsdc010_mmc __iomem *regs, struct mmc_config *cfg); + +#ifdef CONFIG_BLK +int ftsdc010_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); +#endif + + +#endif /* __FTSDC010_MCI_H */ diff --git a/drivers/mmc/nds32_mmc.c b/drivers/mmc/nds32_mmc.c new file mode 100644 index 0000000..ec25fe9 --- /dev/null +++ b/drivers/mmc/nds32_mmc.c @@ -0,0 +1,139 @@ +/* + * Andestech ATFSDC010 SD/MMC driver + * + * (C) Copyright 2016 + * Rick Chen, NDS32 Software Engineering, rick(a)andestech.com + + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-structs.h> +#include <faraday/ftsdc010.h> +#include <errno.h> +#include <mapmem.h> +#include <pwrseq.h> +#include <syscon.h> +#include <mmc.h> +#include <linux/err.h> +#include "ftsdc010_mci.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +struct nds_mmc { + fdt32_t bus_width; + bool cap_mmc_highspeed; + bool cap_sd_highspeed; + fdt32_t card_detect_delay; + fdt32_t clock_freq_min_max[2]; + struct phandle_2_cell clocks[4]; + bool disable_wp; + fdt32_t fifo_depth; + fdt32_t interrupts[3]; + fdt32_t num_slots; + fdt32_t reg[2]; + fdt32_t vmmc_supply; +}; +#endif + +struct nds_mmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct nds_mmc dtplat; +#endif + struct mmc_config cfg; + struct mmc mmc; +}; + +struct ftsdc_priv { + struct clk clk; + struct ftsdc010_chip chip; + int fifo_depth; + bool fifo_mode; + u32 minmax[2]; +}; + +static int nds32_mmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct ftsdc_priv *priv = dev_get_priv(dev); + struct ftsdc010_chip *chip = &priv->chip; + chip->name = dev->name; + chip->ioaddr = (void *)dev_get_addr(dev); + chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); + chip->priv = dev; + /* use non-removeable as sdcard and emmc as judgement */ + if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable")) + chip->dev_index = 0; + else + chip->dev_index = 1; + + priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "fifo-depth", 0); + priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "fifo-mode"); + if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "clock-freq-min-max", priv->minmax, 2)) + return -EINVAL; +#endif + chip->sclk = priv->minmax[1]; + chip->regs = chip->ioaddr; + return 0; +} + +static int nds32_mmc_probe(struct udevice *dev) +{ + struct nds_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct ftsdc_priv *priv = dev_get_priv(dev); + struct ftsdc010_chip *chip = &priv->chip; + struct udevice *pwr_dev __maybe_unused; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + int ret; + struct nds_mmc *dtplat = &plat->dtplat; + chip->name = dev->name; + chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); + chip->buswidth = dtplat->bus_width; + chip->priv = dev; + chip->dev_index = 0; + priv->fifo_depth = dtplat->fifo_depth; + priv->fifo_mode = 0; + memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); + ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); + if (ret < 0) + return ret; +#endif + ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps, + priv->minmax[1] , priv->minmax[0]); + chip->mmc = &plat->mmc; + chip->mmc->priv = &priv->chip; + chip->mmc->dev = dev; + upriv->mmc = chip->mmc; + return ftsdc010_probe(dev); +} + +static int nds32_mmc_bind(struct udevice *dev) +{ + struct nds_mmc_plat *plat = dev_get_platdata(dev); + return ftsdc010_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id nds32_mmc_ids[] = { + { .compatible = "andestech,atsdc010" }, + { } +}; + +U_BOOT_DRIVER(nds32_mmc_drv) = { + .name = "nds32_mmc", + .id = UCLASS_MMC, + .of_match = nds32_mmc_ids, + .ofdata_to_platdata = nds32_mmc_ofdata_to_platdata, + .ops = &dm_ftsdc010_ops, + .bind = nds32_mmc_bind, + .probe = nds32_mmc_probe, + .priv_auto_alloc_size = sizeof(struct ftsdc_priv), + .platdata_auto_alloc_size = sizeof(struct nds_mmc_plat), +}; -- 1.7.9.5

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[U-Boot] [PATCH v5 0/16] sunxi: Add support for the CHIP Pro
by Maxime Ripard 01 Jun '17

01 Jun '17

The CHIP Pro is a SoM made by NextThing Co, and that embeds a GR8 SIP, an AXP209 PMIC, a WiFi BT chip and a 512MB SLC NAND. Since the first Allwinner device coming whit an SLC NAND that doesn't have the shortcomings (and breakages) the MLC NAND has, we can finally enable the NAND support on a board by default. This is the occasion to introduce a bunch of additions needed imo to be able to come up with a sane NAND support for our users. The biggest pain point is that the BROM uses a different ECC and randomizer configuration than for the rest of the NAND. In order to lessen the number of bitflips, you also need to pad with random data the SPL image. Since it's quite tedious to do right (and most users won't be able to figure it out) and since if it is not done right, it will eventually turn into an unusable system (which is bad UX), we think that the best solution is to generate an SPL image that already embeds all this. We'll possible have to do the same thing for the U-Boot image (at least for the random padding) on MLC NANDs. The only drawback from that is that you need to flash it raw, instead of using the usual nand write, but it's just a different command, nothing major anyway. In order to flash it, from a device switched in FEL, on your host: sunxi-fel spl spl/sunxi-spl.bin sunxi-fel write 0x4a000000 u-boot-dtb.bin sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin sunxi-fel exe 0x4a000000 And on the board, once u-boot is running (assuming the NAND is already erased): nand write.raw.noverify 0x43000000 0 40 nand write.raw.noverify 0x43000000 0x400000 40 nand write 0x4a000000 0x800000 0xc0000 I also encountered some weird bug in the private libgcc that prevents U-Boot from loading. Disabling CONFIG_USE_PRIVATE_LIBGCC fixes that. Let me know what you think, Maxime Changes from v4: - Rebased on top of last pull request - Removed irrelevant config options Changes from v3: - Bring new Kconfig patches from Boris - Do not define Kconfig defaults in our board Kconfig but directly in the option declaration - Sync the DT with the kernel - Fixed build breakages Changes from v2: - Move CMD_NAND and CMD_UBI default to cmd/Kconfig - Define the env Kconfig options only for ARCH_SUNXI to avoid build breakages - Define CMD_MTDPARTS only for ARCH_SUNXI Changes from v1: - Allowed to build lib/bch.c for the host, and used that in the image builder - Fixed a bug in the NAND driver - Wrote a documentation on how to flash a NAND image on an Allwinner board - Fixed a few compilation breakages and issues - Moved U-boot offset out of the config header and into Kconfig - Moved the environment into UBI - Moved the environment selection to Kconfig - Moved the CMD_MTDPARTS options to Kconfig - Provide MTDIDS_DEFAULT and MTDPARTS_DEFAULT options through Kconfig - Added the tags from everyone Boris Brezillon (3): mtd: ubi: Select RBTREE option from MTD_UBI Kconfig entry cmd: Expose a Kconfig option to enable UBIFS commands cmd: nand: Expose optional suboptions in Kconfig Hans de Goede (1): sunxi: Enable UBI and NAND support Maxime Ripard (12): nand: sunxi: Fix modulo by zero error bch: Allow to build for the host tools: sunxi: Add spl image builder common: Move environment choice to Kconfig cmd: Add Kconfig option for CMD_MTDPARTS and related options mtd: sunxi: Select the U-Boot location config option mtd: sunxi: Change U-Boot offset sunxi: Add the default mtdids and mtdparts to our env nand: sunxi: Add options for the SPL NAND configuration scripts: sunxi: Build an raw SPL image sunxi: Sync GR8 DTS and AXP209 with the kernel sunxi: Add support for the CHIP Pro Makefile | 3 +- arch/arm/dts/Makefile | 1 +- arch/arm/dts/axp209.dtsi | 6 +- arch/arm/dts/sun5i-gr8-chip-pro.dts | 266 +++++++- arch/arm/dts/sun5i-gr8.dtsi | 1132 ++++++++++++++++++++++++++++- board/sunxi/README.nand | 54 +- cmd/Kconfig | 50 +- cmd/mtdparts.c | 8 +- common/Kconfig | 69 ++- configs/CHIP_pro_defconfig | 33 +- drivers/mtd/nand/Kconfig | 19 +- drivers/mtd/nand/sunxi_nand_spl.c | 7 +- drivers/mtd/ubi/Kconfig | 1 +- include/configs/sunxi-common.h | 33 +- include/environment.h | 2 +- lib/Kconfig | 5 +- lib/bch.c | 48 +- scripts/Makefile.spl | 15 +- tools/.gitignore | 1 +- tools/Makefile | 2 +- tools/sunxi-spl-image-builder.c | 484 ++++++++++++- 21 files changed, 2224 insertions(+), 15 deletions(-) create mode 100644 arch/arm/dts/sun5i-gr8-chip-pro.dts create mode 100644 arch/arm/dts/sun5i-gr8.dtsi create mode 100644 board/sunxi/README.nand create mode 100644 configs/CHIP_pro_defconfig create mode 100644 tools/sunxi-spl-image-builder.c base-commit: 35affe7698e95c058a1f6c7eb2e1bf35f82461c9 -- git-series 0.8.11

6 29

[U-Boot] [PATCH 3/3] nds32: board: Support ftsdc010 DM.
by Andes 01 Jun '17

01 Jun '17

From: rick <rick(a)andestech.com> Support Andestech ftsdc010 SD/MMC device tree flow on AG101P/AE3XX platforms. Signed-off-by: rick <rick(a)andestech.com> --- board/AndesTech/adp-ae3xx/adp-ae3xx.c | 4 +--- board/AndesTech/adp-ag101p/adp-ag101p.c | 7 +------ configs/adp-ae3xx_defconfig | 5 +++++ configs/adp-ag101p_defconfig | 5 +++++ include/configs/adp-ae3xx.h | 1 - include/configs/adp-ag101p.h | 1 - 6 files changed, 12 insertions(+), 11 deletions(-) diff --git a/board/AndesTech/adp-ae3xx/adp-ae3xx.c b/board/AndesTech/adp-ae3xx/adp-ae3xx.c index 98ed4d9..3903427 100644 --- a/board/AndesTech/adp-ae3xx/adp-ae3xx.c +++ b/board/AndesTech/adp-ae3xx/adp-ae3xx.c @@ -77,10 +77,8 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) int board_mmc_init(bd_t *bis) { -#ifndef CONFIG_DM_MMC -#ifdef CONFIG_FTSDC010 +#if defined(CONFIG_FTSDC010) && !defined(CONFIG_DM_MMC) ftsdc010_mmc_init(0); #endif -#endif return 0; } diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c index a462941..826ba14 100644 --- a/board/AndesTech/adp-ag101p/adp-ag101p.c +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -20,7 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; /* * Miscellaneous platform dependent initializations */ - int board_init(void) { /* @@ -30,7 +29,6 @@ int board_init(void) printf("Board: %s\n" , CONFIG_SYS_BOARD); gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P; gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; - return 0; } @@ -39,11 +37,8 @@ int dram_init(void) unsigned long sdram_base = PHYS_SDRAM_0; unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE; unsigned long actual_size; - actual_size = get_ram_size((void *)sdram_base, expected_size); - gd->ram_size = actual_size; - if (expected_size != actual_size) { printf("Warning: Only %lu of %lu MiB SDRAM is working\n", actual_size >> 20, expected_size >> 20); @@ -83,7 +78,7 @@ ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) int board_mmc_init(bd_t *bis) { -#ifdef CONFIG_FTSDC010 +#if defined(CONFIG_FTSDC010) && !defined(CONFIG_DM_MMC) ftsdc010_mmc_init(0); #endif return 0; diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig index cbef412..d12f307 100644 --- a/configs/adp-ae3xx_defconfig +++ b/configs/adp-ae3xx_defconfig @@ -18,6 +18,11 @@ CONFIG_BAUDRATE=38400 CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_BLK=y +CONFIG_DM_MMC=y +CONFIG_DM_MMC_OPS=y +CONFIG_MMC_NDS32=y +CONFIG_FTSDC010=y CONFIG_MTD=y CONFIG_CFI_FLASH=y CONFIG_DM_ETH=y diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig index 22b1182..85e2225 100644 --- a/configs/adp-ag101p_defconfig +++ b/configs/adp-ag101p_defconfig @@ -18,6 +18,11 @@ CONFIG_BAUDRATE=38400 CONFIG_OF_CONTROL=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_BLK=y +CONFIG_DM_MMC=y +CONFIG_DM_MMC_OPS=y +CONFIG_MMC_NDS32=y +CONFIG_FTSDC010=y CONFIG_DM_ETH=y CONFIG_FTMAC100=y CONFIG_DM_SERIAL=y diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h index 6bfc08e..011b2a8 100644 --- a/include/configs/adp-ae3xx.h +++ b/include/configs/adp-ae3xx.h @@ -92,7 +92,6 @@ /* * SD (MMC) controller */ -#define CONFIG_FTSDC010 #define CONFIG_FTSDC010_NUMBER 1 #define CONFIG_FTSDC010_SDIO diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h index 4cef64e..71a557b 100644 --- a/include/configs/adp-ag101p.h +++ b/include/configs/adp-ag101p.h @@ -98,7 +98,6 @@ /* * SD (MMC) controller */ -#define CONFIG_FTSDC010 #define CONFIG_FTSDC010_NUMBER 1 #define CONFIG_FTSDC010_SDIO -- 1.7.9.5

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[U-Boot] [PATCH 2/3] nds32: dts: Support ftsdc010 DM.
by Andes 01 Jun '17

01 Jun '17

From: rick <rick(a)andestech.com> Support Andestech ftsdc010 SD/MMC device tree flow on AG101P/AE3XX platforms. Signed-off-by: rick <rick(a)andestech.com> --- arch/nds32/dts/ae3xx.dts | 8 ++++++++ arch/nds32/dts/ag101p.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts index 4221e4b..781eabc 100644 --- a/arch/nds32/dts/ae3xx.dts +++ b/arch/nds32/dts/ae3xx.dts @@ -62,6 +62,14 @@ interrupts = <25 4>; }; + mmc0: mmc@f0e00000 { + compatible = "andestech,atsdc010"; + clock-freq-min-max = <400000 100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <17 4>; + }; + nor@0,0 { compatible = "cfi-flash"; reg = <0x88000000 0x1000>; diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts index 99cde2f..dd2bf8f 100644 --- a/arch/nds32/dts/ag101p.dts +++ b/arch/nds32/dts/ag101p.dts @@ -60,4 +60,12 @@ reg = <0x90900000 0x1000>; interrupts = <25 4>; }; + + mmc0: mmc@98e00000 { + compatible = "andestech,atsdc010"; + clock-freq-min-max = <400000 30000000>; + fifo-depth = <0x10>; + reg = <0x98e00000 0x1000>; + interrupts = <5 4>; + }; }; -- 1.7.9.5

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[U-Boot] [PATCH 00/26] dm: tegra: Move nyan-big to livetree
by Simon Glass 01 Jun '17

01 Jun '17

This moves an entire board to use a live device tree as an example of the impact. Nyan-big was chosen because I can easily and boot U-Boot without any media swapping, etc. Total code size impact on this board is approximately 9KB on U-Boot and 64 bytes on SPL: 27: dm: tegra: nyan-big: Move to livetree arm: (for 1/1 boards) all +9264.0 bss -16.0 data +44.0 rodata +92.0 spl/u-boot-spl:all +326.0 spl/u-boot-spl:rodata +262.0 spl/u-boot-spl:text +64.0 text +9144.0 Tegra does not use Thumb2, which would likely reduce the code size by about 25%, indicating a code-size impact of perhaps 7KB. I have not yet collected reliable detailed timing information. I will do that with the next version of this series, after comments are received. I expect that building the live tree will take a little time, and that using it will be very slightly faster. The use of livetree is controlled by a the CONFIG_OF_LIVE option. When enabled, U-Boot builds a livetree immediately after relocation and uses it from then on. This series is available at u-boot-dm/livet-working (note that some work remains for apalis-tk1, jetson-tk1, cei-tk1-som) Simon Glass (26): dm: video: Sync display on backspace dm: video: Update pwm_backlight to support livetree video: simple-panel: Add a little more debugging tegra: Fix up include file ordering tegra: spl: Enable debug UART tegra: nyan: Add a PMC syscon driver dm: tegra: Convert USB setup to livetree dm: tegra: Convert clock_decode_periph_id() to support livetree dm: video: tegra124: Convert to livetree tegra: dts: Move stdout-path to /chosen tegra: Don't set up the UART clocks again in U-Boot dm: tegra: gpio: Convert to support livetree dm: tegra: usb: Convert to livetree dm: tegra: spi: Convert to livetree dm: tegra: i2c: Convert to livetree dm: tegra: pwm: Convert to livetree dm: tegra: mmc: Convert to livetree power: Add a regulator driver for the as3722 PMIC power: Add a GPIO driver for the as3722 PMIC dm: power: Convert as3722 to driver model dm: serial: ns16550: Convert to livetree dm: serial: Separate out the core serial-device finding code dm: serial: Add livetree support tegra: Show a debug message if the LCD PMIC fails to start fdtdec: Drop old compatible values dm: tegra: nyan-big: Move to livetree arch/arm/dts/tegra124-nyan-big.dts | 5 +- arch/arm/include/asm/arch-tegra/clock.h | 2 +- arch/arm/include/asm/arch-tegra/tegra.h | 5 + arch/arm/include/asm/arch-tegra/xusb-padctl.h | 2 +- arch/arm/mach-tegra/board.c | 2 + arch/arm/mach-tegra/board2.c | 34 ++- arch/arm/mach-tegra/clock.c | 9 +- arch/arm/mach-tegra/spl.c | 4 + arch/arm/mach-tegra/tegra124/Makefile | 1 + arch/arm/mach-tegra/tegra124/pmc.c | 19 ++ arch/arm/mach-tegra/tegra124/xusb-padctl.c | 36 +++- arch/arm/mach-tegra/tegra210/xusb-padctl.c | 40 +++- arch/arm/mach-tegra/xusb-padctl-common.c | 84 ++++---- arch/arm/mach-tegra/xusb-padctl-common.h | 11 +- arch/arm/mach-tegra/xusb-padctl-dummy.c | 2 +- board/nvidia/nyan-big/nyan-big.c | 22 +- configs/nyan-big_defconfig | 4 + drivers/gpio/tegra_gpio.c | 10 +- drivers/i2c/tegra_i2c.c | 6 +- drivers/mmc/tegra_mmc.c | 17 +- drivers/power/pmic/Makefile | 2 +- drivers/power/pmic/as3722.c | 292 +++++++++----------------- drivers/power/pmic/as3722_gpio.c | 120 +++++++++++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/as3722_regulator.c | 149 +++++++++++++ drivers/pwm/tegra_pwm.c | 2 +- drivers/serial/ns16550.c | 15 +- drivers/serial/serial-uclass.c | 92 ++++---- drivers/spi/tegra114_spi.c | 15 +- drivers/spi/tegra20_sflash.c | 2 +- drivers/spi/tegra20_slink.c | 2 +- drivers/spi/tegra210_qspi.c | 2 +- drivers/usb/host/ehci-tegra.c | 36 ++-- drivers/video/pwm_backlight.c | 23 +- drivers/video/simple_panel.c | 2 + drivers/video/tegra124/display.c | 8 +- drivers/video/tegra124/dp.c | 3 +- drivers/video/tegra124/sor.c | 25 +-- drivers/video/vidconsole-uclass.c | 1 + include/fdtdec.h | 6 - include/power/as3722.h | 27 ++- lib/fdtdec.c | 6 - 43 files changed, 699 insertions(+), 456 deletions(-) create mode 100644 arch/arm/mach-tegra/tegra124/pmc.c create mode 100644 drivers/power/pmic/as3722_gpio.c create mode 100644 drivers/power/regulator/as3722_regulator.c -- 2.13.0.303.g4ebf302169-goog

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[U-Boot] [PATCH v3 0/4] Extend xhci-dwc3
by patrice.chotard＠st.com 01 Jun '17

01 Jun '17

From: Patrice Chotard <patrice.chotard(a)st.com> v3: _ introduce generic_phy_valid() method _ add Reviewed-by v2: _ use dev_get_addr() in PATCH 1 and removed useless piece of code Patrice Chotard (4): usb: host: xhci-dwc3: Convert driver to DM usb: host: xhci-dwc3: Add dual role mode support from DT drivers: phy: add generic_phy_valid() method usb: host: xhci-dwc3: Add generic PHY support drivers/phy/phy-uclass.c | 5 +++ drivers/usb/host/xhci-dwc3.c | 91 ++++++++++++++++++++++++++++++++++++++++++++ include/generic-phy.h | 8 ++++ 3 files changed, 104 insertions(+) -- 1.9.1

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[U-Boot] [PATCH v4 00/11] usb: Extend ehci and ohci generic drivers
by patrice.chotard＠st.com 01 Jun '17

01 Jun '17

From: Patrice Chotard <patrice.chotard(a)st.com> This series improves generic ehci and ohci drivers by addition of : _ error path during probe (clocks, resets and phy release) _ .remove callback _ add generic PHY framework for both generic ehci and ohci drivers _ add RESET and CLOCK framework for generic ohci driver To implement these features, some new methods are needed in RESET and CLOCKS frameworks : _ add reset_request(), reset_count() and reset_assert_all() methods in RESET framework _ add clk_count() and add clk_disable_all() methods in CLOCK framework v4: _ add clk_disable_all() and reset_assert_all() methods into CLOCK and RESET framework as suggested by Simon Glass and Marek Vasut _ add reset_count() and clk_count() methods which returns respectively the number of resets and clocks declared into "resets" and "clocks" DT properties. This allows to allocate the right amount of memory to keep resets and clocks reference _ update the memory allocation for deasserted resets and enabled clocks reference list. Replace lists by arrays. v3: _ keep enabled clocks and deasserted resets reference in list in order to disable clock or assert resets in error path or in .remove callback _ add missing commit message _ use struct generic_ehci * instead of struct udevice * as parameter for ehci_release_resets() and ehci_release_clocks() _ test return value on generic_phy_get_by_index() and generic_phy_init() _ split previous patch 5 in 3 independant patch for CLOCK, RESET and PHY support v2: _ add needed reset_request() in RESET framework _ add error path in ehci/ohci-generic to disable clocks and to assert resets _ add .remove callback with clocks, resets and phy release _ split the replacement of printf() by error() in an independant patch Patrice Chotard (11): reset: add reset_request() reset: add reset_count() reset: add reset_assert_all() clk: add clk_count() clk: add clk_disable_all() usb: host: ehci-generic: replace printf() by error() usb: host: ehci-generic: add error path and .remove callback usb: host: ehci-generic: add generic PHY support usb: host: ohci-generic: add CLOCK support usb: host: ohci-generic: add RESET support usb: host: ohci-generic: add generic PHY support drivers/clk/clk-uclass.c | 34 ++++++++++ drivers/reset/reset-uclass.c | 45 +++++++++++++ drivers/usb/host/ehci-generic.c | 142 +++++++++++++++++++++++++++++++++------- drivers/usb/host/ohci-generic.c | 121 +++++++++++++++++++++++++++++++++- include/clk.h | 22 +++++++ include/reset.h | 37 +++++++++++ 6 files changed, 376 insertions(+), 25 deletions(-) -- 1.9.1

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[U-Boot] Uboot send pull request
by uboot＠andestech.com 01 Jun '17

01 Jun '17

Hi Tom, Please pull the following patch from u-boot-nds32 into your tree. Thanks! The following changes since commit ccbbada0a59fead35495409d0c2c7bcb22a40278: Merge branch 'master' of git://git.denx.de/u-boot-mmc (2017-05-30 14:07:23 -0400) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to 4099090fd0ed9c03d6b90c1382921e7184946878: nds32: board: Support ftsdc010 DM. (2017-06-01 09:11:19 +0800) ---------------------------------------------------------------- rick (3): nds32: mmc: Support ftsdc010 DM. nds32: dts: Support ftsdc010 DM. nds32: board: Support ftsdc010 DM. arch/nds32/dts/ae3xx.dts | 8 ++ arch/nds32/dts/ag101p.dts | 8 ++ board/AndesTech/adp-ae3xx/adp-ae3xx.c | 4 +- board/AndesTech/adp-ag101p/adp-ag101p.c | 7 +- configs/adp-ae3xx_defconfig | 5 ++ configs/adp-ag101p_defconfig | 5 ++ drivers/mmc/Kconfig | 12 +++ drivers/mmc/Makefile | 1 + drivers/mmc/ftsdc010_mci.c | 140 ++++++++++++++++++++++++------- drivers/mmc/ftsdc010_mci.h | 54 ++++++++++++ drivers/mmc/nds32_mmc.c | 139 ++++++++++++++++++++++++++++++ include/configs/adp-ae3xx.h | 1 - include/configs/adp-ag101p.h | 1 - 13 files changed, 344 insertions(+), 41 deletions(-) create mode 100644 drivers/mmc/ftsdc010_mci.h create mode 100644 drivers/mmc/nds32_mmc.c

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[U-Boot] Add ethernet support to Banana-Pi M2U
by Duncan Hare 01 Jun '17

01 Jun '17

Banana Pi BPI-M2 Ultra is a quad-core mini single board computer built with Allwinner R40 SoC. It features 2GB of RAM and 8GB eMMC. Duncan Hare 714 931 7952

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[U-Boot] Add Ethernet Support for Banana Pi M64
by Duncan Hare 01 Jun '17

01 Jun '17

BPI-M64 is a 64-bit quad-core mini single board computer using the Allwinner A64 SOC. BPI-M64 features - 1.2 Ghz Quad-Core ARM Cortex A53 - 2GB DDR3 SDRAM with 733MHz - MicroSD/eMMC(8GB) - 10/100/1000Mbps ethernet (Realtek RTL8211E/D) - Wifi + BT - IR receiver - Audio In/Out - Video In/Out - 5V 2A DC power-supply Duncan Hare 714 931 7952

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