April 2017 - U-Boot

[U-Boot] U-boot-sunxi status?
by Chen-Yu Tsai 21 Apr '17

21 Apr '17

Hi, (Resent from my main email address.) What's the current status of u-boot-sunxi? There are still some patch series floating around. Some of them have been around for a while now, listed here in no particular order: - sunxi: Add support for R40 SoC v2 (by Chen-Yu Tsai) - sunxi: Remove SYS_EXTRA_OPTIONS v3 (by Mylene Josserand) - sunxi: video: Add support for HDMI output on A64/H3/H5 v3 (by Jernej Skrabec) - Allwinner V3s and Lichee Pi Zero support (w/o SPL) v5 (by Icenowy Zheng) - Allwinner DesignWare-like DRAM controllers refactor v1 (by Icenowy Zheng) - Various DM related patch series from Philipp Tomsich Also sunxi related but probably not going through u-boot-sunxi: - SPL: extend FIT loading support v3 (by Andre Przywara) - Retrieve MAC address from EEPROM v5 (by Olliver Schinagl) Some of these series have been fully reviewed, others only partially. I'm sure there are more out there, but I don't track U-boot patches as closely as kernel patches. So how can we help getting all these things ready and merged? Regards ChenYu

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[U-Boot] AM335x Falcon Mode
by ayoub.zaki＠embexus.com 21 Apr '17

21 Apr '17

Hi Everyone, I'm trying to boot a Beaglebone-Black using Falcon Mode, so far no luck ! I'm using manline u-boot version v2017.01 configured using am335x_boneblack_defconfig and no other source changes. Here are the steps I performed running from an SD card (Fat Partition) : U-Boot SPL 2017.01-dirty (Apr 18 2017 - 22:57:12) Trying to boot from MMC1MMC partition switch failed *** Warning - MMC partition switch failed, using default environment reading u-boot.img reading u-boot.img U-Boot 2017.01-dirty (Apr 18 2017 - 22:57:12 +0200) CPU : AM335X-GP rev 2.1 I2C: ready DRAM: 512 MiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 ** First descriptor is NOT a primary desc on 1:1 ** Net: cpsw, usb_ether Press SPACE to abort autoboot in 2 seconds => run args_mmc => run loadimage 8942296 bytes read in 610 ms (14 MiB/s) => run loadfdt 58129 bytes read in 56 ms (1013.7 KiB/s) => spl export fdt ${loadaddr} - ${fdtaddr} data abort pc : [<9ff5e4e8>] lr : [<9ff63925>] reloc pc : [<8080c4e8>] lr : [<80811925>] sp : 9df31be8 ip : 9ff8c349 fp : 9ffa124c r10: 9df31c84 r9 : 9df31ed8 r8 : 9ffa124c r7 : 00000007 r6 : 82000000 r5 : 9ffa124c r4 : 00000000 r3 : 00000000 r2 : 9ff8c530 r1 : 82000000 r0 : 9ff90251 Flags: Nzcv IRQs off FIQs on Mode SVC_32 Resetting CPU ... resetting ... Aynone could give me some hints? Thank you ! Best Regards, Ayoub Zaki

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[U-Boot] [PATCH resend v2 00/13] sunxi: Add support for R40 SoC
by Chen-Yu Tsai 21 Apr '17

21 Apr '17

Hi everyone, This is a resend of my Allwinner R40 SoC support series v2. This is rebased on v2017.05-rc2. Maxime's ack for the first two patches have been added, and the defconfig has been regenerated which moved the CONFIG_SPL_I2C_SUPPORT=y line around. The patches can also be found here: https://github.com/wens/u-boot-sunxi/tree/r40 Original v2 cover letter: This is v2 of my Allwinner R40 SoC support series. Changes since v1: - Add Maxime's ack for all but the first patch. - Add a patch to split up very long Kconfig lines. This series adds support for the new R40 SoC. The R40 is marketed as the successor to the A20. It is mostly pin compatible (in software) with the A20. It has a somewhat similar memory layout, a hybrid of A20 and newer sun6i gen.. Like the A20, it does not have a PRCM block. Checkpatch throws out a lot of errors, mostly "no spaces at the start of a line" or "space prohibited after that open parenthesis '('", but fixing them does not improve the readability of the code. Patch 1 splits up some very long Kconfig lines. (new in v2) Patch 2 introduces the R40 to U-boot, by adding a Kconfig symbol, fixing up any SoC depends on in Kconfig to disable unsupported features, and reworking board level pinmuxes. Patch 3 enables using the AXP221s PMIC in I2C mode. The R40 is paired with this PMIC, but it does not have a P2WI controller. Patch 4 fixes the watchdog reset function for R40. The R40's watchdog register layout is like the A10/A20. Patch 5 adds mmc pinmux settings for R40. Patch 6 fixes the PLL lock settings for the R40. The R40's CCU has a new mode for PLL lock, which can be configured and also switched back to the old mode. Here we just use the old mode, which is the same as the other sun6i gen. SoCs. Patch 7 provides some default DRAM settings for the R40. These were taken from the Bananapi M2 Ultra, the only R40 board available. Patch 8 adds the compatible string for the R40 PIO. It is mostly compatible with the A20, with a few functions gone, and a few new ones. Patch 9 adds DRAM initialization support for the R40. The DRAM controller is very similar to the A64 and H5, however the A15 line and CSC1 line are muxed on the same pin. Also the PIR_QSGATE bit must not be set, or DRAM init fails. Patch 10 enables SPL for R40. Patch 11 fixes the address of the CPUCFG block on the R40. It is the same as on the A20. Patch 12 adds a PSCI implementation for the R40. As the register layout is slightly erratic, we just use a macro for the ones that can't fit into the cpucfg register definition structure. Patch 13 adds a board dts and defconfig for the Bananapi M2 Ultra. Please have a look. Regards ChenYu Chen-Yu Tsai (13): sunxi: Split up long Kconfig lines sunxi: Add initial support for R40 sunxi: Enable AXP221s in I2C mode with the R40 SoC sunxi: Fix watchdog reset function for R40 sunxi: Add mmc[1-3] pinmux settings for R40 sunxi: Set PLL lock enable bits for R40 sunxi: Provide defaults for R40 DRAM settings gpio: sunxi: Add compatible string for R40 PIO sunxi: Use H3/A64 DRAM initialization code for R40 sunxi: Enable SPL for R40 sunxi: Fix CPUCFG address for R40 sunxi: Add PSCI support for R40 sunxi: Add support for Bananapi M2 Ultra arch/arm/cpu/armv7/sunxi/psci.c | 35 ++++- arch/arm/dts/Makefile | 2 + arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 69 +++++++++ arch/arm/dts/sun8i-r40.dtsi | 183 ++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 2 + arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 +- arch/arm/include/asm/arch-sunxi/dram.h | 4 +- arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h | 20 ++- arch/arm/include/asm/arch-sunxi/timer.h | 5 +- arch/arm/include/asm/arch-sunxi/watchdog.h | 5 +- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/board.c | 15 +- arch/arm/mach-sunxi/clock_sun6i.c | 9 +- arch/arm/mach-sunxi/cpu_info.c | 2 + arch/arm/mach-sunxi/dram_sun8i_h3.c | 121 ++++++++++++++-- arch/arm/mach-sunxi/pmic_bus.c | 7 + board/sunxi/Kconfig | 41 +++++- board/sunxi/MAINTAINERS | 6 + board/sunxi/board.c | 36 ++++- configs/Bananapi_M2_Ultra_defconfig | 15 ++ drivers/gpio/sunxi_gpio.c | 1 + drivers/power/Kconfig | 16 ++- 23 files changed, 550 insertions(+), 52 deletions(-) create mode 100644 arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts create mode 100644 arch/arm/dts/sun8i-r40.dtsi create mode 100644 configs/Bananapi_M2_Ultra_defconfig -- 2.11.0

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[U-Boot] [PATCH v2 00/14] STiH410-B2260: add reset, usb and fastboot support
by patrice.chotard＠st.com 21 Apr '17

21 Apr '17

From: Patrice Chotard <patrice.chotard(a)st.com> This series adds : _ add reset driver _ update existing sdhci driver to use reset framework _ add usb phy driver _ add ehci support _ add ohci support _ add xhci support _ add fastboot support With all this feature enable, it's now possible to _ boot on usb mass storage device _ boot from kernel image and dtb previously loaded using tftp _ update mmc partiton using fastboot v2: _ add Reviewed-by: Jaehoon Chung <jh80.chung(a)samsung.com> in patches 2,3 and 4 _ fix remarks done by Marek Vasut : _ patch 5 : replace bitfield_replace() by clrsetbits_le32() _ patch 6 : update error messages and add remove callback _ patch 8 : put board specific defines in a separate patch _ patch 7: use setbits_le32() instead of read, modify, write sequence and add missing parenthesis _ squash previous patches 7,9,11,12,14,16,17,18,19,20 and 21 in patch 14 Patrice Chotard (14): reset: Add STi reset support mmc: sti_sdhci: Rework sti_mmc_core_config() ARM: dts: stih410-family: Add missing reset_names for mmc1 node mmc: sti_sdhci: Use reset framework phy: Add STi phy usb support usb: ehci: Add STi ehci support usb: ohci: Add STi ohci support board: STiH410-B2260: add OHCI related defines usb: xhci: Add STi xhci support board: STiH410-B2260: add XHCI related define usb: dwc3: Add dwc3 support for STi board: STiH410-B2260: add fastboot support STiH410-B2260: enable USB Host Networking STiH410-B2260: enable USB, fastboot, reset related flags arch/arm/Kconfig | 1 + arch/arm/dts/stih407-family.dtsi | 1 + arch/arm/include/asm/arch-stih410/sys_proto.h | 11 + board/st/stih410-b2260/board.c | 44 ++++ configs/stih410-b2260_defconfig | 36 ++- drivers/mmc/sti_sdhci.c | 60 +++-- drivers/reset/Kconfig | 8 + drivers/reset/Makefile | 1 + drivers/reset/sti-reset.c | 320 ++++++++++++++++++++++++++ drivers/usb/Kconfig | 4 + drivers/usb/dwc3/Kconfig | 8 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-sti.c | 135 +++++++++++ drivers/usb/host/Kconfig | 26 +++ drivers/usb/host/Makefile | 3 + drivers/usb/host/ehci-sti.c | 115 +++++++++ drivers/usb/host/ohci-sti.c | 90 ++++++++ drivers/usb/host/xhci-sti.c | 156 +++++++++++++ drivers/usb/phy/Kconfig | 11 + drivers/usb/phy/Makefile | 1 + drivers/usb/phy/sti_phy_usb.c | 153 ++++++++++++ include/configs/stih410-b2260.h | 16 ++ include/dwc3-sti-uboot.h | 50 ++++ 23 files changed, 1225 insertions(+), 26 deletions(-) create mode 100644 arch/arm/include/asm/arch-stih410/sys_proto.h create mode 100644 drivers/reset/sti-reset.c create mode 100644 drivers/usb/dwc3/dwc3-sti.c create mode 100644 drivers/usb/host/ehci-sti.c create mode 100644 drivers/usb/host/ohci-sti.c create mode 100644 drivers/usb/host/xhci-sti.c create mode 100644 drivers/usb/phy/Kconfig create mode 100644 drivers/usb/phy/sti_phy_usb.c create mode 100644 include/dwc3-sti-uboot.h -- 1.9.1

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[U-Boot] (no subject)
by Zhikang Zhang 21 Apr '17

21 Apr '17

Test for NVMe driver: platform: LS1046AQDS NVMe SSD: Intel P3700 400G The test logs are as follow: ---------------------------- => nvme list Device 0: Vendor: 0x8086 Rev: 8DV10131 Prod: CVFT535600LS400BGN Type: Hard Disk Capacity: 381554.0 MB = 372.6 GB (781422768 x 512) => nvme device 0 Device 0: Vendor: 0x8086 Rev: 8DV10131 Prod: CVFT535600LS400BGN Type: Hard Disk Capacity: 381554.0 MB = 372.6 GB (781422768 x 512) ... is now current device => nvme info Blk device 0: Optional Admin Command Support: Namespace Management/Attachment: no Firmware Commit/Image download: yes Format NVM: yes Security Send/Receive: no Blk device 0: Optional NVM Command Support: Reservation: no Save/Select field in the Set/Get features: no Write Zeroes: yes Dataset Management: yes Write Uncorrectable: no Blk device 0: Format NVM Attributes: Support Cryptographic Erase: yes Support erase a particular namespace: No Support format a particular namespace: No Blk device 0: LBA Format Support: LBA Foramt 0 Support: (current) Metadata Size: 0 LBA Data Size: 512 Relative Performance: Good LBA Foramt 1 Support: Metadata Size: 8 LBA Data Size: 512 Relative Performance: Good LBA Foramt 2 Support: Metadata Size: 16 LBA Data Size: 512 Relative Performance: Good LBA Foramt 3 Support: Metadata Size: 0 LBA Data Size: 4096 Relative Performance: Best LBA Foramt 4 Support: Metadata Size: 8 LBA Data Size: 4096 Relative Performance: Best LBA Foramt 5 Support: Metadata Size: 64 LBA Data Size: 4096 Relative Performance: Best Blk device 0: End-to-End DataProtect Capabilities: As last eight bytes: yes As first eight bytes: No Support Type3: No Support Type2: No Support Type1: yes Blk device 0: Metadata capabilities: As part of a separate buffer: No As part of an extended data LBA: yes => nvme part Partition Map for UNKNOWN device 0 -- Partition Type: DOS Part Start Sector Num Sectors UUID Type 1 2048 2048000 ffc18949-01 83 => nvme read 90000000 0 100000 NVME read: device 0 block # 0, count 1048576 ... read: OK 536870912 bytes read in 1086 ms (471.5 MiB/s) => nvme write 90000000 0 100000 NVME write: device 0 block # 0, count 1048576 ... write: OK 536870912 bytes read in 1070 ms (478.5 MiB/s) => fatls nvme 0 32376967 kernel.itb 22929408 100m 2 file(s), 0 dir(s) => fatload nvme 0 90000000 kernel.itb reading kernel.itb 32376967 bytes read in 128 ms (241.2 MiB/s)

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[U-Boot] [PATCH v2] QE: add QE support on SD boot
by Zhao Qiang 21 Apr '17

21 Apr '17

modify u_qe_init to upload QE firmware from SD card when it is SD boot Signed-off-by: Zhao Qiang <qiang.zhao(a)nxp.com> --- Changes for v2: - fix issue of memory leak drivers/qe/qe.c | 37 ++++++++++++++++++++++++++++++++++++- include/configs/ls1043a_common.h | 2 ++ include/configs/ls1043ardb.h | 4 +--- 3 files changed, 39 insertions(+), 4 deletions(-) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 4f0a278..52e4d7c 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <malloc.h> #include <command.h> #include <linux/errno.h> #include <asm/io.h> @@ -17,6 +18,10 @@ #include <asm/arch/immap_ls102xa.h> #endif +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC +#include <mmc.h> +#endif + #define MPC85xx_DEVDISR_QE_DISABLE 0x1 qe_map_t *qe_immr = NULL; @@ -194,8 +199,38 @@ void u_qe_init(void) { qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET); - u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR); +#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR) + void *addr = (void *)CONFIG_SYS_QE_FW_ADDR; +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) + int dev = CONFIG_SYS_MMC_ENV_DEV; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; + u32 blk = CONFIG_SYS_QE_FW_ADDR / 512; + + if (mmc_initialize(gd->bd)) { + printf("%s: mmc_initialize() failed\n", __func__); + return; + } + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + free(addr); + printf("\nMMC cannot find device for ucode\n"); + } else { + printf("\nMMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); + } +#endif + u_qe_upload_firmware(addr); out_be32(&qe_immr->iram.iready, QE_IRAM_READY); +#ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC + free(addr); +#endif } #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e269248..80c508e 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -219,6 +219,7 @@ */ #define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) #elif defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 @@ -230,6 +231,7 @@ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* FMan fireware Pre-load address */ #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 +#define CONFIG_SYS_QE_FW_ADDR 0x60600000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 5e570cd..ffa0dba 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -277,11 +277,9 @@ /* QE */ #ifndef SPL_NO_QE -#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ - !defined(CONFIG_QSPI_BOOT) +#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE #endif -#define CONFIG_SYS_QE_FW_ADDR 0x60600000 #endif /* USB */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] rockchip: rk3399: use actual dram size
by Kever Yang 20 Apr '17

20 Apr '17

Since our sdram driver is ready, we can use the actual size instead of hard code. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - fix compile warning of print type not match arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 8 ++++---- board/rockchip/evb_rk3399/evb-rk3399.c | 19 ++++++++++++++++++- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index 749b52c..536879d 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -1280,6 +1280,8 @@ static int rk3399_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); + priv->info.base = 0; + priv->info.size = sdram_size_mb(priv) << 20; #endif return 0; } @@ -1288,9 +1290,7 @@ static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info) { struct dram_info *priv = dev_get_priv(dev); - info = &priv->info; - priv->info.base = 0; - priv->info.size = sdram_size_mb(priv) << 20; + *info = priv->info; return 0; } @@ -1314,8 +1314,8 @@ U_BOOT_DRIVER(dmc_rk3399) = { .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, #endif .probe = rk3399_dmc_probe, -#ifdef CONFIG_SPL_BUILD .priv_auto_alloc_size = sizeof(struct dram_info), +#ifdef CONFIG_SPL_BUILD .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), #endif }; diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index e3ba020..9b98388 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -5,6 +5,7 @@ */ #include <common.h> #include <dm.h> +#include <ram.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> #include <asm/arch/periph.h> @@ -64,7 +65,23 @@ out: int dram_init(void) { - gd->ram_size = 0x80000000; + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size); + gd->ram_size = ram.size; + return 0; } -- 1.9.1

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[U-Boot] rockchip: enable debug uart
by Eddie Cai 20 Apr '17

20 Apr '17

enable debug uart for rk3288 and print something to let people know where we are Signed-off-by: Eddie Cai <eddie.cai.linux(a)gmail.com> --- arch/arm/mach-rockchip/rk3288-board-spl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 74f3379..8ca6b1e 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -164,7 +164,6 @@ void board_init_f(ulong dummy) int ret; /* Example code showing how to enable the debug UART on RK3288 */ -#ifdef EARLY_UART #include <asm/arch/grf_rk3288.h> /* Enable early UART on the RK3288 */ #define GRF_BASE 0xff770000 @@ -183,8 +182,7 @@ void board_init_f(ulong dummy) * printascii("string"); */ debug_uart_init(); -#endif - + debug("\nspl:debug uart enabled in %s\n", __func__); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); @@ -205,7 +203,7 @@ void board_init_f(ulong dummy) debug("Pinctrl init failed: %d\n", ret); return; } - + debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); -- 2.10.2

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[U-Boot] [PATCH v2] rockchip: dts: evb-rk3399: correct pwm3 polarity
by Kever Yang 20 Apr '17

20 Apr '17

The pwm3 on evb-rk3399 is used for pwm regulator, need to invert the polarity to make it work correctly. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - commit message description fix arch/arm/dts/rk3399-evb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index d2ded77..b01ce1e 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -20,7 +20,7 @@ vdd_center: vdd-center { compatible = "pwm-regulator"; - pwms = <&pwm3 0 25000 0>; + pwms = <&pwm3 0 25000 1>; regulator-name = "vdd_center"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; -- 1.9.1

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[U-Boot] [PATCH v1 0/2] rockchip: dts: rk3399-puma: Update to use DDR3-1600 timings
by Philipp Tomsich 20 Apr '17

20 Apr '17

With our validation having progresses to the point of tuning the DRAM interface, we can now use a DDR3-1600 timing (i.e. 800MHz base clock) as the default for the RK3399-Q7 (Puma). This series - adds a DDR3-1600 timing for the RK3399-Q7 - switches the RK3399-Q7 over to use this new timing - cleans up some graffiti (i.e. unwanted source edits) from the DDR3-1333 timing we had submitted earlier Philipp Tomsich (2): rockchip: dts: Clean up graffiti in rk3399-sdram-ddr3-1333.dtsi rockchip: dts: rk3399-puma: Add DDR3-1600 timings and use for Puma arch/arm/dts/rk3399-puma.dts | 6 +- arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi | 8 +- arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi | 1537 ++++++++++++++++++++++++++++++ 3 files changed, 1546 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi -- 1.9.1

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