April 2017 - U-Boot

Re: [U-Boot] [PATCH] spl: dfu: compilation fixes for spl-dfu
by Lukasz Majewski 20 Apr '17

20 Apr '17

Hi Ravi, Please add u-boot mailing list to CC, when sending patches. > This patch fixes the compilation error > common/cli_hush.c:3349: undefined reference to 'realloc_simple' > > The dfu does not depend on HUSH_PARSER. > The dfu, fastboot uses run_command(), it is > part of cli.c and use cli_simple_run_command(). > > Signed-off-by: Ravi Babu <ravibabu(a)ti.com> > --- > common/Makefile | 1 - > common/cli.c | 2 +- > 2 files changed, 1 insertion(+), 2 deletions(-) > > diff --git a/common/Makefile b/common/Makefile > index bcd2486..dc5cb1d 100644 > --- a/common/Makefile > +++ b/common/Makefile > @@ -90,7 +90,6 @@ endif # !CONFIG_SPL_BUILD > > ifdef CONFIG_SPL_BUILD > obj-$(CONFIG_SPL_DFU_SUPPORT) += dfu.o > -obj-$(CONFIG_SPL_DFU_SUPPORT) += cli_hush.o > obj-$(CONFIG_SPL_HASH_SUPPORT) += hash.o > obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o > obj-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o > diff --git a/common/cli.c b/common/cli.c > index a433ef2..3dd4c2b 100644 > --- a/common/cli.c > +++ b/common/cli.c > @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; > */ > int run_command(const char *cmd, int flag) > { > -#ifndef CONFIG_HUSH_PARSER > +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_HUSH_PARSER) > /* > * cli_run_command can return 0 or 1 for success, so clean up > * its result. So for the initial support of the DFU in SPL you did not needed the HUSH parser. What is the motivation to enable it now? Enabling the HUSH in SPL should make the binary even bigger - hence it is counterintuitive. Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de

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[U-Boot] [PATCH v1 0/4] sf: add ADDR_4B for 4byte address support
by Yuan Yao 20 Apr '17

20 Apr '17

From: Yuan Yao <yao.yuan(a)nxp.com> Some new flash don't support bar but use 4bytes address to direct support exceed 16MB flash size. So add flash flag: ADDR_4B for some flash which support 4bytes address. Yuan Yao (4): sf: add ADDR_4B for 4byte address support spi: fsl_qspi: Add 4bytes address support armv8: ls1012a: update the flash size to 64M. armv8: ls1046a: update the flash size to 64M. drivers/mtd/spi/sf_internal.h | 4 +++- drivers/mtd/spi/sf_params.c | 2 +- drivers/mtd/spi/spi_flash.c | 38 +++++++++++++++++++++++++------------- drivers/spi/fsl_qspi.c | 8 ++++++-- include/configs/ls1012a_common.h | 3 +-- include/configs/ls1046ardb.h | 3 +-- include/spi_flash.h | 1 + 7 files changed, 38 insertions(+), 21 deletions(-) -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] arm64: zynqmp: Sync defconfig with Kconfig
by Michal Simek 20 Apr '17

20 Apr '17

Remove option which depends on MMC controller which is disabled for dc2. Savedefconfig is removing it because of new dependencies. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index aa40be0ed60d..6682b679b351 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -3,7 +3,6 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 -# CONFIG_SPL_MMC_SUPPORT is not set # CONFIG_SPL_LIBDISK_SUPPORT is not set # CONFIG_SPL_FAT_SUPPORT is not set CONFIG_ZYNQMP_USB=y -- 1.9.1

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[U-Boot] [PATCH] zynq-topic-miami.dts: Add usbotg0 alias to make USB actually work
by Mike Looijmans 20 Apr '17

20 Apr '17

Fixes the following problem: zynq-uboot> run dfu_ram Setting bus to 1 g_dnl_register: failed!, error: -19 The cause appears to be that the USB framework is looking for a usbotg aliases, so add the alias to point to our USB device. Signed-off-by: Mike Looijmans <mike.looijmans(a)topic.nl> --- arch/arm/dts/zynq-topic-miami.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/zynq-topic-miami.dts b/arch/arm/dts/zynq-topic-miami.dts index aa05c4d..79a3671 100644 --- a/arch/arm/dts/zynq-topic-miami.dts +++ b/arch/arm/dts/zynq-topic-miami.dts @@ -19,6 +19,7 @@ i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; + usbotg0 = &usb0; }; memory@0 { -- 1.9.1

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[U-Boot] [U-Boot PATCH V2 0/9] introduce Rockchip rockusb
by Eddie Cai 20 Apr '17

20 Apr '17

rockusb is a protocol run between host pc and device. it help people get device info, flash image to device. this patch implement rockusb on device side. Eddie Cai (9): usb: ums: split macro and data struct in storage_common.c usb: ums: split macro and data struct in f_mass_storage.c usb: ums: merge storage_common.c into f_mass_storage.c usb: ums: remove static declaration of some ums functions usb: ums: add functions to set and get usb interface descriptor usb: ums: add do_extra_command cmd: add rockusb command rockchip: config: enable rockusb support on rk3288 based board rockusb: add a simple readme cmd/Kconfig | 5 + cmd/Makefile | 1 + cmd/rockusb.c | 383 +++++++++++++++++++++ configs/evb-rk3288_defconfig | 2 + configs/fennec-rk3288_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/popmetal-rk3288_defconfig | 1 + configs/rock2_defconfig | 2 + configs/sandbox_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + doc/README.rockusb | 35 ++ drivers/usb/gadget/f_mass_storage.c | 356 +++++++++++++------ .../storage_common.c => include/f_mass_storage.h | 296 +++++----------- 14 files changed, 775 insertions(+), 311 deletions(-) create mode 100644 cmd/rockusb.c create mode 100644 doc/README.rockusb rename drivers/usb/gadget/storage_common.c => include/f_mass_storage.h (65%) -- 2.10.2

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[U-Boot] [PATCH v2] rockchip: reserve memory for rk3399 ATF data
by Kever Yang 20 Apr '17

20 Apr '17

There are 3 region used by rk3399 ATF: - bl31 code, locate at 0x10000; - cortex-m0 code and data, locate at 0xff8c0000; - bl31 data, locate at 0xff8c1000 ~ 0xff8c4000; SPL_TEXT_BASE starts from 0xff8c2000, we need to reserve memory for ATF data, or else there will have memory corrupt after SPL load ATF image. More detail about cortex-M0 code in ATF: https://github.com/ARM-software/arm-trusted-firmware/commit/ 8382e17c4c6bffd15119dfce1ee4372e3c1a7890 Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: - use Kconfig for the reserved memory size arch/arm/include/asm/arch-rockchip/boot0.h | 4 ++++ arch/arm/mach-rockchip/Kconfig | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 8d7bc9a..7346876 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -16,3 +16,7 @@ .space 0x4 /* space for the 'RK33' */ #endif b reset + +#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD) + .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index af0796d..979b48e 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -72,6 +72,14 @@ config ROCKCHIP_SPL_BACK_TO_BROM SPL will return to the boot rom, which will then load the U-Boot binary to keep going on. +config ROCKCHIP_SPL_RESERVE_IRAM + hex "Size of IRAM reserved in SPL" + default 0x4000 + help + SPL may need reserve memory for firmware load by SPL, which load + address is in IRAM and may overlay with SPL text area if not + reserved. + config ROCKCHIP_BROM_HELPER bool -- 1.9.1

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[U-Boot] [PATCH] configs: sama5d4_xplained: Fix wrong CONFIG_DEBUG_UART_CLOCK
by Wenyou Yang 20 Apr '17

20 Apr '17

Fix the wrong configured CONFIG_DEBUG_UART_CLOCK, should be 100MHz, instead of 88MHz, align with at91bootstrap to avoid the weird character. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- configs/sama5d4_xplained_mmc_defconfig | 2 +- configs/sama5d4_xplained_nandflash_defconfig | 2 +- configs/sama5d4_xplained_spiflash_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 2b95a16fc9..389cfd32f4 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -56,7 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 -CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index b0466c2973..af22049058 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -53,7 +53,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 -CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 57dec69b38..b51b05182a 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -55,7 +55,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_ATMEL=y CONFIG_DEBUG_UART_BASE=0xfc00c000 -CONFIG_DEBUG_UART_CLOCK=88000000 +CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y -- 2.11.0

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[U-Boot] [PATCH 1/4] mmc: fsl_esdhc: introduce vs18_enable for 1.8V fix I/O
by Peng Fan 20 Apr '17

20 Apr '17

When using eMMC with 1.8V I/O, the VSELECT bit need to be set in the USDHC controller when init. This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg structure and priv data, so each controller can have different settings. We could not use CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT, it has problem that it will apply to all USDHC controllers and it only set the 1.8V at init phase. So if user does not select to the eMMC device, the voltage on the I/O pins are not correct. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Jaehoon Chung <jh80.chung(a)samsung.com> Cc: York Sun <york.sun(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/mmc/fsl_esdhc.c | 9 +++++++++ include/fsl_esdhc.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index f3c6358..bddfe24 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -92,6 +92,7 @@ struct fsl_esdhc { * @dev: pointer for the device * @non_removable: 0: removable; 1: non-removable * @wp_enable: 1: enable checking wp; 0: no check + * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V * @cd_gpio: gpio for card detection * @wp_gpio: gpio for write protection */ @@ -104,6 +105,7 @@ struct fsl_esdhc_priv { struct udevice *dev; int non_removable; int wp_enable; + int vs18_enable; #ifdef CONFIG_DM_GPIO struct gpio_desc cd_gpio; struct gpio_desc wp_gpio; @@ -673,6 +675,9 @@ static int esdhc_init(struct mmc *mmc) esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); #endif + if (priv->vs18_enable) + esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); + return 0; } @@ -733,6 +738,7 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, priv->bus_width = cfg->max_bus_width; priv->sdhc_clk = cfg->sdhc_clk; priv->wp_enable = cfg->wp_enable; + priv->vs18_enable = cfg->vs18_enable; return 0; }; @@ -759,6 +765,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); #endif + if (priv->vs18_enable) + esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); + writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); memset(&priv->cfg, 0, sizeof(priv->cfg)); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index e15d3ae..7a5d653 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -178,6 +178,7 @@ struct fsl_esdhc_cfg { u32 sdhc_clk; u8 max_bus_width; u8 wp_enable; + u8 vs18_enable; /* Use 1.8V if set to 1 */ struct mmc_config cfg; }; -- 2.6.2

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[U-Boot] [PATCH 1/2][v2] board: freescale: ls2080ardb: Update QIXIS code
by Priyanka Jain 20 Apr '17

20 Apr '17

Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS flag is enabled Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- board/freescale/ls2080ardb/ls2080ardb.c | 19 ++++++++++++++++--- 1 files changed, 16 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index ea05ec6..1de5058 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -22,8 +22,10 @@ #include <asm/arch/ppa.h> #include <fsl_sec.h> +#ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" #include "ls2080ardb_qixis.h" +#endif #include "../common/vid.h" #define PIN_MUX_SEL_SDHC 0x00 @@ -57,12 +59,15 @@ unsigned long long get_qixis_addr(void) int checkboard(void) { +#ifdef CONFIG_FSL_QIXIS u8 sw; +#endif char buf[15]; cpu_name(buf); printf("Board: %s-RDB, ", buf); +#ifdef CONFIG_FSL_QIXIS sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); @@ -78,7 +83,7 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - +#endif puts("SERDES1 Reference : "); printf("Clock1 = 156.25MHz "); printf("Clock2 = 156.25MHz"); @@ -92,6 +97,7 @@ int checkboard(void) unsigned long get_board_sys_clk(void) { +#ifdef CONFIG_FSL_QIXIS u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x0F) { @@ -110,6 +116,7 @@ unsigned long get_board_sys_clk(void) case QIXIS_SYSCLK_166: return 166666666; } +#endif return 66666666; } @@ -133,6 +140,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel) int config_board_mux(int ctrl_type) { +#ifdef CONFIG_FSL_QIXIS u8 reg5; reg5 = QIXIS_READ(brdcfg[5]); @@ -150,7 +158,7 @@ int config_board_mux(int ctrl_type) } QIXIS_WRITE(brdcfg[5], reg5); - +#endif return 0; } @@ -180,8 +188,9 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#ifdef CONFIG_FSL_QIXIS QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); - +#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -301,6 +310,7 @@ int ft_board_setup(void *blob, bd_t *bd) void qixis_dump_switch(void) { +#ifdef CONFIG_FSL_QIXIS int i, nr_of_cfgsw; QIXIS_WRITE(cms[0], 0x00); @@ -311,6 +321,7 @@ void qixis_dump_switch(void) QIXIS_WRITE(cms[0], i); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } +#endif } /* @@ -321,6 +332,7 @@ void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr) { +#ifdef CONFIG_FSL_QIXIS u8 sw; sw = QIXIS_READ(arch); @@ -330,4 +342,5 @@ void update_spd_address(unsigned int ctrl_num, else if (ctrl_num == 1 && slot == 1) *addr = SPD_EEPROM_ADDRESS3; } +#endif } -- 1.7.4.1

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[U-Boot] [PATCH 1/3] dm: core: Clarify uclass_first/next_device() comments
by Simon Glass 20 Apr '17

20 Apr '17

These are not as clear as they could be. Tidy them up a bit. Also fix a tiny code-style nit. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- drivers/core/uclass.c | 3 +-- include/dm/uclass.h | 13 +++++++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 04fb45b01a..42613031ff 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -342,8 +342,7 @@ int uclass_get_device_by_driver(enum uclass_id id, return -ENODEV; } -int uclass_get_device_tail(struct udevice *dev, int ret, - struct udevice **devp) +int uclass_get_device_tail(struct udevice *dev, int ret, struct udevice **devp) { if (ret) return ret; diff --git a/include/dm/uclass.h b/include/dm/uclass.h index b583aa869b..63da868ae5 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -224,8 +224,13 @@ int uclass_get_device_by_driver(enum uclass_id id, const struct driver *drv, * * The device returned is probed if necessary, and ready for use * + * This function is useful to start iterating through a list of devices which + * are functioning correctly and can be probed. + * * @id: Uclass ID to look up - * @devp: Returns pointer to the first device in that uclass, or NULL if none + * @devp: Returns pointer to the first device in that uclass if no error + * occurred, or NULL if there is no first device, or an error occurred with + * that device. * @return 0 if OK (found or not found), other -ve on error */ int uclass_first_device(enum uclass_id id, struct udevice **devp); @@ -246,8 +251,12 @@ int uclass_first_device_err(enum uclass_id id, struct udevice **devp); * * The device returned is probed if necessary, and ready for use * + * This function is useful to start iterating through a list of devices which + * are functioning correctly and can be probed. + * * @devp: On entry, pointer to device to lookup. On exit, returns pointer - * to the next device in the same uclass, or NULL if none + * to the next device in the uclass if no error occurred, or NULL if there is + * no next device, or an error occurred with that next device. * @return 0 if OK (found or not found), other -ve on error */ int uclass_next_device(struct udevice **devp); -- 2.12.2.816.g2cccc81164-goog

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