April 2017 - U-Boot

[U-Boot] [PATCH 2/2][v3] nxp/ls2080ardb: Add QSPI-boot support
by Priyanka Jain 21 Apr '17

21 Apr '17

QSPI-boot is verified on LS20080ARDB RevF board with LS2088A SoC. LS2088ARDB RevF Board has limitation that QIXIS can not be access, so QIXIS flag is kept disabled Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta(a)nxp.com> --- Changes for v3:Udated README Changes for v2: Incorporated Sun York's comments Introduced another patch to update qixis related code arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/dts/Makefile | 2 +- arch/arm/dts/fsl-ls2080a-rdb-qspi.dts | 57 +++++++++++++++++++++++++++++ board/freescale/ls2080ardb/README | 26 +++++++++++++ configs/ls2080ardb_qspi_defconfig | 40 ++++++++++++++++++++ include/configs/ls2080a_common.h | 6 +++ include/configs/ls2080aqds.h | 8 +---- include/configs/ls2080ardb.h | 56 ++++++++++++++++++++++++++++- 8 files changed, 187 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/fsl-ls2080a-rdb-qspi.dts create mode 100644 configs/ls2080ardb_qspi_defconfig diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 12fd80e..4b32b2e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -163,6 +163,7 @@ endchoice config SYS_LS_PPA_FW_ADDR hex "Address of PPA firmware loading from" depends on FSL_LS_PPA + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A default 0x60500000 if SYS_LS_PPA_FW_IN_XIP diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0ee4281..59366cf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -171,7 +171,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ - fsl-ls2080a-rdb.dtb + fsl-ls2080a-rdb.dtb fsl-ls2080a-rdb-qspi.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts new file mode 100644 index 0000000..aa9b03d --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-rdb-qspi.dts @@ -0,0 +1,57 @@ +/* + * NXP ls2080a RDB board device tree source for QSPI-boot + * + * Copyright (C) 2017 NXP Semiconductors + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "fsl-ls2080a.dtsi" + +/ { + model = "Freescale Layerscape 2080a RDB Board"; + compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; + + aliases { + spi0 = &qspi; + spi1 = &dspi; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q512a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fs512s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + qflash1: s25fs512s@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 0c9c574..c870adc 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -43,6 +43,7 @@ Memory map from core's view 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM +0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2 @@ -68,6 +69,31 @@ Booting Options --------------- a) NOR boot b) NAND boot +c) QSPI boot + +cfg_rcw_src switches needs to be changed for booting from different option. +Refer to board documentation for correct switch setting. + +QSPI boot details +=================== +Supported only for + LS2080/LS2088ARDB RevF board with LS2088A SoC. + +Images needs to be copied to QSPI flash +as per memory map given below. + +Memory map for QSPI flash +------------------------- +Image Flash Offset +RCW+PBI 0x00000000 +Boot firmware (U-Boot) 0x00100000 +Boot firmware Environment 0x00300000 +PPA firmware 0x00400000 +Cortina PHY firmware 0x00980000 +DPAA2 MC 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01100000 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) ------------------------------------------------------------------- diff --git a/configs/ls2080ardb_qspi_defconfig b/configs/ls2080ardb_qspi_defconfig new file mode 100644 index 0000000..d89c724 --- /dev/null +++ b/configs/ls2080ardb_qspi_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS2080ARDB=y +CONFIG_FSL_LS_PPA=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb-qspi" +# CONFIG_SYS_MALLOC_F is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=10 +CONFIG_CMD_GREPENV=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_DM_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_FSL_DSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 427f623..cdb416a 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -28,6 +28,12 @@ #else #define CONFIG_SYS_TEXT_BASE 0x30100000 #endif +#else +#define CONFIG_SYS_TEXT_BASE 0x20100000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #endif #define CONFIG_SUPPORT_RAW_INITRD diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index beacb99..5e2c164 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -262,13 +262,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_TEXT_BASE 0x20010000 -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else +#ifndef CONFIG_QSPI_BOOT #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) #define CONFIG_ENV_SECT_SIZE 0x20000 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 2155a89..aa50f39 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -12,6 +12,12 @@ #undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 2 +#ifdef CONFIG_FSL_QSPI +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_I2C_EARLY_INIT +#define CONFIG_DISPLAY_BOARDINFO_LATE +#endif + #define I2C_MUX_CH_VOL_MONITOR 0xa #define I2C_VOL_MONITOR_ADDR 0x38 #define CONFIG_VOL_MONITOR_IR36021_READ @@ -116,7 +122,9 @@ unsigned long get_board_sys_clk(void); CONFIG_SYS_FLASH_BASE + 0x40000000} #endif +#ifndef CONFIG_FSL_QSPI #define CONFIG_NAND_FSL_IFC +#endif #define CONFIG_SYS_NAND_MAX_ECCPOS 256 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 @@ -154,11 +162,15 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE +#ifndef CONFIG_FSL_QSPI #define CONFIG_CMD_NAND +#endif #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) +#ifndef CONFIG_FSL_QSPI #define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#endif #define QIXIS_LBMAP_SWITCH 0x06 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -241,11 +253,13 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#ifndef CONFIG_QSPI_BOOT #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x2000 #endif +#endif /* Debug Server firmware */ #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR @@ -263,11 +277,18 @@ unsigned long get_board_sys_clk(void); #define I2C_MUX_CH_DEFAULT 0x8 /* SPI */ -#ifdef CONFIG_FSL_DSPI +#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_BAR +#ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO #endif +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ +#define FSL_QSPI_FLASH_NUM 2 +#endif +#endif /* * RTC configuration @@ -347,6 +368,27 @@ unsigned long get_board_sys_clk(void); " 0x580800000 \0" \ BOOTENV #else +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ + "scriptaddr=0x80800000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x81000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "ramdisk_addr_r=0x89000000\0" \ + "loadaddr=0x80100000\0" \ + "kernel_addr=0x100000\0" \ + "ramdisk_addr=0x800000\0" \ + "ramdisk_size=0x2000000\0" \ + "fdt_high=0xa0000000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_start=0x21100000\0" \ + "mcmemsize=0x40000000\0" \ + "fdtfile=fsl-ls2080a-rdb.dtb\0" \ + "mcinitcmd=fsl_mc start mc 0x20a00000" \ + " 0x20e00000 \0" \ + BOOTENV +#else #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "scriptaddr=0x80800000\0" \ @@ -369,6 +411,7 @@ unsigned long get_board_sys_clk(void); " 0x580800000 \0" \ BOOTENV #endif +#endif #undef CONFIG_BOOTARGS @@ -378,11 +421,18 @@ unsigned long get_board_sys_clk(void); " hugepagesz=2m hugepages=256" #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_QSPI_BOOT +/* Try to boot an on-QSPI kernel first, then do normal distro boot */ +#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \ + " && bootm $kernel_start" \ + " || run distro_bootcmd" +#else /* Try to boot an on-NOR kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \ " && cp.b $kernel_start $kernel_load $kernel_size" \ " && bootm $kernel_load" \ " || run distro_bootcmd" +#endif /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET @@ -391,7 +441,11 @@ unsigned long get_board_sys_clk(void); #define CONFIG_PHY_CORTINA #define CONFIG_PHYLIB #define CONFIG_SYS_CORTINA_FW_IN_NOR +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_CORTINA_FW_ADDR 0x20980000 +#else #define CONFIG_CORTINA_FW_ADDR 0x581000000 +#endif #define CONFIG_CORTINA_FW_LENGTH 0x40000 #define CORTINA_PHY_ADDR1 0x10 -- 1.7.4.1

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[U-Boot] [PATCH 1/2][v3] board: freescale: ls2080ardb: Update QIXIS code
by Priyanka Jain 21 Apr '17

21 Apr '17

Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS flag is enabled Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- board/freescale/ls2080ardb/ls2080ardb.c | 19 ++++++++++++++++--- 1 files changed, 16 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index ea05ec6..1de5058 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -22,8 +22,10 @@ #include <asm/arch/ppa.h> #include <fsl_sec.h> +#ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" #include "ls2080ardb_qixis.h" +#endif #include "../common/vid.h" #define PIN_MUX_SEL_SDHC 0x00 @@ -57,12 +59,15 @@ unsigned long long get_qixis_addr(void) int checkboard(void) { +#ifdef CONFIG_FSL_QIXIS u8 sw; +#endif char buf[15]; cpu_name(buf); printf("Board: %s-RDB, ", buf); +#ifdef CONFIG_FSL_QIXIS sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); @@ -78,7 +83,7 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - +#endif puts("SERDES1 Reference : "); printf("Clock1 = 156.25MHz "); printf("Clock2 = 156.25MHz"); @@ -92,6 +97,7 @@ int checkboard(void) unsigned long get_board_sys_clk(void) { +#ifdef CONFIG_FSL_QIXIS u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x0F) { @@ -110,6 +116,7 @@ unsigned long get_board_sys_clk(void) case QIXIS_SYSCLK_166: return 166666666; } +#endif return 66666666; } @@ -133,6 +140,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel) int config_board_mux(int ctrl_type) { +#ifdef CONFIG_FSL_QIXIS u8 reg5; reg5 = QIXIS_READ(brdcfg[5]); @@ -150,7 +158,7 @@ int config_board_mux(int ctrl_type) } QIXIS_WRITE(brdcfg[5], reg5); - +#endif return 0; } @@ -180,8 +188,9 @@ int board_init(void) #endif select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#ifdef CONFIG_FSL_QIXIS QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); - +#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -301,6 +310,7 @@ int ft_board_setup(void *blob, bd_t *bd) void qixis_dump_switch(void) { +#ifdef CONFIG_FSL_QIXIS int i, nr_of_cfgsw; QIXIS_WRITE(cms[0], 0x00); @@ -311,6 +321,7 @@ void qixis_dump_switch(void) QIXIS_WRITE(cms[0], i); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } +#endif } /* @@ -321,6 +332,7 @@ void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr) { +#ifdef CONFIG_FSL_QIXIS u8 sw; sw = QIXIS_READ(arch); @@ -330,4 +342,5 @@ void update_spd_address(unsigned int ctrl_num, else if (ctrl_num == 1 && slot == 1) *addr = SPD_EEPROM_ADDRESS3; } +#endif } -- 1.7.4.1

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[U-Boot] [PATCH] board: freescale: ls2080ardb: Enable SD interface for RevF board
by Priyanka Jain 21 Apr '17

21 Apr '17

LS2080ARDB/LS2088ARDB RevF board has smart voltage translator which needs to be programmed to enable high speed SD interface by setting GPIO4_10 output to zero Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Santan Kumar <santan.kumar(a)nxp.com> --- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++ board/freescale/ls2080ardb/ls2080ardb.c | 17 +++++++++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 80c421f..9fdd6a0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -45,6 +45,9 @@ #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) +#define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) +#define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 1bd555b..51012e4 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -214,6 +214,23 @@ int board_early_init_f(void) int misc_init_r(void) { +#ifdef CONFIG_FSL_QIXIS + u8 sw; + + sw = QIXIS_READ(arch); + /* + * LS2080ARDB/LS2088ARDB RevF board has smart voltage translator + * which needs to be programmed to enable high speed SD interface + * by setting GPIO4_10 output to zero + */ + if ((sw & 0xf) == 0x5) { + out_le32(GPIO4_GPDIR_ADDR, (1 << 21 | + in_le32(GPIO4_GPDIR_ADDR))); + out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) & + in_le32(GPIO4_GPDAT_ADDR))); + } +#endif + if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); -- 1.7.4.1

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[U-Boot] [PATCH] boards: axs10x, nsim, tb100: Enable cmdline history
by Alexey Brodkin 21 Apr '17

21 Apr '17

Enable shell commands history on ARC boards for more convenience of users. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- include/configs/axs10x.h | 1 + include/configs/nsim.h | 1 + include/configs/tb100.h | 1 + 3 files changed, 3 insertions(+) diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 768e8fbfa423..8ff998ed98aa 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -96,6 +96,7 @@ #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 16 +#define CONFIG_CMDLINE_EDITING /* * Environment settings diff --git a/include/configs/nsim.h b/include/configs/nsim.h index d6d26c74b43b..5bbf6108463e 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -37,6 +37,7 @@ */ #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 16 +#define CONFIG_CMDLINE_EDITING /* * Environment settings diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 115b3b3c5be5..fe8e6c4e3b30 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -60,6 +60,7 @@ #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 16 +#define CONFIG_CMDLINE_EDITING /* * Environment settings -- 2.7.4

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[U-Boot] [PATCH] axs10x: Add support of Ext2/4 FS
by Alexey Brodkin 21 Apr '17

21 Apr '17

Those could be easily used on USB flash drives or on SD/MMC cards. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- configs/axs101_defconfig | 3 +++ configs/axs103_defconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index b9ea1c6dea21..9d7dc7f7c053 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -13,6 +13,9 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index fb8e72ff6c9d..bcd4754eef7c 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -13,6 +13,9 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_OF_EMBED=y -- 2.7.4

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[U-Boot] [PATCH] axs101: Enable data cache
by Alexey Brodkin 21 Apr '17

21 Apr '17

There's no reason to keep data cache disabled in axs101 board any longer, enabling it. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- configs/axs101_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 1af505d9ebc4..b9ea1c6dea21 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -1,5 +1,4 @@ CONFIG_ARC=y -CONFIG_SYS_DCACHE_OFF=y CONFIG_TARGET_AXS101=y CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_SYS_CLK_FREQ=750000000 -- 2.7.4

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[U-Boot] [PATCH] arc: arcv1: Disable master/slave check
by Alexey Brodkin 21 Apr '17

21 Apr '17

ARCompact cores are not supposed to be used in SMP designs (this doesn't stop people from creation of heterogeneous chips, for an example keep reading) so there's no point in checking ARCNUM and halting somebody if we build for ARC700. Moreover on AXS101 board we have ARC770 in the ASIC together with other ARC cores and ARC770 happens to be the last node in JTAG chain with ARCNUM = 4. And existing check halts the one and only core we want keep running. Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> --- arch/arc/lib/start.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index b2ba7683097f..95d64f9d4375 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -10,6 +10,9 @@ #include <asm/arcregs.h> ENTRY(_start) +; ARCompact devices are not supposed to be SMP so master/slave check +; makes no sense. +#ifdef CONFIG_ISA_ARCV2 ; Non-masters will be halted immediately, they might be kicked later ; by platform code right before passing control to the Linux kernel ; in bootm.c:boot_jump_linux(). @@ -25,6 +28,7 @@ ENTRY(_start) nop .Lmaster_proceed: +#endif /* Setup interrupt vector base that matches "__text_start" */ sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] -- 2.7.4

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[U-Boot] [PATCH 0/2] drivers: omap_hsmmc: move to DM_MMC_OPS
by Jean-Jacques Hiblot 21 Apr '17

21 Apr '17

This series adapts the omap_hsmmc driver to DM_MMC_OPS. To reduce the number of #idef/#else/#endif, I voluntarily did not use CONFIG_DM_MMC_OPS in the driver. It's supposed to go away at one point anyway. The consequence is that DM_MMC_OPS must be selected if DM_MMC is selected. This is handled in the Kconfig. The first patch disables DM_MMC_OPS when DM_MMC is manually disabled in the plaform configuration header file (am335x_evm.h for example). This is done on some platforms when building the SPL. Those #undef could probably haven been removed but it requires some testing that I haven't done yet. The second patch implements the real DM_MMC_OPS support. This has been tested on DRA7 boards. buildman has been run for dra7 am43 am33 am57. Jean-Jacques Hiblot (2): include: config: am335x: disable DM_MMC_OPS if DM_MMC is disabled drivers: omap_hsmmc: move to DM_MMC_OPS drivers/mmc/Kconfig | 1 + drivers/mmc/omap_hsmmc.c | 39 ++++++++++++++++++++++++++++++++------- include/configs/am335x_evm.h | 1 + include/configs/am335x_shc.h | 1 + include/configs/chiliboard.h | 1 + 5 files changed, 36 insertions(+), 7 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 0/8] Stop AXP from crashing when enabeling LDO3
by Olliver Schinagl 21 Apr '17

21 Apr '17

Hi list, When powering up an AXP209, the default value for LDO3 output is enabled. This works fine. However if for whatever reason, LDO3 is disabled, for example by OS during reboot and u-boot enables LDO3 again, the PMIC shutsdown (without setting an interrupt) causing the board to hang. This behavior has been seen from Linux as well, u-boot disables LDO3 as a default value, the kernel enables it per its DTS, the kernel hangs as the PMIC gets shut down. The root cause is that some boards have to high capacitance on the LDO3 output port causing inrush currents exceeding the maximum of the AXP209. The fix is to turn on the LDO3 at the lowest possible voltage and then set the final voltage. If the capacitance is really big (due to a connected device for example) the AXP209 also features VRC, or Voltage Rate Control, which allows the voltage ramp up to be even slower. This patch series implements the above with a few tiny, cleanups I ran into underway. The initial discussion with some scope screenshots can be found in the linux-sunxi mailing list [0]. Signed-off-by: Olliver Schinagl <oliver(a)schinagl.nl> [0] https://groups.google.com/forum/m/#!topic/linux-sunxi/EDvEsbHHqQI Olliver Schinagl (8): sunxi: board: Print error after power initialization fails sunxi: pmic_bus: Decrease boot time by not writing duplicate data power: axp209: Use BIT() macro power: axp209: Define the chip version mask power: axp209: Reduce magic values by adding defines for LDO[234] power: axp209: Add support for voltage rate control on LDO3 power: axp209: Limit inrush current for broken boards arm: sunxi: Enable inrush quirk on Olimex OLinuXino-A20-Lime2 arch/arm/mach-sunxi/pmic_bus.c | 6 ++++ board/sunxi/board.c | 14 ++++---- configs/A20-OLinuXino-Lime2_defconfig | 1 + drivers/power/Kconfig | 42 ++++++++++++++++++++++ drivers/power/axp209.c | 61 ++++++++++++++++++++++++++------ include/axp209.h | 66 ++++++++++++++++++++++++++--------- 6 files changed, 158 insertions(+), 32 deletions(-) -- 2.11.0

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[U-Boot] [PATCH 0/2] sunxi: power: Add AXP806 and AXP808 support
by Rask Ingemann Lambertsen 21 Apr '17

21 Apr '17

The X-Powers AXP806 and AXP808 PMICs are usually found on boards featuring the Allwinner A80 ARM SoC. The so far supported features are the same on the two chips. A lack of data sheets to compare makes it impossible to know for sure what the differences are, but at least two of the power-up voltages (bldo2 and dcdce) differ. Patch 1 adds support for the regulators and also sets up the master/slave mode addressing to match the way it is wired on the board. This is necessary for the PMIC to respond to register accesses and hopefully solves the AXP806 problems for the Linux 4.9 and 4.10 kernels on Cubieboard4 and A80 Optimus boards, where the AXP806 is wired for slave mode addressing. Patch 2 goes on top of "ARM: sunxi: Add defconfig for Sunchip CX-A99". It updates the defconfig for the Sunchip CX-A99 board. Now that the CPU core voltage can be controlled, the board is configured for 1200 MHz at 1020 mV, which is the maximum according to the vendor's sys_config.fex file, instead of the previous 1008 MHz at 900 mV. Rask Ingemann Lambertsen (2): sunxi: power: Add AXP806 and AXP808 support sunxi: defconfig: Sunchip CX-A99: Raise CPU voltage and clock frequency arch/arm/include/asm/arch-sunxi/pmic_bus.h | 4 + arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/pmic_bus.c | 107 ++++++++++--- board/sunxi/board.c | 20 +++ configs/Sunchip_CX-A99_defconfig | 2 + drivers/power/Kconfig | 226 +++++++++++++++++++++++++++- drivers/power/Makefile | 1 + drivers/power/axp806.c | 231 +++++++++++++++++++++++++++++ include/axp806.h | 50 +++++++ include/axp_pmic.h | 13 ++ 10 files changed, 625 insertions(+), 30 deletions(-) create mode 100644 drivers/power/axp806.c create mode 100644 include/axp806.h -- 2.10.2

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