December 2017 - U-Boot

[U-Boot] [GIT PULL] Xilinx fixes for v2018.01-rc2 v2
by Michal Simek 19 Dec '17

19 Dec '17

Hi Tom, +Stephen This is second pull request. I have removed that AES command enabling which was causing compilation warning on arm64. Thanks, Michal The following changes since commit 659208da4703de50826a469cbb38bf6afb938978: README: update the kernel coding style reference (2017-12-12 21:34:10 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.01-rc2-v2 for you to fetch changes up to 3e229a83bd4190f99731992d3a56983f29313899: test/py: Setup variables based on HUSH selection (2017-12-18 09:32:07 +0100) ---------------------------------------------------------------- Xilinx changes for v2018.01-rc2-v2 fpga: - Enable loading bitstream via fit image for !xilinx platforms zynq: - Fix SPL SD boot mode zynqmp: - Not not reset in panic - Do not use simple allocator because of fat changes - Various dt chagnes - modeboot variable setup - Fix fpga loading on automotive devices - Fix coverity issues test: - Fix env test for !hush case - Stephen's patch ---------------------------------------------------------------- Goldschmidt Simon (1): fpga: allow programming fpga from FIT image for all FPGA drivers Javier Martinez Canillas (1): arm64: zynqmp: Add generic compatible string for I2C EEPROM Michal Simek (18): arm: zynq: Fix SPL SD boot mode arm64: zynqmp: Do not perform reset in case of panic arm64: zynqmp: Do not use SPL_SYS_MALLOC_SIMPLE allocator arm64: zynqmp: Add reference to pmu firmware node arm64: zynqmp: Add support for generic QSPI boot arm64: zynqmp: Enable SPL_CLK when SPL is enabled arm64: zynqmp: Setup modeboot variable based on bootmode arm64: zynqmp: Enable phys for zcu102 arm64: zynqmp: Enable clock command for all boards arm64: zynqmp: Remove undocumented dma properties arm64: zynqmp: Use only earlycon bootargs instead of full one arm64: zynqmp: Add missing zynq_board_read_rom_ethaddr() prototype arm64: zynqmp: Add support for zynqmp automotive silicons arm64: zynqmp: Enable misc devices arm64: zynqmp: Enable SPL ram support arm64: zynqmp: Enable fpga bitstream loading arm64: zynqmp: Enable spi flashes tools: zynqmpimage: Check return values from file functions Siva Durga Prasad Paladugu (3): arm64: zynqmp: Read boot mode register using zynqmp_mmio_read arm64: zynqmp: Dont use 4K sector erase by default for spi-flashes arm64: zynqmp: Access timestamp_ref_ctrl register only if running in el3 Stephen Warren (1): test/py: Setup variables based on HUSH selection arch/arm/Kconfig | 2 +- arch/arm/dts/zynqmp-ep108.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 11 +---------- arch/arm/dts/zynqmp-zcu102-revA.dts | 20 +++++++++++--------- arch/arm/dts/zynqmp.dtsi | 3 ++- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 1 + board/xilinx/zynqmp/zynqmp.c | 23 +++++++++++++++++++---- common/bootm.c | 2 +- common/image.c | 6 ++---- configs/syzygy_hub_defconfig | 2 ++ configs/topic_miami_defconfig | 2 ++ configs/topic_miamilite_defconfig | 2 ++ configs/topic_miamiplus_defconfig | 2 ++ configs/xilinx_zynqmp_ep_defconfig | 7 ++++++- configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 9 ++++++++- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 7 ++++++- configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 14 +++++++++++++- configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 7 ++++++- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 9 ++++++++- configs/xilinx_zynqmp_zcu102_revA_defconfig | 9 ++++++++- configs/xilinx_zynqmp_zcu102_revB_defconfig | 9 ++++++++- configs/zynq_cc108_defconfig | 2 ++ configs/zynq_cse_qspi_defconfig | 2 ++ configs/zynq_microzed_defconfig | 2 ++ configs/zynq_picozed_defconfig | 2 ++ configs/zynq_z_turn_defconfig | 2 ++ configs/zynq_zc702_defconfig | 2 ++ configs/zynq_zc706_defconfig | 2 ++ configs/zynq_zc770_xm010_defconfig | 2 ++ configs/zynq_zc770_xm011_defconfig | 2 ++ configs/zynq_zc770_xm012_defconfig | 2 ++ configs/zynq_zc770_xm013_defconfig | 2 ++ configs/zynq_zed_defconfig | 2 ++ configs/zynq_zybo_defconfig | 2 ++ drivers/fpga/fpga.c | 9 +++++++++ drivers/fpga/xilinx.c | 13 +++++++++++++ include/configs/xilinx_zynqmp.h | 16 +++++++++++++--- include/configs/zynq-common.h | 7 ++----- include/fpga.h | 1 + test/py/tests/test_env.py | 11 ++++++++++- tools/zynqmpimage.c | 32 +++++++++++++++++++++++++++----- 44 files changed, 212 insertions(+), 81 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs

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[U-Boot] [PATCH] common: image.c: Fix CACHE: Misaligned operation output
by Heiko Schocher 19 Dec '17

19 Dec '17

When booting a itb file with a Ramdisk on a imx6 based board, U-Boot drops the warning: Loading Kernel Image ... OK Loading Ramdisk to 4ecf1000, end 4ef8b11f ... \ CACHE: Misaligned operation at range [4ecf1000, 4ef8b11f] Fix it! Signed-off-by: Heiko Schocher <hs(a)denx.de> Tested-by: Ayoub Zaki <hs(a)denx.de> --- Tested on travis: https://travis-ci.org/hsdenx/u-boot-i2c/builds/316257686 common/image.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/common/image.c b/common/image.c index 4bcf6b3128..d52d95a7a5 100644 --- a/common/image.c +++ b/common/image.c @@ -1186,7 +1186,8 @@ int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len, * AMP boot scenarios in which we might not be * HW cache coherent */ - flush_cache((unsigned long)*initrd_start, rd_len); + flush_cache((unsigned long)*initrd_start, + ALIGN(rd_len, ARCH_DMA_MINALIGN)); #endif puts("OK\n"); } -- 2.13.6

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[U-Boot] [PATCH] am335x_evm: Fix DFU for eMMC
by Sam Protsenko 19 Dec '17

19 Dec '17

Use dfu_alt_info_emmc variable from include/environment/ti/dfu.h file. It was probably overlooked when extracting DFU variables to mentioned file. This patch fixes DFU on BeagleBone Black, so that we can use commands like ones below to upgrade various images on eMMC: => setenv dfu_alt_info $dfu_alt_info_emmc => dfu 0 mmc 1 $ dfu-util -D MLO -a MLO.raw $ dfu-util -D u-boot.img -a u-boot.img.raw Without this patch, the user is forced to assign the value to dfu_alt_info_emmc manually, which contradicts with instructions [1]. [1] http://processors.wiki.ti.com/index.php/Linux_Core_U-Boot_User%27s_Guide Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- include/configs/am335x_evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 5ad0366730..856c546fc1 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -255,7 +255,7 @@ /* USB Device Firmware Update support */ #ifndef CONFIG_SPL_BUILD #define DFUARGS \ - "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \ + DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_NAND -- 2.15.0

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[U-Boot] [PATCH u-boot] net: phy: meson-gxl: detect LPA corruption
by Neil Armstrong 19 Dec '17

19 Dec '17

From: Jerome Brunet <jbrunet(a)baylibre.com> This patch is ported from the Linux patch posted at [1] and applied to net tree as commit f1e2400a80ff. The purpose of this change is to fix the incorrect detection of the link partner (LP) advertised capabilities which sometimes happens with this PHY (roughly 1 time in a dozen) This issue may cause the link to be negotiated at 10Mbps/Full or 10Mbps/Half when 100MBps/Full is actually possible. In some case, the link is even completely broken and no communication is possible. To detect the corruption, we must look for a magic undocumented bit in the WOL bank (hint given by the SoC vendor kernel) but this is not enough to cover all cases. We also have to look at the LPA ack. If the LP supports Aneg but did not ack our base code when aneg is completed, we assume something went wrong. The detection of a corrupted LPA triggers a restart of the aneg process. This solves the problem but may take up to 6 retries to complete. [1] https://lkml.kernel.org/r/20171208110811.30789-1-jbrunet@baylibre.com Fixes: 8995a96d1d67 ("net: phy: Add Amlogic Meson GXL Internal PHY support") Signed-off-by: Jerome Brunet <jbrunet(a)baylibre.com> Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- This patch has been tested on LibreTech-CC and adapted to U-Boot PHY calls. Comments from Jerome from the original patch : "" I suppose this patch probably seems a bit hacky, especially the part about the link partner acknowledge. I'm trying to figure out if the value in MII_LPA makes sense but I don't have such a deep knowledge of the ethernet spec. To me, it does not makes sense for the LP to support ANEG (Bit 1 in MII_EXPENSION), the aneg to have successfully complete and, at the same time, LP does not ACK our base code word, which we should have sent during this aneg. If you think this may have unintended consequences or if you have an idea to do this differently, feel free to let me know. This fix has been tested on the libretech-cc and khadas VIM "" drivers/net/phy/meson-gxl.c | 88 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c index ccf70c9..5f4ecb1 100644 --- a/drivers/net/phy/meson-gxl.c +++ b/drivers/net/phy/meson-gxl.c @@ -10,8 +10,94 @@ #include <config.h> #include <common.h> #include <linux/bitops.h> +#include <dm.h> #include <phy.h> +/* This function is provided to cope with the possible failures of this phy + * during aneg process. When aneg fails, the PHY reports that aneg is done + * but the value found in MII_LPA is wrong: + * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that + * the link partner (LP) supports aneg but the LP never acked our base + * code word, it is likely that we never sent it to begin with. + * - Late failures: MII_LPA is filled with a value which seems to make sense + * but it actually is not what the LP is advertising. It seems that we + * can detect this using a magic bit in the WOL bank (reg 12 - bit 12). + * If this particular bit is not set when aneg is reported being done, + * it means MII_LPA is likely to be wrong. + * + * In both case, forcing a restart of the aneg process solve the problem. + * When this failure happens, the first retry is usually successful but, + * in some cases, it may take up to 6 retries to get a decent result + */ +int meson_gxl_startup(struct phy_device *phydev) +{ + unsigned int retries = 10; + int ret, wol, lpa, exp; + +restart_aneg: + ret = genphy_update_link(phydev); + if (ret) + return ret; + + if (phydev->autoneg == AUTONEG_ENABLE) { + /* Need to access WOL bank, make sure the access is open */ + ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + if (ret) + return ret; + ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + if (ret) + return ret; + ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); + if (ret) + return ret; + ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); + if (ret) + return ret; + + /* Request LPI_STATUS WOL register */ + ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80); + if (ret) + return ret; + + /* Read LPI_STATUS value */ + wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); + if (wol < 0) + return wol; + + lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); + if (lpa < 0) + return lpa; + + exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION); + if (exp < 0) + return exp; + + if (!(wol & BIT(12)) || + ((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) { + + /* Looks like aneg failed after all */ + if (!retries) { + printf("%s LPA corruption max attempts\n", + phydev->dev->name); + return -ETIMEDOUT; + } + + printf("%s LPA corruption - aneg restart\n", + phydev->dev->name); + + ret = genphy_restart_aneg(phydev); + if (ret) + return ret; + + --retries; + + goto restart_aneg; + } + } + + return genphy_parse_link(phydev); +} + static int meson_gxl_phy_config(struct phy_device *phydev) { /* Enable Analog and DSP register Bank access by */ @@ -45,7 +131,7 @@ static struct phy_driver meson_gxl_phy_driver = { .mask = 0xfffffff0, .features = PHY_BASIC_FEATURES, .config = &meson_gxl_phy_config, - .startup = &genphy_startup, + .startup = &meson_gxl_startup, .shutdown = &genphy_shutdown, }; -- 2.7.4

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[U-Boot] [PATCH u-boot] ARM: arch-meson: fix writel arguments order
by Neil Armstrong 19 Dec '17

19 Dec '17

From: Hans Verkuil <hans.verkuil(a)cisco.com> Using writel causes a "Synchronous Abort". Invert the arguments. Signed-off-by: Hans Verkuil <hans.verkuil(a)cisco.com> Signed-off-by: Neil Armstrong <narmstrong(a)baylibre.com> --- arch/arm/mach-meson/eth.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Thanks Hans for finding this stupid error ! Neil diff --git a/arch/arm/mach-meson/eth.c b/arch/arm/mach-meson/eth.c index 2debe93..8c6577b 100644 --- a/arch/arm/mach-meson/eth.c +++ b/arch/arm/mach-meson/eth.c @@ -38,8 +38,8 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags) /* Use GXL RMII Internal PHY */ if (IS_ENABLED(CONFIG_MESON_GXL) && (flags & MESON_GXL_USE_INTERNAL_RMII_PHY)) { - writel(GXBB_ETH_REG_2, 0x10110181); - writel(GXBB_ETH_REG_3, 0xe40908ff); + writel(0x10110181, GXBB_ETH_REG_2); + writel(0xe40908ff, GXBB_ETH_REG_3); } break; -- 2.7.4

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[U-Boot] [PULL] efi patch queue 2017-12-17
by Alexander Graf 19 Dec '17

19 Dec '17

Hi Tom, This is my current patch queue for efi. Please pull. Alex The following changes since commit 15616a0aa58173bce1efe47569bf2e10d023ae9c: Merge git://git.denx.de/u-boot-dm (2017-12-14 15:46:07 -0500) are available in the git repository at: git://github.com/agraf/u-boot.git tags/signed-efi-v2018.01 for you to fetch changes up to bde6bfe4c3234480a0eef3b5bda8cf5fc83d3c79: efi_loader: comments for dp_part_fill() (2017-12-16 23:07:56 +0100) ---------------------------------------------------------------- Patch queue for efi - 2017-12-17 A few fixes for 2018.01: - Compile fix with helloworld example - DP match fix (fixes FreeBSD loader and grub on block storage) - More DP fixes for SD, block - Fix use-after-free ---------------------------------------------------------------- Alexander Graf (3): efi_loader: helloworld.c: Explicitly use .rodata for loaded_image_guid efi_loader: helloworld.c: Reduce file size efi_loader: Ensure efi_dp_find_obj() finds exact matches Heinrich Schuchardt (7): efi_loader: return status from efi_setup_loaded_image() efi_loader: new function efi_delete_handle() efi_loader: error handling in efi_load_image() efi_loader: correctly determine if an MMC device is an SD-card efi_loader: correctly setup device paths for block devices efi_loader: correct DeviceNodeToText for media types efi_loader: comments for dp_part_fill() arch/arm/lib/elf_arm_efi.lds | 11 +- include/efi_loader.h | 10 +- lib/efi_loader/efi_boottime.c | 228 +++++++++++++++++-------------- lib/efi_loader/efi_device_path.c | 56 ++++++-- lib/efi_loader/efi_device_path_to_text.c | 43 ++++-- lib/efi_loader/helloworld.c | 3 +- 6 files changed, 214 insertions(+), 137 deletions(-)

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[U-Boot] [PATCH] dm: mmc: sandbox: Update SD card emulation
by Jean-Jacques Hiblot 19 Dec '17

19 Dec '17

The SDcard initialization procedure does a few more things than it did earlier: * switch the bus width even for 1-bit bus width * check that speed has been properly set (in resp[4] of SD_CMD_SWITCH_FUNC) Update the SD simulator to handle those requests gracefully. Signed-off-by: Jean-Jacques Hiblot <jjhiblot(a)ti.com> --- This patch makes 'make tests' work again with the HS200/UHS support. The new SD initialization procedures checks the content of resp[4] because it indicates the speed of the card. This patch also fixes a crash occurring during bus width selection (NULL pointer). Jean-Jacques drivers/mmc/sandbox_mmc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c index fdb29a5..8a5d256 100644 --- a/drivers/mmc/sandbox_mmc.c +++ b/drivers/mmc/sandbox_mmc.c @@ -48,9 +48,12 @@ static int sandbox_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, cmd->response[1] = 10 << 16; /* 1 << block_len */ break; case SD_CMD_SWITCH_FUNC: { + if (!data) + break; u32 *resp = (u32 *)data->dest; - resp[7] = cpu_to_be32(SD_HIGHSPEED_BUSY); + if ((cmd->cmdarg & 0xF) == UHS_SDR12_BUS_SPEED) + resp[4] = (cmd->cmdarg & 0xF) << 24; break; } case MMC_CMD_READ_SINGLE_BLOCK: -- 1.9.1

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[U-Boot] [PATCH v3 1/3] rockchip: add a common script for generate fit its
by Kever Yang 19 Dec '17

19 Dec '17

Rockchip release bl31.elf file for armv8 SoCs like rk3399, rk3328, the elf have more than one section, we need to decode it first and packed them into u-boot.itb with its file. This script is to generate the its script. Need default bl31.elf in root directory of U-Boot source and dtb as parameter. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v3: - use python script - adapt for latest spl atf support Changes in v2: None arch/arm/mach-rockchip/make_fit_atf.py | 221 +++++++++++++++++++++++++++++++++ 1 file changed, 221 insertions(+) create mode 100755 arch/arm/mach-rockchip/make_fit_atf.py diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py new file mode 100755 index 0000000..7c6dd57 --- /dev/null +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -0,0 +1,221 @@ +#!/usr/bin/env python2 +""" +A script to generate FIT image source for rockchip boards +with ARM Trusted Firmware +and multiple device trees (given on the command line) + +usage: $0 <dt_name> [<dt_name> [<dt_name] ...] +""" + +import os +import sys +import getopt + +# pip install pyelftools +from elftools.elf.elffile import ELFFile +from elftools.elf.sections import SymbolTableSection +from elftools.elf.segments import Segment, InterpSegment, NoteSegment + +ELF_SEG_P_TYPE='p_type' +ELF_SEG_P_PADDR='p_paddr' +ELF_SEG_P_VADDR='p_vaddr' +ELF_SEG_P_OFFSET='p_offset' +ELF_SEG_P_FILESZ='p_filesz' +ELF_SEG_P_MEMSZ='p_memsz' + +DT_HEADER="""/* + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * Minimal dts for a SPL FIT image payload. + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ +/dts-v1/; + +/ { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + + images { + uboot@1 { + description = "U-Boot (64-bit)"; + data = /incbin/("u-boot-nodtb.bin"); + type = "standalone"; + os = "U-Boot"; + arch = "arm64"; + compression = "none"; + load = <0x%08x>; + }; +""" + +DT_IMAGES_NODE_END=""" + }; +""" + +DT_END=""" +}; +""" + +def append_atf_node(file, atf_index, phy_addr): + """ + Append ATF DT node to input FIT dts file. + """ + data = 'bl31_0x%08x.bin' % phy_addr + print >> file, '\t\tatf@%d {' % atf_index + print >> file, '\t\t\tdescription = \"ARM Trusted Firmware\";' + print >> file, '\t\t\tdata = /incbin/("%s");' % data + print >> file, '\t\t\ttype = "firmware";' + print >> file, '\t\t\tarch = "arm64";' + print >> file, '\t\t\tos = "arm-trusted-firmware";' + print >> file, '\t\t\tcompression = "none";' + print >> file, '\t\t\tload = <0x%08x>;' % phy_addr + if atf_index == 1: + print >> file, '\t\t\tentry = <0x%08x>;' % phy_addr + print >> file, '\t\t};' + print >> file, '' + +def append_fdt_node(file, dtbs): + """ + Append FDT nodes. + """ + cnt = 1 + for dtb in dtbs: + dtname = os.path.basename(dtb) + print >> file, '\t\tfdt@%d {' % cnt + print >> file, '\t\t\tdescription = "%s";' % dtname + print >> file, '\t\t\tdata = /incbin/("%s");' % dtb + print >> file, '\t\t\ttype = "flat_dt";' + print >> file, '\t\t\tcompression = "none";' + print >> file, '\t\t};' + print >> file, '' + cnt = cnt + 1 + +def append_conf_section(file, cnt, dtname, atf_cnt): + print >> file, '\t\tconfig@%d {' % cnt + print >> file, '\t\t\tdescription = "%s";' % dtname + print >> file, '\t\t\tfirmware = "atf@1";' + print >> file, '\t\t\tloadables = "uboot@1",', + for i in range(1, atf_cnt): + print >> file, '"atf@%d"' % (i+1), + if i != (atf_cnt - 1): + print >> file, ',', + else: + print >> file, ';' + print >> file, '\t\t\tfdt = "fdt@1";' + print >> file, '\t\t};' + print >> file, '' + +def append_conf_node(file, dtbs, atf_cnt): + """ + Append configeration nodes. + """ + cnt = 1 + print >> file, '\tconfigurations {' + print >> file, '\t\tdefault = "config@1";' + for dtb in dtbs: + dtname = os.path.basename(dtb) + append_conf_section(file, cnt, dtname, atf_cnt) + cnt = cnt + 1 + print >> file, '\t};' + print >> file, '' + +def generate_atf_fit_dts(fit_file_name, bl31_file_name, uboot_file_name, dtbs_file_name): + """ + Generate FIT script for ATF image. + """ + if fit_file_name != sys.stdout: + fit_file = open(fit_file_name, "wb") + else: + fit_file = sys.stdout + + num_load_seg = 0 + p_paddr = 0xFFFFFFFF + with open(uboot_file_name) as uboot_file: + uboot = ELFFile(uboot_file) + for i in range(uboot.num_segments()): + seg = uboot.get_segment(i) + if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): + p_paddr = seg.__getitem__(ELF_SEG_P_PADDR) + num_load_seg = num_load_seg + 1 + + assert (p_paddr != 0xFFFFFFFF and num_load_seg == 1) + + print >> fit_file, DT_HEADER % p_paddr + + with open(bl31_file_name) as bl31_file: + bl31 = ELFFile(bl31_file) + for i in range(bl31.num_segments()): + seg = bl31.get_segment(i) + if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): + paddr = seg.__getitem__(ELF_SEG_P_PADDR) + p= seg.__getitem__(ELF_SEG_P_PADDR) + append_atf_node(fit_file, i+1, paddr) + atf_cnt = i+1 + append_fdt_node(fit_file, dtbs_file_name) + print >> fit_file, '%s' % DT_IMAGES_NODE_END + append_conf_node(fit_file, dtbs_file_name, atf_cnt) + print >> fit_file, '%s' % DT_END + + if fit_file_name != sys.stdout: + fit_file.close() + +def generate_atf_binary(bl31_file_name): + with open(bl31_file_name) as bl31_file: + bl31 = ELFFile(bl31_file) + + num = bl31.num_segments() + for i in range(num): + seg = bl31.get_segment(i) + if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): + paddr = seg.__getitem__(ELF_SEG_P_PADDR) + file_name = 'bl31_0x%08x.bin' % paddr + with open(file_name, "wb") as atf: + atf.write(seg.data()); + +def get_bl31_segments_info(bl31_file_name): + """ + Get load offset, physical offset, file size + from bl31 elf file program headers. + """ + with open(bl31_file_name) as bl31_file: + bl31 = ELFFile(bl31_file) + + num = bl31.num_segments() + print 'Number of Segments : %d' % bl31.num_segments() + for i in range(num): + print 'Segment %d' % i + seg = bl31.get_segment(i) + ptype = seg[ELF_SEG_P_TYPE] + poffset = seg[ELF_SEG_P_OFFSET] + pmemsz = seg[ELF_SEG_P_MEMSZ] + pfilesz = seg[ELF_SEG_P_FILESZ] + print 'type: %s\nfilesz: %08x\nmemsz: %08x\noffset: %08x' % (ptype, pfilesz, pmemsz, poffset) + paddr = seg[ELF_SEG_P_PADDR] + print 'paddr: %08x' % paddr + +def main(): + uboot_elf="./u-boot" + bl31_elf="./bl31.elf" + FIT_ITS=sys.stdout + + opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h") + for opt, val in opts: + if opt == "-o": + FIT_ITS=val + elif opt == "-u": + uboot_elf=val + elif opt == "-b": + bl31_elf=val + elif opt == "-h": + print __doc__ + sys.exit(2) + + dtbs = args + #get_bl31_segments_info("u-boot") + #get_bl31_segments_info("bl31.elf") + + generate_atf_fit_dts(FIT_ITS, bl31_elf, uboot_elf, dtbs) + generate_atf_binary(bl31_elf); + +if __name__ == "__main__": + main() -- 1.9.1

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[U-Boot] Anyone using recentish u-boot on a GuruPlug?
by Martin Husemann 18 Dec '17

18 Dec '17

I naively compiled a 2017.11 u-boot for GuruPlug and wrote the u-boot.kwb to nand, but that bricked the GuruPlug (should have tested with a ram version first, yes, I know). I have a jtag for it and was able to recover, but I wonder if i did something wrong in my local build or if support just bitrotted silently. I am not familiar with .kwb and early kirkwood bootstrap, so not sure how I could debug this, besides the jtag is "slightly fragile" and using it a bit inconvenient. Anyone used recentish u-boot on Sheeva/Guruplug lately? Martin

2 2

[U-Boot] SPI Slave mode Device Tree
by Amartya Shreyank (RBEI/ESD2) 18 Dec '17

18 Dec '17

Hi, While going over device tree binding documentation I came across this: /doc/device-tree-bindins/spi/spi-bus.txt: "This binding does not describe SPI controllers in slave mode." Does this mean I cannot use device tree in case I want to configure the controller as SPI slave? If yes, please suggest how can I configure it as a SPI slave. I'm using a imx6solo based custom board. Best regards, Shreyank Amartya RBEI/ESD2

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