December 2017 - U-Boot

[U-Boot] [PATCH v2] rockchip: update boot0 hook
by Kever Yang 18 Dec '17

18 Dec '17

Rockchip SoCs only need boot0 hook at SPL, and the U-Boot proper do not need it. The very beginning of U-Boot proper is different between armv7 and armv8: armv7 start with ARM_VECTORS while armv8 start with 'b reset'. Here is the map of very beginning for all cases: armv7 SPL: TAG(overwrite 'b 1f')+'b reset' + ARM_VECTORS armv7 U-Boot: ARM_VECTORS armv8 SPL: TAG(overwrite 'b 1f')+'b reset' + Reserved_iram(rk3399) armv8 U-Boot: 'b reset' Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: - update commit message arch/arm/include/asm/arch-rockchip/boot0.h | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index af3a733..65b4213 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -26,7 +26,6 @@ */ b 1f /* if overwritten, entry-address is at the next word */ 1: -#endif #if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM) adr r3, entry_counter ldr r0, [r3] @@ -40,6 +39,15 @@ entry_counter: .word 0 #endif b reset + +#if defined(CONFIG_ROCKCHIP_RK3399) + .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ +#endif + +#elif defined(CONFIG_ARM64) /* U-Boot for arm64 */ + b reset +#endif + #if !defined(CONFIG_ARM64) /* * For armv7, the addr '_start' will used as vector start address @@ -49,7 +57,3 @@ entry_counter: _start: ARM_VECTORS #endif - -#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD) - .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ -#endif -- 1.9.1

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[U-Boot] [PATCH] rockchip: rk3399-puma: set gpio4cd iodomain to 1.8V
by Jakob Unterwurzacher 18 Dec '17

18 Dec '17

The PCIe reset signal is connected to GPIO4_C6 on the Puma module. This pin is supplied by 1.8V, but the default iodomain setting is 3.0V and in this situation the pin is unable to go high. Linux assumes that this signal works in early boot as PCIe is probed before loading the iodomain driver. Make PCIe work in Linux by setting the gpio4cd iodomain to 1.8V. Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher(a)theobroma-systems.com> --- board/theobroma-systems/puma_rk3399/puma-rk3399.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index c9768dd75c..8d407940e5 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -9,10 +9,15 @@ #include <misc.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> +#include <asm/io.h> #include <asm/setup.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/arch/grf_rk3399.h> #include <asm/arch/periph.h> #include <power/regulator.h> #include <spl.h> +#include <syscon.h> #include <u-boot/sha256.h> DECLARE_GLOBAL_DATA_PTR; @@ -145,10 +150,25 @@ static void setup_serial(void) #endif } +static void setup_iodomain(void) +{ + const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3; + struct rk3399_grf_regs *grf = + syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* + * Set bit 3 in GRF_IO_VSEL so PCIE_RST# works (pin GPIO4_C6). + * Linux assumes that PCIE_RST# works out of the box as it probes + * PCIe before loading the iodomain driver. + */ + rk_setreg(&grf->io_vsel, 1 << GRF_IO_VSEL_GPIO4CD_SHIFT); +} + int misc_init_r(void) { setup_serial(); setup_macaddr(); + setup_iodomain(); return 0; } -- 2.11.0

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[U-Boot] [PATCH] rockchip: config: update part table
by Kever Yang 18 Dec '17

18 Dec '17

User do not need to access the reserved part in system, remove them from partition table. Rename atf to trust as generic name for armv7 do not use ATF. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- include/configs/rockchip-common.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 35d948a..4139a7b 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -52,10 +52,8 @@ #define PARTS_DEFAULT \ "uuid_disk=${uuid_gpt_disk};" \ "name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \ - "name=reserved1,size=64K,uuid=${uuid_gpt_reserved1};" \ - "name=reserved2,size=4M,uuid=${uuid_gpt_reserved2};" \ - "name=loader2,size=4MB,uuid=${uuid_gpt_loader2};" \ - "name=atf,size=4M,uuid=${uuid_gpt_atf};" \ + "name=loader2,start=8MB,size=4MB,uuid=${uuid_gpt_loader2};" \ + "name=trust,size=4M,uuid=${uuid_gpt_atf};" \ "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \ "name=rootfs,size=-,uuid="ROOT_UUID -- 1.9.1

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[U-Boot] [PATCH v3] rockchip: update boot0 hook
by Kever Yang 18 Dec '17

18 Dec '17

Rockchip SoCs only need boot0 hook at SPL, and the U-Boot proper do not need it. The very beginning of U-Boot proper is different between armv7 and armv8: armv7 start with ARM_VECTORS while armv8 start with 'b reset'. Here is the map of very beginning for all cases: armv7 SPL: TAG(overwrite 'b 1f')+'b reset' + ARM_VECTORS armv7 U-Boot: ARM_VECTORS armv8 SPL: TAG(overwrite 'b 1f')+'b reset' + Reserved_iram(rk3399) armv8 U-Boot: 'b reset' Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v3: - address comments from Philipp Changes in v2: - update commit message arch/arm/include/asm/arch-rockchip/boot0.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index af3a733..5d35c35 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -39,7 +39,12 @@ entry_counter: .word 0 #endif + +#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64)) + /* U-Boot proper of armv7 do not need this */ b reset +#endif + #if !defined(CONFIG_ARM64) /* * For armv7, the addr '_start' will used as vector start address @@ -50,6 +55,6 @@ _start: ARM_VECTORS #endif -#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_SPL_BUILD) && (CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0) .space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */ #endif -- 1.9.1

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[U-Boot] [PATCH] rockchip: update ROCKCHIP_SPL_RESERVE_IRAM to 0
by Kever Yang 18 Dec '17

18 Dec '17

Only rk3399 atf need ROCKCHIP_SPL_RESERVE_IRAM, so update it dtfault 0 so that other SoCs do not need to define it. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/mach-rockchip/Kconfig | 2 +- configs/evb-rk3399_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 1e74db3..967290f 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -179,7 +179,7 @@ config ROCKCHIP_BOOT_MODE_REG config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" - default 0x4000 + default 0 help SPL may need reserve memory for firmware loaded by SPL, whose load address is in IRAM and may overlay with SPL text area if not diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 7b5ea82..e8e52c3 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_DEBUG_UART=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index 731222c..b8d0654 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -4,6 +4,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3399-firefly" CONFIG_DEBUG_UART=y -- 1.9.1

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[U-Boot] [PATCH] config: Enable part command for socfpga platform
by Andrey Zhizhikin 18 Dec '17

18 Dec '17

Enable CONFIG_CMD_PART item, as default environment requires it and complains this command in unknown. Signed-off-by: Andrey Zhizhikin <andrey.z(a)gmail.com> diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 8ed6169..2685881 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_PART=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" CONFIG_CMD_UBI=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 54c3495..f49d0ab 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_PART=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" CONFIG_CMD_UBI=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 079d465..857f2f7 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_PART=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" CONFIG_CMD_UBI=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 35773e6..71bd8f1 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_PART=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" CONFIG_CMD_UBI=y -- 2.7.4

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[U-Boot] questions on SPL
by herbert 18 Dec '17

18 Dec '17

Hi I am very sorry to ask this simple question. I read a lot of document and googled online, but I still feel puzzled by the SPL of U-Boot. I has an ancient SoC s3c2440 which is armv4t architecture. s3c2440 will copy the first 4K code on NAND to static SRAM. It is obvious that u-boot bin is bigger than 4K. so Here is my question: 1. In this condition, do I must compile a SPL bin？ and flash it to the first page of NAND flash. if it's, I think the SPL should be less than 4K, or it's meaningless, It still need to copy remain content, and has no difference with a single u-boot. 2. can I only compile a regular u-boot and do copy work and relocate work at this single u-boot. namely, merge SPL and regular u-boot, does u-boot support this framework? thanks very much! From 袁建鹏 (Yuan Jianpeng)

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[U-Boot] [PATCH] arm: imx: cx9020: remove usage of mx53_dram_size
by linux-kernel-dev＠beckhoff.com 18 Dec '17

18 Dec '17

From: Patrick Bruenn <p.bruenn(a)beckhoff.com> Global variables are not available during board_init_f(). 'static uint32_t mx53_dram_size[2];' was used in board specific dram_init(), dram_init_banksize() and get_effective_memsize() to avoid multiple calls to get_ram_size(). However multiple calls are better than undefined behavior... This fixes: https://lists.denx.de/pipermail/u-boot/2017-November/313214.html https://lists.denx.de/pipermail/u-boot/2017-December/314480.html Signed-off-by: Patrick Bruenn <p.bruenn(a)beckhoff.com> --- mx53cx9020 was based on mx53loco, which still uses this global variable. If you agree, this is a bug, I can prepare a similar fix for the QSB. Maybe it makes sense to move the dram_init functions for both boards into something like boards/freescale/common/mx53_dram.c But be aware I have no QSB at hand and could only compile test that patch for mx53loco. --- board/beckhoff/mx53cx9020/mx53cx9020.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c index 021bd967c4..d8bdfc27bb 100644 --- a/board/beckhoff/mx53cx9020/mx53cx9020.c +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -59,8 +59,6 @@ static const u32 CCAT_MODE_RUN = 0x0033DC8F; DECLARE_GLOBAL_DATA_PTR; -static uint32_t mx53_dram_size[2]; - phys_size_t get_effective_memsize(void) { /* @@ -74,15 +72,13 @@ phys_size_t get_effective_memsize(void) * U-Boot into invalid memory area close to the end of the first * DRAM bank. */ - return mx53_dram_size[0]; + return get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); } int dram_init(void) { - mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); - mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); - - gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; + gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); return 0; } @@ -90,10 +86,10 @@ int dram_init(void) int dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = mx53_dram_size[0]; + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = mx53_dram_size[1]; + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); return 0; } -- 2.11.0

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[U-Boot] [GIT PULL] Xilinx fixes for v2018.01-rc2
by Michal Simek 18 Dec '17

18 Dec '17

Hi Tom, +Stephen please pull these changes to your tree. Travis is not showing any issue. https://travis-ci.org/michalsimek-test/u-boot/builds/316577925 Buildman was also fine over all patches and tests on board looks good too. I have included one patch from Stephen which we discussed for fixing zynq_cse_qspi configuration which doesn't use HUSH. Thanks, Michal The following changes since commit 659208da4703de50826a469cbb38bf6afb938978: README: update the kernel coding style reference (2017-12-12 21:34:10 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.01-rc2 for you to fetch changes up to 956a1340c8677e96f9eb364fb0070c152d591a4a: test/py: Setup variables based on HUSH selection (2017-12-14 20:09:04 +0100) ---------------------------------------------------------------- Xilinx changes for v2018.01-rc2 fpga: - Enable loading bitstream via fit image for !xilinx platforms zynq: - Fix SPL SD boot mode zynqmp: - Not not reset in panic - Do not use simple allocator because of fat changes - Various dt chagnes - modeboot variable setup - Fix fpga loading on automotive devices - Fix coverity issues test: - Fix env test for !hush case - Stephen's patch ---------------------------------------------------------------- Goldschmidt Simon (1): fpga: allow programming fpga from FIT image for all FPGA drivers Javier Martinez Canillas (1): arm64: zynqmp: Add generic compatible string for I2C EEPROM Michal Simek (19): arm: zynq: Fix SPL SD boot mode arm64: zynqmp: Do not perform reset in case of panic arm64: zynqmp: Do not use SPL_SYS_MALLOC_SIMPLE allocator arm64: zynqmp: Add reference to pmu firmware node arm64: zynqmp: Add support for generic QSPI boot arm64: zynqmp: Enable SPL_CLK when SPL is enabled arm64: zynqmp: Setup modeboot variable based on bootmode arm64: zynqmp: Enable phys for zcu102 arm64: zynqmp: Enable clock command for all boards arm64: zynqmp: Remove undocumented dma properties arm64: zynqmp: Use only earlycon bootargs instead of full one arm64: zynqmp: Add missing zynq_board_read_rom_ethaddr() prototype arm64: zynqmp: Add support for zynqmp automotive silicons arm64: zynqmp: Enable misc devices arm64: zynqmp: Enable SPL ram support arm64: zynqmp: Enable fpga bitstream loading arm64: zynqmp: Enable AES command arm64: zynqmp: Enable spi flashes tools: zynqmpimage: Check return values from file functions Siva Durga Prasad Paladugu (3): arm64: zynqmp: Read boot mode register using zynqmp_mmio_read arm64: zynqmp: Dont use 4K sector erase by default for spi-flashes arm64: zynqmp: Access timestamp_ref_ctrl register only if running in el3 Stephen Warren (1): test/py: Setup variables based on HUSH selection arch/arm/Kconfig | 2 +- arch/arm/dts/zynqmp-ep108.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 9 --------- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 11 +---------- arch/arm/dts/zynqmp-zcu102-revA.dts | 20 +++++++++++--------- arch/arm/dts/zynqmp.dtsi | 3 ++- arch/arm/include/asm/arch-zynqmp/sys_proto.h | 1 + board/xilinx/zynqmp/zynqmp.c | 23 +++++++++++++++++++---- common/bootm.c | 2 +- common/image.c | 6 ++---- configs/syzygy_hub_defconfig | 2 ++ configs/topic_miami_defconfig | 2 ++ configs/topic_miamilite_defconfig | 2 ++ configs/topic_miamiplus_defconfig | 2 ++ configs/xilinx_zynqmp_ep_defconfig | 7 ++++++- configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 10 +++++++++- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 8 +++++++- configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 15 ++++++++++++++- configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 8 +++++++- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 10 +++++++++- configs/xilinx_zynqmp_zcu102_revA_defconfig | 10 +++++++++- configs/xilinx_zynqmp_zcu102_revB_defconfig | 10 +++++++++- configs/zynq_cc108_defconfig | 2 ++ configs/zynq_cse_qspi_defconfig | 2 ++ configs/zynq_microzed_defconfig | 2 ++ configs/zynq_picozed_defconfig | 2 ++ configs/zynq_z_turn_defconfig | 2 ++ configs/zynq_zc702_defconfig | 2 ++ configs/zynq_zc706_defconfig | 2 ++ configs/zynq_zc770_xm010_defconfig | 2 ++ configs/zynq_zc770_xm011_defconfig | 2 ++ configs/zynq_zc770_xm012_defconfig | 2 ++ configs/zynq_zc770_xm013_defconfig | 2 ++ configs/zynq_zed_defconfig | 2 ++ configs/zynq_zybo_defconfig | 2 ++ drivers/fpga/fpga.c | 9 +++++++++ drivers/fpga/xilinx.c | 13 +++++++++++++ include/configs/xilinx_zynqmp.h | 16 +++++++++++++--- include/configs/zynq-common.h | 7 ++----- include/fpga.h | 1 + test/py/tests/test_env.py | 11 ++++++++++- tools/zynqmpimage.c | 32 +++++++++++++++++++++++++++----- 44 files changed, 219 insertions(+), 81 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs

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[U-Boot] [PULL] Please pull u-boot-imx
by Stefano Babic 18 Dec '17

18 Dec '17

Hi Tom, please pull from u-boot-imx, thanks ! The following changes since commit fcc8250c2f7c982f3593a8eecf737f8e2c95f222: Merge git://git.denx.de/u-boot-mips (2017-11-28 16:54:30 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 1040d801f8ffe96c7eff16454a4529fdf1d46c50: arm: imx: add tzic interrupt controller for imx53 (2017-12-17 11:08:38 +0100) ---------------------------------------------------------------- Adam Ford (1): mx6_common: remove dead code Breno Lima (5): mx6slevk: imximage.cfg: Handle the CONFIG_SECURE_BOOT case warp: imximage.cfg: Handle the CONFIG_SECURE_BOOT case mx6sl: Select MX6SL option via Kconfig Kconfig: mx6ull: Deselect MX6UL from CONFIG_MX6ULL imx: Kconfig: Add HAS_CAAM option Christopher Spinrath (4): ARM: imx: cm-fx6: reinstate USB support by syncing the devicetree with Linux ARM: imx: cm_fx6: defconfig: enable CONFIG_DM_KEYBOARD ARM: imx: cm_fx6: remove sata init code from board file ARM: imx: cm_fx6: remove esdhc init code from board file Fabio Estevam (3): imx: Unify CONFIG_BOOTDELAY imx: Add a common way for detecting NXP boards revision mx6sxsabresd: Load the correct dtb for revA board Hannu Lounento (5): net: e1000: add support for writing to EEPROM net: e1000: split e1000_read_mac_addr net: e1000: implement eth_write_hwaddr board: ge: bx50v3: program MAC address to I210 board: ge: bx50v3: mount rootfs read-only Ian Ray (5): configs: Add network device support for bx50v3 products board: ge: bx50v3: Support FIT and select configuration based on VPD config: ge_bx50v3: read boot script configs: ge_bx50v3: enable bootcount configs: ge_bx50v3: automatic partition selection and video output failure message Lukasz Majewski (1): ARM: imx: display5: config: Update display5_factory_defconfig to use USE_BOOTCOMMAND Marek Vasut (1): ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK Martyn Welch (4): board: ge: mx53ppd: Move check_time() to common location board: ge: Enable access to i2c bus 1 and 2 board: ge: bx50v3: move FEC MAC address programming to driver board: ge: bx50v3: Enable hardware watchdog Nandor Han (2): rtc: adding RX8010SJ rtc driver board,ge,bx50v3 - rtc time validation Patrick Bruenn (1): arm: imx: add tzic interrupt controller for imx53 Peng Fan (2): power: pmic.h: include dm/ofnode.h power: pmic/regulator allow dm be omitted by SPL Vagrant Cascadian (1): imx: Fix missing spl_sd configuration for wandboard. arch/arm/dts/imx53.dtsi | 8 ++ arch/arm/dts/imx6q-cm-fx6.dts | 396 +++++++++++++++++++++++++++++++++++++++++++++++-------- arch/arm/include/asm/mach-imx/sys_proto.h | 3 + arch/arm/mach-imx/Kconfig | 13 +- arch/arm/mach-imx/cpu.c | 25 ++++ arch/arm/mach-imx/mx6/Kconfig | 13 +- arch/arm/mach-imx/mx7/Kconfig | 1 + board/compulab/cm_fx6/cm_fx6.c | 71 ---------- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 - board/freescale/mx6sabreauto/mx6sabreauto.c | 47 +------ board/freescale/mx6slevk/imximage.cfg | 9 ++ board/freescale/mx6sxsabresd/mx6sxsabresd.c | 16 ++- board/ge/bx50v3/bx50v3.c | 130 ++++++++++++------ board/ge/common/Makefile | 2 +- board/ge/common/ge_common.c | 55 ++++++++ board/ge/common/ge_common.h | 7 + board/ge/mx53ppd/mx53ppd.c | 47 +------ board/warp/imximage.cfg | 9 ++ configs/cm_fx6_defconfig | 1 + configs/display5_factory_defconfig | 4 +- configs/ge_b450v3_defconfig | 7 +- configs/ge_b650v3_defconfig | 7 +- configs/ge_b850v3_defconfig | 8 +- configs/mx23evk_defconfig | 1 - configs/mx25pdk_defconfig | 1 - configs/mx28evk_auart_console_defconfig | 1 - configs/mx28evk_defconfig | 1 - configs/mx28evk_nand_defconfig | 1 - configs/mx28evk_spi_defconfig | 1 - configs/mx31ads_defconfig | 1 - configs/mx31pdk_defconfig | 1 - configs/mx35pdk_defconfig | 1 - configs/mx51evk_defconfig | 1 - configs/mx53ard_defconfig | 1 - configs/mx53evk_defconfig | 1 - configs/mx53loco_defconfig | 1 - configs/mx53smd_defconfig | 1 - configs/mx6sabreauto_defconfig | 2 +- configs/mx6sabresd_defconfig | 1 - configs/mx6slevk_defconfig | 3 +- configs/mx6slevk_spinor_defconfig | 3 +- configs/mx6slevk_spl_defconfig | 3 +- configs/mx6sllevk_defconfig | 1 - configs/mx6sllevk_plugin_defconfig | 1 - configs/mx6sxsabreauto_defconfig | 1 - configs/mx6sxsabresd_defconfig | 2 +- configs/mx6sxsabresd_spl_defconfig | 2 +- configs/mx6ul_14x14_evk_defconfig | 1 - configs/mx6ul_9x9_evk_defconfig | 1 - configs/mx6ull_14x14_evk_defconfig | 1 - configs/mx6ull_14x14_evk_plugin_defconfig | 1 - configs/mx7dsabresd_defconfig | 1 - configs/mx7dsabresd_secure_defconfig | 1 - configs/wandboard_defconfig | 1 + configs/warp_defconfig | 2 +- drivers/net/e1000.c | 292 +++++++++++++++++++++++++++++++++++++--- drivers/net/e1000.h | 3 + drivers/power/pmic/Makefile | 4 +- drivers/power/regulator/Makefile | 2 +- drivers/rtc/Kconfig | 6 + drivers/rtc/Makefile | 1 + drivers/rtc/rx8010sj.c | 378 ++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/ge_bx50v3.h | 190 +++++++++++--------------- include/configs/mx6_common.h | 3 - include/configs/mx6sxsabresd.h | 8 +- include/power/pmic.h | 1 + 66 files changed, 1370 insertions(+), 443 deletions(-) create mode 100644 board/ge/common/ge_common.c create mode 100644 board/ge/common/ge_common.h create mode 100644 drivers/rtc/rx8010sj.c -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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