August 2016 - U-Boot

[U-Boot] [PATCH RESEND] phy: atheros: add support for RGMII_ID, RGMII_TXID and RGMII_RXID
by Andrea Merello 13 Oct '16

13 Oct '16

This adds support for internal delay on RX and TX on RGMII interface for the AR8035 phy. This is basically the same Linux driver do. Tested on a Zynq Zturn board (for which u-boot support in is my tree; first patch waiting ML approval) Signed-off-by: Andrea Merello <andrea.merello(a)gmail.com> diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index e57c412..694a338 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -31,6 +31,22 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { + /* select debug reg 5 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5); + /* enable tx delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100); + } + + if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || + (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) { + /* select debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0); + /* enable rx delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000); + } + phydev->supported = phydev->drv->features; genphy_config_aneg(phydev); -- 2.1.4

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[U-Boot] [PATCH 0/5] armv8: Add generic PSCI client support
by Alexander Graf 13 Oct '16

13 Oct '16

On aarch64 systems, Linux only has managed to push almost everyone to using PSCI as standardized interface for CPU start/stop operations. Fortunately PSCI also gives us a nicely abstracted interface to reset and power off the system. This patch set adds support for generic PSCI reset/shutdown support and ties it up to EFI Run Time Services, so that an OS like Linux will magically have reset and shutdown work. Alexander Graf (5): efi_loader: Allow boards to implement get_time and reset_system arm: Disable HVC PSCI calls by default arm: Add PSCI shutdown function arm: Provide common PSCI based reset handler efi_loader: Add generic PSCI RTS arch/arm/cpu/armv8/Kconfig | 18 ++++++++ arch/arm/cpu/armv8/fwcall.c | 59 ++++++++++++++++++++++-- arch/arm/include/asm/system.h | 12 +---- arch/arm/mach-meson/board.c | 5 --- board/xilinx/zynqmp/zynqmp.c | 5 --- cmd/bootefi.c | 4 ++ include/efi_loader.h | 18 ++++++++ lib/efi_loader/efi_runtime.c | 101 +++++++++++++++++++++++++++++++++++++----- 8 files changed, 187 insertions(+), 35 deletions(-) -- 1.8.5.6

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[U-Boot] [PATCH] fsl_sec_mon: Update driver for Security Monitor
by Sumit Garg 08 Oct '16

08 Oct '16

Update the API's for transition of Security Monitor states. Instead of providing both initial and final states for transition, just provide final state for transition as Security Monitor driver will take care of it internally. Signed-off-by: Sumit Garg <sumit.garg(a)nxp.com> --- board/freescale/common/fsl_validate.c | 52 ++------ drivers/misc/fsl_sec_mon.c | 240 ++++++++++++++++++---------------- include/fsl_sec_mon.h | 12 +- 3 files changed, 151 insertions(+), 153 deletions(-) diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 37c249d..91e6b50 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -339,27 +339,15 @@ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) */ static void fsl_secboot_header_verification_failure(void) { - struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); /* 29th bit of OSPR is ITS */ u32 its = sfp_in32(&sfp_regs->ospr) >> 2; - /* - * Read the SEC_MON status register - * Read SSM_ST field - */ - sts = sec_mon_in32(&sec_mon_regs->hp_stat); - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { - if (its == 1) - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_SOFT_FAIL); - else - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_NON_SECURE); - } + if (its == 1) + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + else + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); @@ -376,32 +364,20 @@ static void fsl_secboot_header_verification_failure(void) */ static void fsl_secboot_image_verification_failure(void) { - struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; - /* - * Read the SEC_MON status register - * Read SSM_ST field - */ - sts = sec_mon_in32(&sec_mon_regs->hp_stat); - if ((sts & HPSR_SSM_ST_MASK) == HPSR_SSM_ST_TRUST) { - if (its == 1) { - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_SOFT_FAIL); - - printf("Generating reset request\n"); - do_reset(NULL, 0, 0, NULL); - /* If reset doesn't coocur, halt execution */ - do_esbc_halt(NULL, 0, 0, NULL); - - } else { - change_sec_mon_state(HPSR_SSM_ST_TRUST, - HPSR_SSM_ST_NON_SECURE); - } + if (its == 1) { + set_sec_mon_state(HPSR_SSM_ST_SOFT_FAIL); + + printf("Generating reset request\n"); + do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + + } else { + set_sec_mon_state(HPSR_SSM_ST_NON_SECURE); } } diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c index d482a7d..415232e 100644 --- a/drivers/misc/fsl_sec_mon.c +++ b/drivers/misc/fsl_sec_mon.c @@ -7,140 +7,158 @@ #include <common.h> #include <fsl_sec_mon.h> -int change_sec_mon_state(u32 initial_state, u32 final_state) +static u32 get_sec_mon_state(void) { struct ccsr_sec_mon_regs *sec_mon_regs = (void *) (CONFIG_SYS_SEC_MON_ADDR); - u32 sts = sec_mon_in32(&sec_mon_regs->hp_stat); + return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK; +} + +static int set_sec_mon_state_non_sec(void) +{ + u32 sts; int timeout = 10; + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); - if ((sts & HPSR_SSM_ST_MASK) != initial_state) - return -1; + sts = get_sec_mon_state(); - if (initial_state == HPSR_SSM_ST_TRUST) { - switch (final_state) { - case HPSR_SSM_ST_NON_SECURE: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); - - /* - * poll till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } - } + switch (sts) { + /* + * If initial state is check or Non-Secure, then set the Software + * Security Violation Bit and transition to Non-Secure State. + */ + case HPSR_SSM_ST_CHECK: + printf("SEC_MON state transitioning to Non Secure.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } + /* polling loop till SEC_MON is in Non Secure state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_NON_SECURE) + break; + + udelay(10); + timeout--; + } - timeout = 10; + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + break; + + /* + * If initial state is Trusted, Secure or Soft-Fail, then first set + * the Software Security Violation Bit and transition to Soft-Fail + * State. + */ + case HPSR_SSM_ST_TRUST: + case HPSR_SSM_ST_SECURE: + case HPSR_SSM_ST_SOFT_FAIL: + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_SV); + + /* polling loop till SEC_MON is in Soft-Fail state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) + break; + + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } + + timeout = 10; + /* + * If SSM Soft Fail to Non-Secure State Transition + * disable is not set, then set SSM_ST bit and + * transition to Non-Secure State. + */ + if ((sec_mon_in32(&sec_mon_regs->hp_com) & + HPCOMR_SSM_SFNS_DIS) == 0) { printf("SEC_MON state transitioning to Non Secure.\n"); sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SSM_ST); - /* - * poll till SEC_MON is in - * Non Secure state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_NON_SECURE)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_NON_SECURE) - break; - - udelay(10); - timeout--; - } - } + /* polling loop till SEC_MON is in Non Secure*/ + while (timeout) { + sts = get_sec_mon_state(); - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } - break; - case HPSR_SSM_ST_SOFT_FAIL: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); - - /* - * polling loop till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_NON_SECURE) + break; + + udelay(10); + timeout--; } if (timeout == 0) { printf("SEC_MON state transition timeout.\n"); return -1; } - break; - default: - return -1; } - } else if (initial_state == HPSR_SSM_ST_NON_SECURE) { - switch (final_state) { - case HPSR_SSM_ST_SOFT_FAIL: - printf("SEC_MON state transitioning to Soft Fail.\n"); - sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); - - /* - * polling loop till SEC_MON is in - * Soft Fail state - */ - while (((sts & HPSR_SSM_ST_MASK) != - HPSR_SSM_ST_SOFT_FAIL)) { - while (timeout) { - sts = sec_mon_in32 - (&sec_mon_regs->hp_stat); - - if ((sts & HPSR_SSM_ST_MASK) == - HPSR_SSM_ST_SOFT_FAIL) - break; - - udelay(10); - timeout--; - } - } + break; + default: + printf("SEC_MON already in Non Secure state.\n"); + return 0; + } + return 0; +} - if (timeout == 0) { - printf("SEC_MON state transition timeout.\n"); - return -1; - } +static int set_sec_mon_state_soft_fail(void) +{ + u32 sts; + int timeout = 10; + struct ccsr_sec_mon_regs *sec_mon_regs = (void *) + (CONFIG_SYS_SEC_MON_ADDR); + + printf("SEC_MON state transitioning to Soft Fail.\n"); + sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); + + /* polling loop till SEC_MON is in Soft-Fail state */ + while (timeout) { + sts = get_sec_mon_state(); + + if ((sts & HPSR_SSM_ST_MASK) == + HPSR_SSM_ST_SOFT_FAIL) break; - default: - return -1; - } + + udelay(10); + timeout--; } + if (timeout == 0) { + printf("SEC_MON state transition timeout.\n"); + return -1; + } return 0; } + +int set_sec_mon_state(u32 state) +{ + int ret = -1; + + switch (state) { + case HPSR_SSM_ST_NON_SECURE: + ret = set_sec_mon_state_non_sec(); + break; + case HPSR_SSM_ST_SOFT_FAIL: + ret = set_sec_mon_state_soft_fail(); + break; + default: + printf("SEC_MON state transition not supported.\n"); + return 0; + } + + return ret; +} diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index b6794ce..1f31f88 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -34,13 +34,16 @@ struct ccsr_sec_mon_regs { u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */ }; -#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ -#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ -#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ +#define HPCOMR_SW_SV 0x100 /* Security Violation bit */ +#define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */ +#define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */ +#define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ +#define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */ #define HPSR_SSM_ST_NON_SECURE 0xb00 /* SEC_MON is in non secure state */ #define HPSR_SSM_ST_TRUST 0xd00 /* SEC_MON is in trusted state */ #define HPSR_SSM_ST_SOFT_FAIL 0x300 /* SEC_MON is in soft fail state */ +#define HPSR_SSM_ST_SECURE 0xf00 /* SEC_MON is in secure state */ #define HPSR_SSM_ST_MASK 0xf00 /* Mask for SSM_ST field */ /* @@ -53,6 +56,7 @@ enum { SEC_MON_SW_SV, }; -int change_sec_mon_state(uint32_t initial_state, uint32_t final_state); +/* Transition SEC_MON state */ +int set_sec_mon_state(u32 state); #endif /* __FSL_SEC_MON_H */ -- 1.8.1.4

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[U-Boot] [PATCH 1/2] armv8: fsl-lsch2: adjust sata parameter
by yuantian.tang＠nxp.com 08 Oct '16

08 Oct '16

From: Tang Yuantian <Yuantian.Tang(a)nxp.com> The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian <yuantian.tang(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 -- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index f62b78d..6333122 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -223,8 +223,6 @@ int sata_init(void) struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); ahci_init((void __iomem *)CONFIG_SYS_SATA); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 8d4a7ad..d5fe0ce 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -60,8 +60,6 @@ struct cpu_type { /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28184d1f -#define AHCI_PORT_PHY_3_CFG 0x0e081509 #define AHCI_PORT_TRANS_CFG 0x08000029 /* AHCI (sata) register map */ -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/6] tools/env: refactor flash read/write function
by Andreas Fenkart 08 Oct '16

08 Oct '16

Take advantage of the environment being block aligned block alignment is enforced since 183923d3e4 Andreas Fenkart (6): tools/env: factor out environment_end function tools/env: pass bad block offset by value tools/env: lookup dev_type directly from flash_read_buf/flash_write_buf tools/env: flash_write_buf: enforce offset to be start of environment tools/env: flash_write_buf: remove block alignment calculations tools/env: flash_read_buf: enforce offset to be start of environment tools/env/fw_env.c | 121 ++++++++++++++++++++--------------------------------- 1 file changed, 45 insertions(+), 76 deletions(-) -- 2.8.1

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[U-Boot] [PATCH] gunzip: cache-align write buffer memory
by Clemens Gruber 08 Oct '16

08 Oct '16

When using gzwrite to eMMC on an i.MX6Q board, the following warning occurs repeatedly: CACHE: Misaligned operation at range [4fd63318, 4fe63318] This patch cache-aligns the memory allocation for the gzwrite writebuf, therefore avoiding the misaligned dcache flush and the warning from check_cache_range. Signed-off-by: Clemens Gruber <clemens.gruber(a)pqgruber.com> --- lib/gunzip.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/gunzip.c b/lib/gunzip.c index bc746d6..832b306 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -11,6 +11,7 @@ #include <console.h> #include <image.h> #include <malloc.h> +#include <memalign.h> #include <u-boot/zlib.h> #include <div64.h> @@ -193,7 +194,7 @@ int gzwrite(unsigned char *src, int len, s.next_in = src + i; s.avail_in = payload_size+8; - writebuf = (unsigned char *)malloc(szwritebuf); + writebuf = (unsigned char *)malloc_cache_aligned(szwritebuf); /* decompress until deflate stream ends or end of file */ do { -- 2.9.3

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[U-Boot] [PATCH] dm: ehci-mx6: support driver model
by Peng Fan 08 Oct '16

08 Oct '16

Support driver model for ehci mx6 driver. Consolidate code to be shared between DM and non-DM, such as introducing ehci_mx6_common_init. For simplicity, some old fasion code are keeped for DM usage, such as board_ehci_power and board_usb_phy_mode. And 'dr-mode', usbphy and vbus handling code for DM is not added now. These will be added in future patches. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> Cc: Stefan Agner <stefan(a)agner.ch> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/usb/host/ehci-mx6.c | 144 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 130 insertions(+), 14 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 922ef29..83364e1 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -15,6 +15,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/imx-common/iomux-v3.h> +#include <dm.h> #include "ehci.h" @@ -303,6 +304,30 @@ int __weak board_ehci_power(int port, int on) return 0; } +int ehci_mx6_common_init(struct usb_ehci *ehci, int index) +{ + int ret; + + enable_usboh3_clk(1); + mdelay(1); + + /* Do board specific initialization */ + ret = board_ehci_hcd_init(index); + if (ret) + return ret; + + usb_power_config(index); + usb_oc_config(index); + +#if defined(CONFIG_MX6) + usb_internal_phy_clock_gate(index, 1); + usb_phy_enable(index, ehci); +#endif + + return 0; +} + +#ifndef CONFIG_DM_USB int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -318,26 +343,18 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (index > 3) return -EINVAL; - enable_usboh3_clk(1); - mdelay(1); - /* Do board specific initialization */ - ret = board_ehci_hcd_init(index); + ret = ehci_mx6_common_init(ehci, index); if (ret) return ret; - usb_power_config(index); - usb_oc_config(index); - -#if defined(CONFIG_MX6) - usb_internal_phy_clock_gate(index, 1); - usb_phy_enable(index, ehci); -#endif type = board_usb_phy_mode(index); - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + if (hccr && hcor) { + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uint32_t)*hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + } if ((type == init) || (type == USB_INIT_DEVICE)) board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); @@ -359,3 +376,102 @@ int ehci_hcd_stop(int index) { return 0; } +#else +struct ehci_mx6_priv_data { + struct ehci_ctrl ctrl; + struct usb_ehci *ehci; + enum usb_init_type init_type; + int portnr; +}; + +static int mx6_init_after_reset(struct ehci_ctrl *dev) +{ + struct ehci_mx6_priv_data *priv = dev->priv; + enum usb_init_type type = priv->init_type; + struct usb_ehci *ehci = priv->ehci; + int ret; + + ret = ehci_mx6_common_init(priv->ehci, priv->portnr); + if (ret) + return ret; + + board_ehci_power(priv->portnr, (type == USB_INIT_DEVICE) ? 0 : 1); + + if (type == USB_INIT_DEVICE) + return 0; + + setbits_le32(&ehci->usbmode, CM_HOST); + writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + + mdelay(10); + + return 0; +} + +static const struct ehci_ops mx6_ehci_ops = { + .init_after_reset = mx6_init_after_reset +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct usb_platdata *plat = dev_get_platdata(dev); + struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev); + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + int ret; + + priv->ehci = ehci; + priv->portnr = dev->seq; + priv->init_type = plat->init_type; + + ret = ehci_mx6_common_init(ehci, priv->portnr); + if (ret) + return ret; + + board_ehci_power(priv->portnr, (priv->init_type == USB_INIT_DEVICE) ? 0 : 1); + + if (priv->init_type == USB_INIT_HOST) { + setbits_le32(&ehci->usbmode, CM_HOST); + writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + } + + mdelay(10); + + hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t)hccr + + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); + + return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id mx6_usb_ids[] = { + { .compatible = "fsl,imx27-usb" }, + { } +}; + +U_BOOT_DRIVER(usb_mx6) = { + .name = "ehci_mx6", + .id = UCLASS_USB, + .of_match = mx6_usb_ids, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif -- 2.6.2

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[U-Boot] [PATCH 00/10] mx7: add dt support for Colibri iMX7S/iMX7D
by Stefan Agner 06 Oct '16

06 Oct '16

From: Stefan Agner <stefan.agner(a)toradex.com> This patchset adds device tree support for Colibri iMX7S/iMX7D. It is the first device tree enabled board for any i.MX 7 SoC hence the patchset adds some common infrastructure: - Add device tree support for serial_mxc. - imx7.dtsi - I descided to leave the s/d suffix since the SoCs are very similar and boards will likely use runtime detection to distinguish the two available SoCs. - The pinmux file imx7d-pinfunc.h is taken from the Kernel and stored in the same place Otherwise the conversion is quite straightforward and simplified the board code somewhat. Two patches enhance the board support with PMIC support, which has been the driver for this conversion. -- Stefan Stefan Agner (10): dm: imx: serial: support device tree pinctrl: imx: do not announce driver initialization arm: dts: imx7: add pinctrl defines arm: dts: imx7: add basic i.MX 7/Colibri iMX7 device tree colibri_imx7: remove legancy I2C support colibri_imx7: remove legancy UART platform data power: pmic: add Ricoh RN5T567 PMIC support arm: dts: imx7: add Ricoh RN5T567 PMIC node colibri_imx7: use Ricoh RN5T567 to reboot the board configs: enable device tree for Colibri iMX7 arch/arm/dts/Makefile | 2 + arch/arm/dts/imx7-colibri.dts | 97 ++ arch/arm/dts/imx7.dtsi | 194 ++++ arch/arm/dts/imx7d-pinfunc.h | 1151 ++++++++++++++++++++++++ board/toradex/colibri_imx7/colibri_imx7.c | 92 +- configs/colibri_imx7_defconfig | 10 +- doc/device-tree-bindings/pmic/rn5t567.txt | 17 + doc/device-tree-bindings/serial/mxc-serial.txt | 8 + drivers/pinctrl/nxp/pinctrl-imx.c | 2 +- drivers/power/pmic/Kconfig | 8 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/rn5t567.c | 64 ++ drivers/serial/serial_mxc.c | 28 +- include/configs/colibri_imx7.h | 3 +- include/power/rn5t567_pmic.h | 115 +++ 15 files changed, 1736 insertions(+), 56 deletions(-) create mode 100644 arch/arm/dts/imx7-colibri.dts create mode 100644 arch/arm/dts/imx7.dtsi create mode 100644 arch/arm/dts/imx7d-pinfunc.h create mode 100644 doc/device-tree-bindings/pmic/rn5t567.txt create mode 100644 doc/device-tree-bindings/serial/mxc-serial.txt create mode 100644 drivers/power/pmic/rn5t567.c create mode 100644 include/power/rn5t567_pmic.h -- 2.9.0

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[U-Boot] [PATCH] net, cmd: fix misaligned cache operation warning
by Heiko Schocher 06 Oct '16

06 Oct '16

when using tftp on the smartweb board, it prints, when using the tftp command: Using ethernet@fffc4000 device TFTP from server 192.168.1.1; our IP address is 192.168.20.80 Filename '/tftpboot/smartweb_hw/tbot/u-boot.bin'. Load address: 0x21000000 Loading: ########################### 73.2 KiB/s done Bytes transferred = 391560 (5f988 hex) CACHE: Misaligned operation at range [21000000, 2105f988] U-Boot# Fixing this. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- cmd/net.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/net.c b/cmd/net.c index b2f3c7b..540daeb 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -244,7 +244,7 @@ static int netboot_common(enum proto_t proto, cmd_tbl_t *cmdtp, int argc, } /* flush cache */ - flush_cache(load_addr, size); + flush_cache(load_addr, ALIGN(size, CONFIG_SYS_CACHELINE_SIZE)); bootstage_mark(BOOTSTAGE_ID_NET_LOADED); -- 2.5.5

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[U-Boot] [PATCH] imx_watchdog: Do not assert WDOG_B on watchdog init
by Ross Parker 04 Oct '16

04 Oct '16

Currently the driver asserts WDOG_B by clearing WCR_WDA bit when enabling the watchdog. Do not clear WCR_WDA. Signed-off-by: Ross Parker <rossjparker(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/watchdog/imx_watchdog.c | 2 +- include/fsl_wdog.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 2938d9f..3f826d1 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -34,7 +34,7 @@ void hw_watchdog_init(void) #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | - SET_WCR_WT(timeout), &wdog->wcr); + WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); hw_watchdog_reset(); } #endif diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h index f698d4d..7818f78 100644 --- a/include/fsl_wdog.h +++ b/include/fsl_wdog.h @@ -15,5 +15,6 @@ struct watchdog_regs { #define WCR_WDE 0x04 #define WCR_WDT 0x08 #define WCR_SRS 0x10 +#define WCR_WDA 0x20 #define SET_WCR_WT(x) (x << 8) #define WCR_WT_MSK SET_WCR_WT(0xFF) -- 1.9.1

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