August 2016 - U-Boot

[U-Boot] [PATCHv2 1/5] fsl: serdes: ensure accessing the initialized maps of serdes protocol
by Zhiqiang Hou 30 Nov '16

30 Nov '16

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- V2: - Check initialization-state of the serdes protocol map before serdes init. - Comment the element 'NONE' used as a initialization-state flag. arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 15 +++++++++++++-- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 12 ++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 12 ++++++++++++ .../arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/fsl_serdes.h | 4 ++++ arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 18 ++++++++++++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 8 ++++++++ arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/p1010_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc85xx/p1022_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc85xx/p1023_serdes.c | 12 +++++++++++- arch/powerpc/cpu/mpc85xx/p2020_serdes.c | 9 +++++++++ arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c | 20 +++++++++++++++++++- arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c | 20 +++++++++++++++++++- arch/powerpc/include/asm/fsl_serdes.h | 4 ++++ 23 files changed, 276 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c index 9b78acb..86ace90 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -23,9 +23,15 @@ int is_serdes_configured(enum srds_prtcl device) u64 ret = 0; #ifdef CONFIG_SYS_FSL_SRDS_1 + if (!(serdes1_prtcl_map & (1ULL << NONE))) + fsl_serdes_init(); + ret |= (1ULL << device) & serdes1_prtcl_map; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!(serdes2_prtcl_map & (1ULL << NONE))) + fsl_serdes_init(); + ret |= (1ULL << device) & serdes2_prtcl_map; #endif @@ -87,19 +93,24 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) serdes_prtcl_map |= (1ULL << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes_prtcl_map |= (1ULL << NONE); + return serdes_prtcl_map; } void fsl_serdes_init(void) { #ifdef CONFIG_SYS_FSL_SRDS_1 - serdes1_prtcl_map = serdes_init(FSL_SRDS_1, + if (!(serdes1_prtcl_map & (1ULL << NONE))) + serdes1_prtcl_map = serdes_init(FSL_SRDS_1, CONFIG_SYS_FSL_SERDES_ADDR, RCWSR4_SRDS1_PRTCL_MASK, RCWSR4_SRDS1_PRTCL_SHIFT); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 - serdes2_prtcl_map = serdes_init(FSL_SRDS_2, + if (!(serdes2_prtcl_map & (1ULL << NONE))) + serdes2_prtcl_map = serdes_init(FSL_SRDS_2, CONFIG_SYS_FSL_SERDES_ADDR + FSL_SRDS_2 * 0x1000, RCWSR4_SRDS2_PRTCL_MASK, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index f73092a..29cd28e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -22,9 +22,15 @@ int is_serdes_configured(enum srds_prtcl device) int ret = 0; #ifdef CONFIG_SYS_FSL_SRDS_1 + if (!serdes1_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes1_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!serdes2_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes2_prtcl_map[device]; #endif @@ -98,6 +104,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; + if (serdes_prtcl_map[NONE]) + return; + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; @@ -115,6 +124,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, else serdes_prtcl_map[lane_prtcl] = 1; } + + /* Set the first element to indicate serdes has been initialized */ + serdes_prtcl_map[NONE] = 1; } void fsl_serdes_init(void) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index be6acc6..9110d7a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -28,9 +28,15 @@ int is_serdes_configured(enum srds_prtcl device) int ret = 0; #ifdef CONFIG_SYS_FSL_SRDS_1 + if (!serdes1_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes1_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!serdes2_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes2_prtcl_map[device]; #endif @@ -79,6 +85,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; + if (serdes_prtcl_map[NONE]) + return; + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; @@ -136,6 +145,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, #endif } } + + /* Set the first element to indicate serdes has been initialized */ + serdes_prtcl_map[NONE] = 1; } void fsl_serdes_init(void) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index e1b3f44..7847bf4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -11,6 +11,10 @@ #ifdef CONFIG_LS2080A enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, @@ -57,6 +61,10 @@ enum srds { }; #elif defined(CONFIG_FSL_LSCH2) enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h index 3a92f5a..22a4275 100644 --- a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -10,6 +10,10 @@ #include <config.h> enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c index 399b208..4b5cd99 100644 --- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -68,6 +68,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; } @@ -79,6 +82,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -90,4 +96,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c index 51972cb..74d27b9 100644 --- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -32,6 +32,9 @@ static const struct serdes_config serdes1_cfg_tbl[] = { int is_serdes_configured(enum srds_prtcl device) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes1_prtcl_map; } @@ -44,6 +47,9 @@ void fsl_serdes_init(void) const struct serdes_config *ptr; int lane; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -59,4 +65,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = ptr->lanes[lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 9920839..ebc9b81 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -92,15 +92,27 @@ int is_serdes_configured(enum srds_prtcl device) int ret = 0; #ifdef CONFIG_SYS_FSL_SRDS_1 + if (!serdes1_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes1_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_2 + if (!serdes2_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes2_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_3 + if (!serdes3_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes3_prtcl_map[device]; #endif #ifdef CONFIG_SYS_FSL_SRDS_4 + if (!serdes4_prtcl_map[NONE]) + fsl_serdes_init(); + ret |= serdes4_prtcl_map[device]; #endif @@ -184,6 +196,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u32 cfg; int lane; + if (serdes_prtcl_map[NONE]) + return; + memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 struct ccsr_sfp_regs __iomem *sfp_regs = @@ -325,6 +340,9 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, else serdes_prtcl_map[lane_prtcl] = 1; } + + /* Set the first element to indicate serdes has been initialized */ + serdes_prtcl_map[NONE] = 1; } void fsl_serdes_init(void) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index ba22f90..85739e9 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -136,6 +136,9 @@ int is_serdes_configured(enum srds_prtcl device) if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) return 0; + if (!(serdes_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes_prtcl_map; } @@ -514,6 +517,8 @@ void fsl_serdes_init(void) if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; #endif + if (serdes_prtcl_map & (1 << NONE)) + return; /* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -857,6 +862,9 @@ void fsl_serdes_init(void) SRDS_RSTCTL_SDPD); } #endif + + /* Set the first bit to indicate serdes has been initialized */ + serdes_prtcl_map |= (1 << NONE); } const char *serdes_clock_to_string(u32 clock) diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index baf52d5..8c075f1 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -71,11 +71,19 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map; if (ret) return ret; + if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; } @@ -88,6 +96,10 @@ void fsl_serdes_init(void) u32 tmp; int lane; + if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; @@ -221,6 +233,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel); return; @@ -230,4 +245,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c index ed78a66..b27763e 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -34,11 +34,19 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map; if (ret) return ret; + if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; } @@ -50,6 +58,10 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -61,6 +73,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -76,4 +91,7 @@ void fsl_serdes_init(void) if (pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS) serdes2_prtcl_map &= ~(1 << SGMII_TSEC3); + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c index d146955..f1042d5 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -24,6 +24,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; } @@ -35,6 +38,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg); if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -46,4 +52,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c index 9199f01..7c287a0 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8568_serdes.c @@ -24,6 +24,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; } @@ -35,6 +38,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -46,4 +52,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c index 6c80b5e..cc8ddb2 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8569_serdes.c @@ -33,6 +33,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; } @@ -44,6 +47,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -55,4 +61,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c index 3632eb5..1f0f474 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8572_serdes.c @@ -28,6 +28,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; } @@ -39,6 +42,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -62,4 +68,7 @@ void fsl_serdes_init(void) if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) serdes1_prtcl_map |= (1 << SGMII_TSEC4); + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index 4b965f7..d8c0b62 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -33,11 +33,19 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map; if (ret) return ret; + if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; } @@ -49,6 +57,10 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -60,6 +72,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -69,4 +84,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index 99a77bd..77b9439 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -41,6 +41,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; } @@ -55,6 +58,9 @@ void fsl_serdes_init(void) int lane; u32 mask, val; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -67,6 +73,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + /* Init SERDES Receiver electrical idle detection control for PCIe */ /* Lane 0 is always PCIe 1 */ diff --git a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c index 14d17eb..88013d4 100644 --- a/arch/powerpc/cpu/mpc85xx/p1022_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1022_serdes.c @@ -72,11 +72,19 @@ static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map; if (ret) return ret; + if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; } @@ -88,6 +96,10 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -99,6 +111,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -108,4 +123,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c index e83b0a3..b2b9f95 100644 --- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -24,7 +24,12 @@ static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map; return ret; } @@ -36,6 +41,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -47,4 +55,6 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c index 59d402c..0890eaa 100644 --- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -32,6 +32,9 @@ static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl prtcl) { + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << prtcl) & serdes1_prtcl_map; } @@ -43,6 +46,9 @@ void fsl_serdes_init(void) MPC85xx_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -54,4 +60,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; serdes1_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c index 2a7e3bf..ea4f4c8 100644 --- a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c +++ b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c @@ -29,11 +29,19 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map; if (ret) return ret; + if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; } @@ -46,6 +54,10 @@ void fsl_serdes_init(void) MPC8610_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -57,6 +69,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -66,4 +81,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c index cc0f8e9..5b12cbd 100644 --- a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c +++ b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c @@ -38,11 +38,19 @@ static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { int is_serdes_configured(enum srds_prtcl device) { - int ret = (1 << device) & serdes1_prtcl_map; + int ret; + + if (!(serdes1_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + + ret = (1 << device) & serdes1_prtcl_map; if (ret) return ret; + if (!(serdes2_prtcl_map & (1 << NONE))) + fsl_serdes_init(); + return (1 << device) & serdes2_prtcl_map; } @@ -55,6 +63,10 @@ void fsl_serdes_init(void) MPC8641_PORDEVSR_IO_SEL_SHIFT; int lane; + if (serdes1_prtcl_map & (1 << NONE) && + serdes2_prtcl_map & (1 << NONE)) + return; + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { @@ -66,6 +78,9 @@ void fsl_serdes_init(void) serdes1_prtcl_map |= (1 << lane_prtcl); } + /* Set the first bit to indicate serdes has been initialized */ + serdes1_prtcl_map |= (1 << NONE); + if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); return; @@ -75,4 +90,7 @@ void fsl_serdes_init(void) enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; serdes2_prtcl_map |= (1 << lane_prtcl); } + + /* Set the first bit to indicate serdes has been initialized */ + serdes2_prtcl_map |= (1 << NONE); } diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 45e248e..bef961c 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -10,6 +10,10 @@ #include <config.h> enum srds_prtcl { + /* + * Nobody will check whether the device 'NONE' has been configured, + * So use it to indicate if the serdes_prtcl_map has been initialized. + */ NONE = 0, PCIE1, PCIE2, -- 2.1.0.27.g96db324

4 10

[U-Boot] [PATCH] drivers: net: keystone_net: add rgmii link type support when parsing dt
by Mugunthan V N 29 Nov '16

29 Nov '16

Add support to detect RGMII link interface from link-interface device tree entry. Also rename the existing link type enums so that it provides meaningful interface like SGMII. Signed-off-by: Mugunthan V N <mugunthanvnm(a)ti.com> --- Tested this patch on Keystone K2G evm, logs [1] [1] - http://pastebin.ubuntu.com/23026361/ --- drivers/net/keystone_net.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index e41b7d1..0da3325 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -56,13 +56,16 @@ struct rx_buff_desc net_rx_buffs = { #ifdef CONFIG_DM_ETH enum link_type { - LINK_TYPE_MAC_TO_MAC_AUTO = 0, - LINK_TYPE_MAC_TO_PHY_MODE = 1, - LINK_TYPE_MAC_TO_MAC_FORCED_MODE = 2, - LINK_TYPE_MAC_TO_FIBRE_MODE = 3, - LINK_TYPE_MAC_TO_PHY_NO_MDIO_MODE = 4, - LINK_TYPE_10G_MAC_TO_PHY_MODE = 10, - LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11, + LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0, + LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1, + LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2, + LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3, + LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4, + LINK_TYPE_RGMII_LINK_MAC_PHY = 5, + LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6, + LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7, + LINK_TYPE_10G_MAC_TO_PHY_MODE = 10, + LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11, }; #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ @@ -1077,11 +1080,15 @@ static int ks2_eth_parse_slave_interface(int netcp, int slave, priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg"); } - if (priv->link_type == LINK_TYPE_MAC_TO_PHY_MODE) { + if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) { priv->phy_if = PHY_INTERFACE_MODE_SGMII; pdata->phy_interface = priv->phy_if; priv->sgmii_link_type = SGMII_LINK_MAC_PHY; priv->has_mdio = true; + } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) { + priv->phy_if = PHY_INTERFACE_MODE_RGMII; + pdata->phy_interface = priv->phy_if; + priv->has_mdio = true; } return 0; -- 2.9.2.664.ga0a1831

4 3

[U-Boot] [PATCH 1/2] fs/fat/fatwrite: Local variable as buffer to store dir_slot entries
by Tien Fong Chee 29 Nov '16

29 Nov '16

fill_dir_slot use get_contents_vfatname_block as a temporary buffer for constructing a list of dir_slot entries. To save the memory and providing correct type of memory for above usage, a local buffer with accurate size declaration is introduced. The local array size 640 is used because for long file name entry, each entry use 32 bytes, one entry can store up to 13 characters. The maximum number of entry possible is 20. So, total size is 32*20=640bytes. Signed-off-by: Genevieve Chan <ccheauya(a)altera.com> Signed-off-by: Tien Fong Chee <tfchee(a)altera.com> --- Changes for V2 - Removed extra space Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: ChinLiang <clsee(a)altera.com> Cc: Vagrant Cascadian <vagrant(a)debian.org> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Benoît Thébaudeau <benoit(a)wsystem.com> --- fs/fat/fat_write.c | 3 ++- include/fat.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index eb3a916..c1d48c5 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -323,7 +323,8 @@ static void flush_dir_table(fsdata *mydata, dir_entry **dentptr); static void fill_dir_slot(fsdata *mydata, dir_entry **dentptr, const char *l_name) { - dir_slot *slotptr = (dir_slot *)get_contents_vfatname_block; + __u8 temp_dir_slot_buffer[MAX_LFN_SLOT * sizeof(dir_slot)]; + dir_slot *slotptr = (dir_slot *)temp_dir_slot_buffer; __u8 counter = 0, checksum; int idx = 0, ret; char s_name[16]; diff --git a/include/fat.h b/include/fat.h index 9d053e6..483ff7c 100644 --- a/include/fat.h +++ b/include/fat.h @@ -33,6 +33,8 @@ #define FAT16BUFSIZE (FATBUFSIZE/2) #define FAT32BUFSIZE (FATBUFSIZE/4) +/* Maximum number of entry for long file name according to spec */ +#define MAX_LFN_SLOT 20 /* Filesystem identifiers */ #define FAT12_SIGN "FAT12 " -- 1.8.2.1

2 1

[U-Boot] [v2, 1/5] mmc: fsl_esdhc: don't set XFERTYP_RSPTYP_48_BUSY for CMD with busy response
by Yangbo Lu 14 Nov '16

14 Nov '16

For CMD with busy response, the eSDHC driver would poll DAT0 until CMD completion rather than polling IRQSTAT. So, don't set XFERTYP_RSPTYP_48_BUSY to avoid interrupts (DTOE or TC) in IRQSTAT. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> --- Changes for v2: - None --- drivers/mmc/fsl_esdhc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a865c7b..b23845d 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -136,8 +136,16 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) xfertyp |= XFERTYP_CICEN; if (cmd->resp_type & MMC_RSP_136) xfertyp |= XFERTYP_RSPTYP_136; - else if (cmd->resp_type & MMC_RSP_BUSY) - xfertyp |= XFERTYP_RSPTYP_48_BUSY; + /* + * For CMD with busy response, the eSDHC driver would poll DAT0 + * until CMD completion rather than polling IRQSTAT. So, don't + * set XFERTYP_RSPTYP_48_BUSY to avoid interrupts (DTOE or TC) + * in IRQSTAT. + * + * Remove: + * else if (cmd->resp_type & MMC_RSP_BUSY) + * xfertyp |= XFERTYP_RSPTYP_48_BUSY; + */ else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -- 2.1.0.27.g96db324

4 17

[U-Boot] [PATCH v2 0/5] Raspberry Pi EFI enablement
by Alexander Graf 14 Nov '16

14 Nov '16

This is a follow-up to the RTS patch set from yesterday. With this patch set I can successfully boot a Raspberry Pi 3 into Linux, with efifb, efi based reset/power off and spin table secondary bringup working. I've put all of this into a single patch set so it doesn't get lost. In theory most patches could live by themselves, but it doesn't make much sense to introduce frameworks without adding users to them :). Enjoy, Alex Alexander Graf (5): efi_loader: Allow boards to implement get_time and reset_system ARM: bcm283x: Implement EFI RTS reset_system efi_loader: gop: Expose fb when 32bpp bcm2835 video: Map frame buffer as 32bpp bcm2835: Reserve the spin table in efi memory map arch/arm/mach-bcm283x/include/mach/wdog.h | 2 +- arch/arm/mach-bcm283x/reset.c | 59 +++++++++++++++-- board/raspberrypi/rpi/rpi.c | 6 ++ cmd/bootefi.c | 4 ++ drivers/video/bcm2835.c | 6 +- include/configs/rpi.h | 2 +- include/efi_loader.h | 18 ++++++ lib/efi_loader/efi_gop.c | 16 +++++ lib/efi_loader/efi_runtime.c | 101 ++++++++++++++++++++++++++---- 9 files changed, 192 insertions(+), 22 deletions(-) -- 1.8.5.6

1 10

[U-Boot] [PATCH 1/6] x86: Add implementations of setjmp() and longjmp()
by Simon Glass 07 Nov '16

07 Nov '16

Bring in these functions from Linux v4.4. They will be needed for EFI loader support. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/setjmp.S | 71 +++++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/setjmp.h | 24 +++++++++++++++ 3 files changed, 96 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/setjmp.S create mode 100644 arch/x86/include/asm/setjmp.h diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 2667e0b..f5b8c9e 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -10,7 +10,7 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o -obj-y += interrupts.o cpu.o cpu_x86.o call64.o +obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) diff --git a/arch/x86/cpu/setjmp.S b/arch/x86/cpu/setjmp.S new file mode 100644 index 0000000..24e7d8a --- /dev/null +++ b/arch/x86/cpu/setjmp.S @@ -0,0 +1,71 @@ +/* + * Written by H. Peter Anvin <hpa(a)zytor.com> + * Brought in from Linux v4.4 and modified for U-Boot + * From Linux arch/um/sys-i386/setjmp.S + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm/global_data.h> +#include <asm/msr-index.h> +#include <asm/processor-flags.h> + +#define _REGPARM + +/* + * The jmp_buf is assumed to contain the following, in order: + * %ebx + * %esp + * %ebp + * %esi + * %edi + * <return address> + */ + + /* + * rdi - 32-bit code segment selector + * rsi - target address + * rdx - table address (0 if none) + */ + .text + .align 4 + .globl setjmp + .type setjmp, @function +setjmp: +#ifdef _REGPARM + movl %eax,%edx +#else + movl 4(%esp),%edx +#endif + popl %ecx # Return address, and adjust the stack + xorl %eax,%eax # Return value + movl %ebx,(%edx) + movl %esp,4(%edx) # Post-return %esp! + pushl %ecx # Make the call/return stack happy + movl %ebp,8(%edx) + movl %esi,12(%edx) + movl %edi,16(%edx) + movl %ecx,20(%edx) # Return address + ret + + .size setjmp,.-setjmp + + .text + .align 4 + .globl longjmp + .type longjmp, @function +longjmp: +#ifdef _REGPARM + xchgl %eax,%edx +#else + movl 4(%esp),%edx # jmp_ptr address + movl 8(%esp),%eax # Return value +#endif + movl (%edx),%ebx + movl 4(%edx),%esp + movl 8(%edx),%ebp + movl 12(%edx),%esi + movl 16(%edx),%edi + jmp *20(%edx) + + .size longjmp,.-longjmp diff --git a/arch/x86/include/asm/setjmp.h b/arch/x86/include/asm/setjmp.h new file mode 100644 index 0000000..deef67e --- /dev/null +++ b/arch/x86/include/asm/setjmp.h @@ -0,0 +1,24 @@ +/* + * Written by H. Peter Anvin <hpa(a)zytor.com> + * Brought in from Linux v4.4 and modified for U-Boot + * From Linux arch/um/sys-i386/setjmp.S + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __setjmp_h +#define __setjmp_h + +struct jmp_buf_data { + unsigned int __ebx; + unsigned int __esp; + unsigned int __ebp; + unsigned int __esi; + unsigned int __edi; + unsigned int __eip; +}; + +int setjmp(struct jmp_buf_data *jmp_buf); +void longjmp(struct jmp_buf_data *jmp_buf); + +#endif -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v2] rk3399: Reserve space for ARM Trust Firmware
by Kever Yang 04 Nov '16

04 Nov '16

RK3399 needs reserve 0x200000 at the beginning of DRAM, for ATF bl31. Signed-off-by: Kever Yang <kever.yang(a)rock-chips.com> --- Changes in v2: - correct some typo on commit message and comment board/rockchip/evb_rk3399/evb-rk3399.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index 39a26fa..84a00fc 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -35,6 +35,7 @@ int dram_init(void) void dram_init_banksize(void) { - gd->bd->bi_dram[0].start = 0; + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; gd->bd->bi_dram[0].size = 0x80000000; } -- 1.9.1

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[U-Boot] [PATCH 0/6] at91: at91sam9g15 improvements
by Heiko Schocher 28 Oct '16

28 Oct '16

This series add some missing things for an at91sam9g15 board, which gets not mainlined, but there are common fixes, which are posted with this patchserie. 2 important things: - enable icache for AT91 based boards speeds up them a lot, for example reading 8MiB from an SPI NOR flash into RAM takes with icache off ~15 seconds with icache enabled only ~5 seconds. gurnard board defines a board specific enable_caches() function which enables dcache .. with acomment that this breaks Ethernet MAC ... I removed this board specific function, and dcache enable functions should be added in arch/arm/mach-at91/arm926ejs/cache.c - SPL clock fix, posted as RFC, as it may breaks other boards. If so, we may make clock settings in SPL board configurable through a weak function? buildman finds no new errors/warnings with the patches from this patchseries applied. Heiko Schocher (6): arm: at91: mpddrc: add missing MPDDRC_MD defines ARM: at91: clock: correct PRES offset for at91sam9x5 arm, at91: add icache support arm, at91: add some missing fields in PIO struct at91: add function to set IO drive [RFC] at91: SPL clock fix for AT91SAM9G15 based boards. arch/arm/mach-at91/arm926ejs/Makefile | 1 + arch/arm/mach-at91/arm926ejs/cache.c | 29 ++++++++++++++++++++++++++ arch/arm/mach-at91/arm926ejs/clock.c | 6 ++++++ arch/arm/mach-at91/include/mach/at91_pio.h | 11 +++++++++- arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 3 +++ arch/arm/mach-at91/include/mach/gpio.h | 2 ++ arch/arm/mach-at91/spl_at91.c | 13 +++++++++--- board/bluewater/gurnard/gurnard.c | 6 ------ drivers/gpio/at91_gpio.c | 29 ++++++++++++++++++++++++++ 9 files changed, 90 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-at91/arm926ejs/cache.c -- 2.5.5

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[U-Boot] [PATCH] mmc: Tinification of the mmc code
by Marek Vasut 28 Oct '16

28 Oct '16

Add new configuration option CONFIG_MMC_TINY which strips away all memory allocation within the MMC code and code for handling multiple cards. This allows extremely space-constrained SPL code use the MMC framework. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> Cc: Simon Glass <sjg(a)chromium.org> --- common/spl/spl_mmc.c | 4 ++++ drivers/mmc/Makefile | 2 ++ drivers/mmc/mmc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++- include/mmc.h | 1 + 4 files changed, 65 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index ae42221..51f0f24 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -300,7 +300,11 @@ int spl_mmc_load_image(u32 boot_device) if (part == 7) part = 0; +#ifdef CONFIG_MMC_TINY + err = mmc_switch_part(mmc, part); +#else err = blk_dselect_hwpart(mmc_get_blk_desc(mmc), part); +#endif if (err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("spl: mmc partition switch failed\n"); diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 3da4817..4d986cb 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -10,8 +10,10 @@ obj-$(CONFIG_GENERIC_MMC) += mmc-uclass.o endif ifndef CONFIG_BLK +ifndef CONFIG_MMC_TINY obj-$(CONFIG_GENERIC_MMC) += mmc_legacy.o endif +endif obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o obj-$(CONFIG_ATMEL_SDHCI) += atmel_sdhci.o diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d687345..1f240ed 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -21,6 +21,29 @@ #include <div64.h> #include "mmc_private.h" +#if defined(CONFIG_MMC_TINY) +static struct mmc mmc_static; +struct mmc *find_mmc_device(int dev_num) +{ + return &mmc_static; +} + +void mmc_do_preinit(void) +{ + struct mmc *m = &mmc_static; +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT + mmc_set_preinit(m, 1); +#endif + if (m->preinit) + mmc_start_init(m); +} + +struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) +{ + return &mmc->block_dev; +} +#endif + __weak int board_mmc_getwp(struct mmc *mmc) { return -1; @@ -238,7 +261,11 @@ static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, if (!mmc) return 0; +#ifdef CONFIG_MMC_TINY + err = mmc_switch_part(mmc, block_dev->hwpart); +#else err = blk_dselect_hwpart(block_dev, block_dev->hwpart); +#endif if (err < 0) return 0; @@ -568,7 +595,7 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num) return 0; } -static int mmc_switch_part(struct mmc *mmc, unsigned int part_num) +int mmc_switch_part(struct mmc *mmc, unsigned int part_num) { int ret; @@ -1585,6 +1612,34 @@ int mmc_unbind(struct udevice *dev) return 0; } +#elif defined(CONFIG_MMC_TINY) +static struct mmc mmc_static = { + .dsr_imp = 0, + .dsr = 0xffffffff, + .block_dev = { + .if_type = IF_TYPE_MMC, + .removable = 1, + .devnum = 0, + .block_read = mmc_bread, + .block_write = mmc_bwrite, + .block_erase = mmc_berase, + .part_type = 0, + }, +}; + +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) +{ + struct mmc *mmc = &mmc_static; + + mmc->cfg = cfg; + mmc->priv = priv; + + return mmc; +} + +void mmc_destroy(struct mmc *mmc) +{ +} #else struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) { @@ -1834,8 +1889,10 @@ int mmc_initialize(bd_t *bis) initialized = 1; #ifndef CONFIG_BLK +#ifndef CONFIG_MMC_TINY mmc_list_init(); #endif +#endif ret = mmc_probe(bis); if (ret) return ret; diff --git a/include/mmc.h b/include/mmc.h index a5c6573..08a59c2 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -444,6 +444,7 @@ struct mmc *find_mmc_device(int dev_num); int mmc_set_dev(int dev_num); void print_mmc_devices(char separator); int get_mmc_num(void); +int mmc_switch_part(struct mmc *mmc, unsigned int part_num); int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, enum mmc_hwpart_conf_mode mode); int mmc_getcd(struct mmc *mmc); -- 2.7.0

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[U-Boot] [PATCH v3 0/4] armv8/fsl-layerscape: add dwc3 gadget driver support
by Rajat Srivastava 26 Oct '16

26 Oct '16

From: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> Adds support for dwc3 gadget driver for ARM v8 platform of layerscape series. Currently this patch has been tested for LS1043A Rajat Srivastava (3): usb: dwc3: Add helper functions to enable snooping and burst settings armv8/fsl-layerscape: add dwc3 gadget driver support armv8/fsl-layerscape: enable dwc3 gadget driver support Rajesh Bhagat (1): usb: ums: support multiple controllers using controller_index arch/arm/cpu/armv8/fsl-layerscape/soc.c | 93 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++ cmd/usb_mass_storage.c | 2 +- drivers/usb/dwc3/core.c | 45 +++++++++++ drivers/usb/dwc3/core.h | 7 ++ drivers/usb/gadget/f_mass_storage.c | 11 ++- include/configs/ls1043aqds.h | 15 ++++ include/usb_mass_storage.h | 2 +- 8 files changed, 177 insertions(+), 4 deletions(-) -- 2.6.2.198.g614a2ac

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