June 2016 - U-Boot

[U-Boot] [UBOOT PATCH] usb: ehci-hcd: Fix crash when rootdev not initialized
by Siva Durga Prasad Paladugu 29 Jun '16

29 Jun '16

This patch fixes the issue on zynq USB failure with DM when rootdev is not initialized. This variable is initalized to zero in non driver model case but not in DM. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> --- - Tested on Zynq ZC702 board with USB DM driver model patches sent by Simon. --- drivers/usb/host/ehci-hcd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 13aa70d..8adffa6 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1624,6 +1624,8 @@ int ehci_register(struct udevice *dev, struct ehci_hccr *hccr, goto err; } + ctrl->rootdev = 0; + ret = ehci_common_init(ctrl, tweaks); if (ret) goto err; -- 2.1.1

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[U-Boot] [PATCH 00/20] dm: rockchip: Move rockchip boards to to use CONFIG_BLK
by Simon Glass 29 Jun '16

29 Jun '16

This series expands the CONFIG_BLK support to SPL, fixes up the EFI boot code and adds a few other tweaks so that all rockchip boards can move to using driver model for block devices. It also introduces snprintf() in the tiny-printf code and tidies up the mmc code a little. Overall the code size for firefly-rk3288 drops by 1KB. This is mostly due to removing GPIO support and cutting down on unnecessary strings. The move to CONFIG_BLK unfortunately adds 0.5KB, or the improvement would be greater. Simon Glass (20): tiny-printf: Tidy up a few nits tiny-printf: Support snprintf() reset: Drop the reset failure message mmc: Drop mmc_register() mmc: Drop dead mmc code for non-generic MMC mmc: Use byte array for multipliers arm: Avoid error messages in cache_v7 rockchip: Check image name for the rksd image rockchip: Drop unnecessary SPL properties rockchip: video: Flush the cache when the display is updated rockchip: Drop SPL GPIO support for rk3288 dm: env: mmc: Convert env_mmc to support CONFIG_BLK dm: mmc: Convert sdhci to support CONFIG_BLK dm: efi: Update for CONFIG_BLK dm: mmc: spl: Add support for CONFIG_BLK dm: mmc: dwmmc: Support CONFIG_BLK dm: rockchip: mmc: Allow use of CONFIG_BLK dm: mmc: Fix up mmc_bread/bwrite() prototypes for SPL dm: mmc: Use cfg directly in mmc_bind() dm: rockchip: Enable CONFIG_BLK arch/arm/cpu/armv7/cache_v7.c | 8 +++--- arch/arm/mach-rockchip/Kconfig | 3 ++ cmd/mmc.c | 62 ---------------------------------------- common/env_mmc.c | 8 +++--- common/spl/spl_mmc.c | 9 +++--- configs/firefly-rk3288_defconfig | 2 +- drivers/misc/reset-uclass.c | 2 +- drivers/mmc/dw_mmc.c | 42 ++++++++++++++++++--------- drivers/mmc/mmc.c | 13 ++------- drivers/mmc/mmc_private.h | 14 +++++++++ drivers/mmc/rockchip_dw_mmc.c | 31 ++++++++++++++++++++ drivers/mmc/sdhci.c | 2 +- drivers/video/rockchip/rk_vop.c | 1 + include/configs/rk3288_common.h | 1 - include/dwmmc.h | 7 ++++- include/efi_loader.h | 2 +- include/mmc.h | 5 ---- lib/efi_loader/efi_disk.c | 61 +++++++++++++++++++++++++++++---------- lib/tiny-printf.c | 43 +++++++++++++++++++++------- tools/rkimage.c | 7 +---- 20 files changed, 181 insertions(+), 142 deletions(-) -- 2.8.0.rc3.226.g39d4020

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[U-Boot] Please pull u-boot-x86
by Bin Meng 29 Jun '16

29 Jun '16

Hi Tom, This includes a fix for coreboot-x86 for v2016.07 release. The following changes since commit 44faff24f58859bdc1acf28ac739020b5091678a: Merge git://git.denx.de/u-boot-fsl-qoriq (2016-06-28 15:59:05 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git master for you to fetch changes up to ff6e1569663eccaf9e582c57cc44568915c2f54b: x86: coreboot: Remove the dummy pch driver (2016-06-29 10:08:15 +0800) ---------------------------------------------------------------- Bin Meng (1): x86: coreboot: Remove the dummy pch driver arch/x86/cpu/coreboot/Makefile | 1 - arch/x86/cpu/coreboot/pci.c | 26 -------------------------- 2 files changed, 27 deletions(-) delete mode 100644 arch/x86/cpu/coreboot/pci.c Regards, Bin

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[U-Boot] [PATCH] x86: coreboot: Remove the dummy pch driver
by Bin Meng 29 Jun '16

29 Jun '16

There is a dummy pch driver in the coreboot directory. This causes drivers of its children fail to function due to empty ops. Remove the whole file since it is no longer needed. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/coreboot/Makefile | 1 - arch/x86/cpu/coreboot/pci.c | 26 -------------------------- 2 files changed, 27 deletions(-) delete mode 100644 arch/x86/cpu/coreboot/pci.c diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index b6e870a..d663656 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -18,4 +18,3 @@ obj-y += coreboot.o obj-y += tables.o obj-y += sdram.o obj-y += timestamp.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c deleted file mode 100644 index 7f5087a..0000000 --- a/arch/x86/cpu/coreboot/pci.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008,2009 - * Graeme Russ, <graeme.russ(a)gmail.com> - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel(a)omicron.se> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <pci.h> - -static const struct udevice_id generic_pch_ids[] = { - { .compatible = "intel,pch7" }, - { .compatible = "intel,pch9" }, - { } -}; - -U_BOOT_DRIVER(generic_pch_drv) = { - .name = "pch", - .id = UCLASS_PCH, - .of_match = generic_pch_ids, -}; -- 2.7.4

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[U-Boot] [PATCH V2 1/2] Kconfig: make NOR_BOOT a common option
by Peng Fan 29 Jun '16

29 Jun '16

Not only am335x supports booting from NOR, i.MX6 SoCs also supports booting from NOR. Make NOR_BOOT a common option to let different SoCs share it. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Heiko Schocher <hs(a)denx.de> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Christophe Ricard <christophe-h.ricard(a)st.com> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Francois Retief <fgretief(a)spaceteq.co.za> Cc: Tom Rini <trini(a)konsulko.com> --- V2: New patch board/ti/am335x/Kconfig | 9 --------- common/Kconfig | 13 +++++++++++++ 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index 11ef3ca..97374bd 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -29,15 +29,6 @@ config NOR In practice this is seen as a NOR flash module connected to the "memory cape" for the BeagleBone family. -config NOR_BOOT - bool "Support for booting from NOR flash" - depends on NOR - help - Enabling this will make a U-Boot binary that is capable of being - booted via NOR. In this case we will enable certain pinmux early - as the ROM only partially sets up pinmux. We also default to using - NOR for environment. - source "board/ti/common/Kconfig" endif diff --git a/common/Kconfig b/common/Kconfig index 4d17b10..04d092c 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -97,6 +97,19 @@ config BOOTSTAGE_STASH_SIZE endmenu +menu "Boot media" + +config NOR_BOOT + bool "Support for booting from NOR flash" + depends on NOR + help + Enabling this will make a U-Boot binary that is capable of being + booted via NOR. In this case we will enable certain pinmux early + as the ROM only partially sets up pinmux. We also default to using + NOR for environment. + +endmenu + config BOOTDELAY int "delay in seconds before automatically booting" default 0 -- 2.6.2

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Re: [U-Boot] [PATCH] configs: Re-sync after boot menu changes
by Tom Rini 29 Jun '16

29 Jun '16

On Mon, Jun 27, 2016 at 10:40:17PM -0400, Tom Rini wrote: > Signed-off-by: Tom Rini <trini(a)konsulko.com> Applied to u-boot/master, thanks! -- Tom

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[U-Boot] Please pull fsl-qoriq master
by york sun 29 Jun '16

29 Jun '16

Tom, The following changes since commit b66a5c03a0870db3045be2967b85684b1887ca18: Merge branch 'master' of git://git.denx.de/u-boot-uniphier (2016-06-21 20:43:21 -0400) are available in the git repository at: git://git.denx.de/u-boot-fsl-qoriq.git for you to fetch changes up to dee01e426b39eac974364c0658fca431894987c3: armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs (2016-06-28 12:08:54 -0700) ---------------------------------------------------------------- Abhimanyu Saini (1): armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs Hou Zhiqiang (1): armv8/fsl_lsch2: Correct the cores frequency initialization Peng Fan (2): mmc: fsl: reset to normal boot mode when eMMC fast boot mmc: fsl: introduce wp_enable Prabhakar Kushwaha (1): armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs Qianyu Gong (3): armv8: ls1043aqds: fix to get boot device info from FPGA armv8: ls1043aqds: use configurable clock armv8: ls1043aqds: print FPGA info early for QSPI boot Ye Li (1): fsl_esdhc: Update clock enable bits for USDHC .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 8 ++- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 +- arch/arm/dts/fsl-ls1012a.dtsi | 12 ---- arch/arm/dts/fsl-ls1043a.dtsi | 32 ---------- arch/arm/dts/fsl-ls2080a.dtsi | 61 ------------------- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 ++--- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 14 ++--- board/freescale/ls1043aqds/ls1043aqds.c | 12 ++-- drivers/mmc/fsl_esdhc.c | 68 +++++++++++++++++----- drivers/usb/common/fsl-errata.c | 4 +- include/configs/ls1043aqds.h | 9 +-- include/fsl_esdhc.h | 7 +++ 12 files changed, 94 insertions(+), 151 deletions(-) Thanks. York

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[U-Boot] [PATCH] net: usb: r8152: Add DM support
by Stefan Roese 28 Jun '16

28 Jun '16

Add support for driver model, so that CONFIG_DM_ETH can be defined and used with this driver. This patch also adds the read_rom_hwaddr() callback so that the ROM MAC address will be used to the DM part of this driver. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Ted Chen <tedchen(a)realtek.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/usb/eth/r8152.c | 235 ++++++++++++++++++++++++++++++++++++++++----- drivers/usb/eth/r8152.h | 4 + drivers/usb/eth/r8152_fw.c | 2 + 3 files changed, 219 insertions(+), 22 deletions(-) diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index 325b70c..a148267 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -3,9 +3,10 @@ * * SPDX-License-Identifier: GPL-2.0 * - */ + */ #include <common.h> +#include <dm.h> #include <errno.h> #include <malloc.h> #include <usb.h> @@ -15,6 +16,7 @@ #include "usb_ether.h" #include "r8152.h" +#ifndef CONFIG_DM_ETH /* local vars */ static int curr_eth_dev; /* index for name of next device detected */ @@ -23,12 +25,6 @@ struct r8152_dongle { unsigned short product; }; -struct r8152_version { - unsigned short tcr; - unsigned short version; - bool gmii; -}; - static const struct r8152_dongle const r8152_dongles[] = { /* Realtek */ { 0x0bda, 0x8050 }, @@ -54,6 +50,13 @@ static const struct r8152_dongle const r8152_dongles[] = { /* Nvidia */ { 0x0955, 0x09ff }, }; +#endif + +struct r8152_version { + unsigned short tcr; + unsigned short version; + bool gmii; +}; static const struct r8152_version const r8152_versions[] = { { 0x4c00, RTL_VER_01, 0 }, @@ -1176,11 +1179,8 @@ static int rtl_ops_init(struct r8152 *tp) return ret; } -static int r8152_init(struct eth_device *eth, bd_t *bd) +static int r8152_init_common(struct r8152 *tp) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct r8152 *tp = (struct r8152 *)dev->dev_priv; - u8 speed; int timeout = 0; int link_detected; @@ -1210,14 +1210,11 @@ static int r8152_init(struct eth_device *eth, bd_t *bd) return 0; } -static int r8152_send(struct eth_device *eth, void *packet, int length) +static int r8152_send_common(struct ueth_data *ueth, void *packet, int length) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - + struct usb_device *udev = ueth->pusb_dev; u32 opts1, opts2 = 0; - int err; - int actual_len; unsigned char msg[PKTSIZE + sizeof(struct tx_desc)]; struct tx_desc *tx_desc = (struct tx_desc *)msg; @@ -1231,18 +1228,31 @@ static int r8152_send(struct eth_device *eth, void *packet, int length) memcpy(msg + sizeof(struct tx_desc), (void *)packet, length); - err = usb_bulk_msg(dev->pusb_dev, - usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), - (void *)msg, - length + sizeof(struct tx_desc), - &actual_len, - USB_BULK_SEND_TIMEOUT); + err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out), + (void *)msg, length + sizeof(struct tx_desc), + &actual_len, USB_BULK_SEND_TIMEOUT); debug("Tx: len = %zu, actual = %u, err = %d\n", length + sizeof(struct tx_desc), actual_len, err); return err; } +#ifndef CONFIG_DM_ETH +static int r8152_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct r8152 *tp = (struct r8152 *)dev->dev_priv; + + return r8152_init_common(tp); +} + +static int r8152_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + + return r8152_send_common(dev, packet, length); +} + static int r8152_recv(struct eth_device *eth) { struct ueth_data *dev = (struct ueth_data *)eth->priv; @@ -1454,3 +1464,184 @@ int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss, debug("MAC %pM\n", eth->enetaddr); return 1; } +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_DM_ETH +static int r8152_eth_start(struct udevice *dev) +{ + struct r8152 *tp = dev_get_priv(dev); + + debug("** %s (%d)\n", __func__, __LINE__); + + return r8152_init_common(tp); +} + +void r8152_eth_stop(struct udevice *dev) +{ + struct r8152 *tp = dev_get_priv(dev); + + debug("** %s (%d)\n", __func__, __LINE__); + + tp->rtl_ops.disable(tp); +} + +int r8152_eth_send(struct udevice *dev, void *packet, int length) +{ + struct r8152 *tp = dev_get_priv(dev); + + return r8152_send_common(&tp->ueth, packet, length); +} + +int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct r8152 *tp = dev_get_priv(dev); + struct ueth_data *ueth = &tp->ueth; + uint8_t *ptr; + int ret, len; + struct rx_desc *rx_desc; + u16 packet_len; + + len = usb_ether_get_rx_bytes(ueth, &ptr); + debug("%s: first try, len=%d\n", __func__, len); + if (!len) { + if (!(flags & ETH_RECV_CHECK_DEVICE)) + return -EAGAIN; + ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ); + if (ret == -EAGAIN) + return ret; + + len = usb_ether_get_rx_bytes(ueth, &ptr); + debug("%s: second try, len=%d\n", __func__, len); + } + + rx_desc = (struct rx_desc *)ptr; + packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; + packet_len -= CRC_SIZE; + + if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) { + debug("Rx: too large packet: %d\n", packet_len); + goto err; + } + + *packetp = ptr + sizeof(struct rx_desc); + return packet_len; + +err: + usb_ether_advance_rxbuf(ueth, -1); + return -EINVAL; +} + +static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len) +{ + struct r8152 *tp = dev_get_priv(dev); + + packet_len += sizeof(struct rx_desc) + CRC_SIZE; + packet_len = ALIGN(packet_len, 8); + usb_ether_advance_rxbuf(&tp->ueth, packet_len); + + return 0; +} + +static int r8152_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct r8152 *tp = dev_get_priv(dev); + + unsigned char enetaddr[8] = { 0 }; + + debug("** %s (%d)\n", __func__, __LINE__); + memcpy(enetaddr, pdata->enetaddr, ETH_ALEN); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + + debug("MAC %pM\n", pdata->enetaddr); + return 0; +} + +int r8152_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct r8152 *tp = dev_get_priv(dev); + + debug("** %s (%d)\n", __func__, __LINE__); + r8152_read_mac(tp, pdata->enetaddr); + return 0; +} + +static int r8152_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct r8152 *tp = dev_get_priv(dev); + struct ueth_data *ueth = &tp->ueth; + + tp->udev = udev; + r8152_read_mac(tp, pdata->enetaddr); + + r8152b_get_version(tp); + + if (rtl_ops_init(tp)) + return 0; + + tp->rtl_ops.init(tp); + tp->rtl_ops.up(tp); + + rtl8152_set_speed(tp, AUTONEG_ENABLE, + tp->supports_gmii ? SPEED_1000 : SPEED_100, + DUPLEX_FULL); + + return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ); +} + +static const struct eth_ops r8152_eth_ops = { + .start = r8152_eth_start, + .send = r8152_eth_send, + .recv = r8152_eth_recv, + .free_pkt = r8152_free_pkt, + .stop = r8152_eth_stop, + .write_hwaddr = r8152_write_hwaddr, + .read_rom_hwaddr = r8152_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(r8152_eth) = { + .name = "r8152_eth", + .id = UCLASS_ETH, + .probe = r8152_eth_probe, + .ops = &r8152_eth_ops, + .priv_auto_alloc_size = sizeof(struct r8152), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id r8152_eth_id_table[] = { + /* Realtek */ + { USB_DEVICE(0x0bda, 0x8050) }, + { USB_DEVICE(0x0bda, 0x8152) }, + { USB_DEVICE(0x0bda, 0x8153) }, + + /* Samsung */ + { USB_DEVICE(0x04e8, 0xa101) }, + + /* Lenovo */ + { USB_DEVICE(0x17ef, 0x304f) }, + { USB_DEVICE(0x17ef, 0x3052) }, + { USB_DEVICE(0x17ef, 0x3054) }, + { USB_DEVICE(0x17ef, 0x3057) }, + { USB_DEVICE(0x17ef, 0x7205) }, + { USB_DEVICE(0x17ef, 0x720a) }, + { USB_DEVICE(0x17ef, 0x720b) }, + { USB_DEVICE(0x17ef, 0x720c) }, + + /* TP-LINK */ + { USB_DEVICE(0x2357, 0x0601) }, + + /* Nvidia */ + { USB_DEVICE(0x0955, 0x09ff) }, + + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table); +#endif /* CONFIG_DM_ETH */ + diff --git a/drivers/usb/eth/r8152.h b/drivers/usb/eth/r8152.h index cd44da2..784ad99 100644 --- a/drivers/usb/eth/r8152.h +++ b/drivers/usb/eth/r8152.h @@ -594,6 +594,10 @@ struct r8152 { u16 ocp_base; u8 version; + +#ifdef CONFIG_DM_ETH + struct ueth_data ueth; +#endif }; int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c index f820b16..b6c8228 100644 --- a/drivers/usb/eth/r8152_fw.c +++ b/drivers/usb/eth/r8152_fw.c @@ -5,7 +5,9 @@ * */ #include <common.h> +#include <dm.h> #include <errno.h> +#include "usb_ether.h" #include "r8152.h" static u8 r8152b_pla_patch_a[] = { -- 2.8.4

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[U-Boot] [PATCH] armv8: dts: fsl: Remove cpu nodes from Layerscape DTSIs
by Abhimanyu Saini 28 Jun '16

28 Jun '16

Currently layescape SoCs are not using cpu nodes. So removing them in favour of compatibly with similar SoCs that have different cores like LS2080A and LS2088A. This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini(a)nxp.com> --- arch/arm/dts/fsl-ls1012a.dtsi | 12 --------- arch/arm/dts/fsl-ls1043a.dtsi | 32 ----------------------- arch/arm/dts/fsl-ls2080a.dtsi | 61 ------------------------------------------- 3 files changed, 105 deletions(-) diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 546a87a..024527e 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -9,18 +9,6 @@ / { compatible = "fsl,ls1012a"; interrupt-parent = <&gic>; - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&clockgen 1 0>; - }; - - }; sysclk: sysclk { compatible = "fixed-clock"; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index bf1dfe6..a8bffba 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -15,38 +15,6 @@ / { compatible = "fsl,ls1043a"; interrupt-parent = <&gic>; - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x0>; - clocks = <&clockgen 1 0>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x1>; - clocks = <&clockgen 1 0>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x2>; - clocks = <&clockgen 1 0>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0 0x3>; - clocks = <&clockgen 1 0>; - }; - }; sysclk: sysclk { compatible = "fixed-clock"; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index a5c579c..b29ba2e 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -12,67 +12,6 @@ #address-cells = <2>; #size-cells = <2>; - cpus { - #address-cells = <2>; - #size-cells = <0>; - - /* - * We expect the enable-method for cpu's to be "psci", but this - * is dependent on the SoC FW, which will fill this in. - * - * Currently supported enable-method is psci v0.2 - */ - - /* We have 4 clusters having 2 Cortex-A57 cores each */ - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x1>; - }; - - cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x100>; - }; - - cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x101>; - }; - - cpu@200 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x200>; - }; - - cpu@201 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x201>; - }; - - cpu@300 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x300>; - }; - - cpu@301 { - device_type = "cpu"; - compatible = "arm,cortex-a57"; - reg = <0x0 0x301>; - }; - }; - memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x80000000>; -- 1.9.1

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[U-Boot] [PATCH][v3] armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs
by Prabhakar Kushwaha 28 Jun '16

28 Jun '16

Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs. like LS2080A, LS1043A, LS1012A. So append "A" at the last of SoCs. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Updated the description Changes for v3: Apped "A" uniformly across the files arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++-- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 14 +++++++------- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 14 +++++++------- drivers/usb/common/fsl-errata.c | 4 ++-- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d8ec426..f62b78d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -28,7 +28,7 @@ bool soc_has_dp_ddr(void) u32 svr = gur_in32(&gur->svr); /* LS2085A has DP_DDR */ - if (SVR_SOC_VER(svr) == SVR_LS2085) + if (SVR_SOC_VER(svr) == SVR_LS2085A) return true; return false; @@ -40,7 +40,7 @@ bool soc_has_aiop(void) u32 svr = gur_in32(&gur->svr); /* LS2085A has AIOP */ - if (SVR_SOC_VER(svr) == SVR_LS2085) + if (SVR_SOC_VER(svr) == SVR_LS2085A) return true; return false; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index df877dd..197b0eb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -8,13 +8,13 @@ #define _FSL_LAYERSCAPE_CPU_H static struct cpu_type cpu_type_list[] = { - CPU_TYPE_ENTRY(LS2080, LS2080, 8), - CPU_TYPE_ENTRY(LS2085, LS2085, 8), - CPU_TYPE_ENTRY(LS2045, LS2045, 4), - CPU_TYPE_ENTRY(LS1043, LS1043, 4), - CPU_TYPE_ENTRY(LS1023, LS1023, 2), - CPU_TYPE_ENTRY(LS2040, LS2040, 4), - CPU_TYPE_ENTRY(LS1012, LS1012, 1), + CPU_TYPE_ENTRY(LS2080A, LS2080A, 8), + CPU_TYPE_ENTRY(LS2085A, LS2085A, 8), + CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), + CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), + CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), + CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), }; #ifndef CONFIG_SYS_DCACHE_OFF diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 2cb6c54..39e8c7a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -41,13 +41,13 @@ struct cpu_type { { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)} #define SVR_WO_E 0xFFFFFE -#define SVR_LS1012 0x870400 -#define SVR_LS1043 0x879200 -#define SVR_LS1023 0x879208 -#define SVR_LS2045 0x870120 -#define SVR_LS2080 0x870110 -#define SVR_LS2085 0x870100 -#define SVR_LS2040 0x870130 +#define SVR_LS1012A 0x870400 +#define SVR_LS1043A 0x879200 +#define SVR_LS1023A 0x879208 +#define SVR_LS2045A 0x870120 +#define SVR_LS2080A 0x870110 +#define SVR_LS2085A 0x870100 +#define SVR_LS2040A 0x870130 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) diff --git a/drivers/usb/common/fsl-errata.c b/drivers/usb/common/fsl-errata.c index ebe60a8..183bf2b 100644 --- a/drivers/usb/common/fsl-errata.c +++ b/drivers/usb/common/fsl-errata.c @@ -182,8 +182,8 @@ bool has_erratum_a008751(void) switch (soc) { #ifdef CONFIG_ARM64 - case SVR_LS2080: - case SVR_LS2085: + case SVR_LS2080A: + case SVR_LS2085A: return IS_SVR_REV(svr, 1, 0); #endif } -- 1.9.1

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