June 2016 - U-Boot

[U-Boot] U-boot support for FIT image with 64 bit Linux Kernel
by vinoth eswaran 30 Jun '16

30 Jun '16

Hello, I am working on an embedded project with the u-boot and Minnowboard max. With compressed kernel (bzImage) everything works fine, I want to check the performance with uncompressed kernel (vmlinux). So for creating the image.fit file I followed the instructions as per the file x86-fit-boot.txt except that I have changed the compression to none in the image.its file since I want to check the uncompressed Kernel data = /incbin/("./vmlinux.bin"); type = "kernel"; arch = "x86"; os = "linux"; compression = "none"; The bootcmd is "bootcmd=fatload mmc 1:1 0x02000000 image.fit ; bootm 0x02000000". Now I am seeing that the start up hangs after printing the commands starting kernel ... and the time summary. Do you have any idea why it is happening? reading imagefit 14566018 bytes read in 317 ms (43.8 MiB/s) ## Loading kernel from FIT Image at 02000000 ... Using 'config@1' configuration Verifying Hash Integrity ... OK Trying 'kernel@1' kernel subimage Description: Vanilla Linux kernel Created: 2016-06-23 14:22:21 UTC Type: Kernel Image Compression: uncompressed Data Start: 0x020000e8 Data Size: 14548992 Bytes = 13.9 MiB Architecture: Intel x86 OS: Linux Load Address: 0x01000000 Entry Point: 0x00000000 Hash algo: sha1 Hash value: 5a0bddcbf1f54ac989fff662fc43fb5fc801ebbc Verifying Hash Integrity ... sha1+ OK ## Loading setup from FIT Image at 02000000 ... Using 'config@1' configuration Trying 'setup@1' setup subimage Description: Linux setup.bin Created: 2016-06-23 14:22:21 UTC Type: x86 setup.bin Compression: uncompressed Data Start: 0x02de01d0 Data Size: 15708 Bytes = 15.3 KiB Hash algo: sha1 Hash value: 08ffa163d054b9b0f5b11d4b3db2a16247cee395 Verifying Hash Integrity ... sha1+ OK Loading setup from 0x02de01d0 to 0x00090000 Loading Kernel Image ... OK Setup at 0x090000 Magic signature found Kernel command line: "quiet" Starting kernel ... I have seen in the document that it doesn't support for 64 bit kernel and the document link given is now not accessible. http://wiki.osdev.org/64-bit_Higher_Half_Kernel_with_GRUB_2 Mit Freundlichen Grüßen VinothKumar +49 1798909072

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[U-Boot] [PATCH v4] mtd: fix compiler warnings
by Steve Rae 29 Jun '16

29 Jun '16

- add missing declaration - update debug output format specifiers Signed-off-by: Steve Rae <steve.rae(a)raedomain.com> --- the checkpatch warning: warning: cmd/mtdparts.c,1494: quoted string split across lines is for the existing code; it is not introduced with this change... Changes in v4: pulled this change out of the "iproc" series, as it had nothing to do with "iproc" Changes in v3: none Changes in v2: none cmd/mtdparts.c | 4 ++-- include/linux/mtd/mtd.h | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index 44b2c3a..ea97415 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -1491,7 +1491,7 @@ static int spread_partitions(void) part = list_entry(pentry, struct part_info, link); debug("spread_partitions: device = %s%d, partition %d =" - " (%s) 0x%08x@0x%08x\n", + " (%s) 0x%08llx@0x%08llx\n", MTD_DEV_TYPE(dev->id->type), dev->id->num, part_num, part->name, part->size, part->offset); @@ -2009,7 +2009,7 @@ static int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, if (!strcmp(&argv[1][3], ".spread")) { spread_partition(mtd, p, &next_offset); - debug("increased %s to %d bytes\n", p->name, p->size); + debug("increased %s to %llu bytes\n", p->name, p->size); } #endif diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index cf20674..779eea0 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -500,5 +500,10 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, loff_t *size, loff_t *maxsize, int devtype, uint64_t chipsize); + +/* drivers/mtd/mtdcore.c */ +void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset, + const uint64_t length, uint64_t *len_incl_bad, + int *truncated); #endif #endif /* __MTD_MTD_H__ */ -- 1.8.5

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[U-Boot] [RFC PATCH v3 1/4] arm: iproc: add NAND driver
by Steve Rae 29 Jun '16

29 Jun '16

From: Jiandong Zheng <jdzheng(a)broadcom.com> Add support for the iproc NAND, and enable on Cygnus and NSP boards. Signed-off-by: Jiandong Zheng <jdzheng(a)broadcom.com> Signed-off-by: Steve Rae <srae(a)broadcom.com> --- There was a previous attempt to implement this "iproc NAND" (see: http://patchwork.ozlabs.org/patch/505399), however, due to the amount of changes required, it seemed better to implement the code in a series of steps. This is the first step, where the "iproc_nand.c" is essentially an empty file (with one function required to allow this commit to build successfully). RFC only - more changes are coming for "drivers/mtd/nand/iproc_nand.c" Changes in v3: - convert more CONFIG_* to Kconfig Changes in v2: - convert some CONFIG_* to Kconfig arch/arm/include/asm/arch-bcmcygnus/configs.h | 2 - arch/arm/include/asm/arch-bcmnsp/configs.h | 2 - board/broadcom/bcmcygnus/Kconfig | 33 ++++++++ board/broadcom/bcmnsp/Kconfig | 33 ++++++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/iproc_nand.c | 19 +++++ drivers/mtd/nand/iproc_nand_cygnus.h | 111 +++++++++++++++++++++++++ drivers/mtd/nand/iproc_nand_ns_plus.h | 113 ++++++++++++++++++++++++++ 8 files changed, 310 insertions(+), 4 deletions(-) create mode 100644 drivers/mtd/nand/iproc_nand.c create mode 100644 drivers/mtd/nand/iproc_nand_cygnus.h create mode 100644 drivers/mtd/nand/iproc_nand_ns_plus.h diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 3c07160..2c75cb9 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -9,8 +9,6 @@ #include <asm/iproc-common/configs.h> -/* uArchitecture specifics */ - /* Serial Info */ /* Post pad 3 bytes after each reg addr */ #define CONFIG_SYS_NS16550_REG_SIZE (-4) diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 786deae..d170e16 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -9,8 +9,6 @@ #include <asm/iproc-common/configs.h> -/* uArchitecture specifics */ - /* Serial Info */ /* no padding */ #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/board/broadcom/bcmcygnus/Kconfig b/board/broadcom/bcmcygnus/Kconfig index faba4cf..6554cdf 100644 --- a/board/broadcom/bcmcygnus/Kconfig +++ b/board/broadcom/bcmcygnus/Kconfig @@ -12,4 +12,37 @@ config SYS_SOC config SYS_CONFIG_NAME default "bcm_ep_board" +config SYS_BCM_CYGNUS + bool + default y + select CMD_NAND + select SYS_NAND_SELF_INIT + +config NAND_IPROC + bool + default y + +# +# NAND configuration +# +config SYS_NAND_IPROC_TIMING_MODE + int + default 5 + +config SYS_NAND_BASE + int + default 0 + +config SYS_MAX_NAND_DEVICE + int + default 1 + +config SYS_MAX_NAND_CHIPS + int + default 1 + +config SYS_NAND_ONFI_DETECTION + bool + default y + endif diff --git a/board/broadcom/bcmnsp/Kconfig b/board/broadcom/bcmnsp/Kconfig index a975082..f420e28 100644 --- a/board/broadcom/bcmnsp/Kconfig +++ b/board/broadcom/bcmnsp/Kconfig @@ -12,4 +12,37 @@ config SYS_SOC config SYS_CONFIG_NAME default "bcm_ep_board" +config SYS_BCM_NSPLUS + bool + default y + select CMD_NAND + select SYS_NAND_SELF_INIT + +config NAND_IPROC + bool + default y + +# +# NAND configuration +# +config SYS_NAND_IPROC_TIMING_MODE + int + default 5 + +config SYS_NAND_BASE + int + default 0 + +config SYS_MAX_NAND_DEVICE + int + default 1 + +config SYS_MAX_NAND_CHIPS + int + default 1 + +config SYS_NAND_ONFI_DETECTION + bool + default y + endif diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 6fb3718..bb3adbc 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o +obj-$(CONFIG_NAND_IPROC) += iproc_nand.o obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o diff --git a/drivers/mtd/nand/iproc_nand.c b/drivers/mtd/nand/iproc_nand.c new file mode 100644 index 0000000..691b8d8 --- /dev/null +++ b/drivers/mtd/nand/iproc_nand.c @@ -0,0 +1,19 @@ +/* + * Copyright 2015 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#if defined(CONFIG_SYS_BCM_CYGNUS) +#include "iproc_nand_cygnus.h" +#elif defined(CONFIG_SYS_BCM_NSPLUS) +#include "iproc_nand_ns_plus.h" +#else +#error "Unsupported configuration" +#endif + +void board_nand_init(void) +{ +} diff --git a/drivers/mtd/nand/iproc_nand_cygnus.h b/drivers/mtd/nand/iproc_nand_cygnus.h new file mode 100644 index 0000000..26a00a9 --- /dev/null +++ b/drivers/mtd/nand/iproc_nand_cygnus.h @@ -0,0 +1,111 @@ +/* + * Copyright 2015 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IPROC_NAND_CYGNUS_H_ +#define _IPROC_NAND_CYGNUS_H_ + +/* + * SoC specific definitions (Cygnus) + */ + +#define REG_NAND_BASE 0x18046000 +#define REG_NAND_IDM_BASE 0xf8105000 + +#define NAND_STRAP_TYPE_MASK 0x000f0000 +#define NAND_STRAP_TYPE_SHIFT 16 +#define NAND_STRAP_PAGE_MASK 0x00300000 +#define NAND_STRAP_PAGE_SHIFT 20 +#define NAND_STRAP_WIDTH_MASK 0x01000000 +#define NAND_STRAP_WIDTH_SHIFT 24 + +#define NAND_STRAP_TYPE_DATA \ +/* sector_1k, ecclevel, spare_size */ \ +{ \ + { 0, 0, 16 }, \ + { 0, 1, 16 }, \ + { 0, 4, 16 }, \ + { 0, 8, 16 }, \ + { 0, 8, 27 }, \ + { 0, 12, 27 }, \ + { 1, 12, 27 }, \ + { 1, 15, 27 }, \ + { 1, 20, 45 } \ +} + +#define NAND_STRAP_PAGE_DATA \ +{ \ + 1024, 2048, 4096, 8192 \ +} + +/* + * iProc NAND timing configurations for ONFI timing modes [0-5] + * + * Clock tick = 10ns + * Multiplier: + * x1: tWP tWH tRP tREH tCLH tALH + * x2: tCS tADL tWB tWHR + */ +#define NAND_TIMING_DATA \ +{ \ + /* ONFI timing mode 0 : */ \ + /* tWC=100ns tWP=50ns tWH=30ns */ \ + /* tRC=100ns tRP=50ns tREH=30ns */ \ + /* tCS=70ns tCLH=20ns tALH=20ns tADL=200ns */ \ + /* tWB=200ns tWHR=120ns tREA=40ns */ \ + { \ + .timing1 = 0x6565435b, \ + .timing2 = 0x00001e85, \ + }, \ + /* ONFI timing mode 1 : */ \ + /* tWC=45 tWP=25ns tWH=15ns */ \ + /* tRC=50 tRP=25ns tREH=15ns */ \ + /* tCS=35ns tCLH=10ns tALH=10ns tADL=100ns */ \ + /* tWB=100ns tWHR=80ns tREA=30ns */ \ + { \ + .timing1 = 0x33333236, \ + .timing2 = 0x00001064, \ + }, \ + /* ONFI timing mode 2 : */ \ + /* tWC=35ns tWP=17ns tWH=15ns */ \ + /* tRC=35ns tRP=17ns tREH=15ns */ \ + /* tCS=25ns tCLH=10ns tALH=10ns tADL=100ns */ \ + /* tWB=100ns tWHR=80ns tREA=25ns */ \ + { \ + .timing1 = 0x32322226, \ + .timing2 = 0x00001063, \ + }, \ + /* ONFI timing mode 3 : */ \ + /* tWC=30ns tWP=15ns tWH=10ns */ \ + /* tRC=30ns tRP=15ns tREH=10ns */ \ + /* tCS=25ns tCLH=5ns tALH=5ns tADL=100ns */ \ + /* tWB=100ns tWHR=60ns tREA=20ns */ \ + { \ + .timing1 = 0x22222126, \ + .timing2 = 0x00001043, \ + }, \ + /* ONFI timing mode 4 : */ \ + /* tWC=25ns tWP=12ns tWH=10ns */ \ + /* tRC=25ns tRP=12ns tREH=10ns */ \ + /* tCS=20ns tCLH=5ns tALH=5ns tADL=70ns */ \ + /* tWB=100ns tWHR=60ns tREA=20ns */ \ + { \ + .timing1 = 0x21212114, \ + .timing2 = 0x00001042, \ + }, \ + /* ONFI timing mode 5 : */ \ + /* tWC=20ns tWP=10ns tWH=7ns */ \ + /* tRC=20ns tRP=10ns tREH=7ns */ \ + /* tCS=15ns tCLH=5ns tALH=5ns tADL=70ns */ \ + /* tWB=100ns tWHR=60ns tREA=16ns */ \ + { \ + .timing1 = 0x11111114, \ + .timing2 = 0x00001042, \ + }, \ +} + +#define NAND_MAX_CS 2 + +#endif /* _IPROC_NAND_CYGNUS_H_ */ diff --git a/drivers/mtd/nand/iproc_nand_ns_plus.h b/drivers/mtd/nand/iproc_nand_ns_plus.h new file mode 100644 index 0000000..41d5da7 --- /dev/null +++ b/drivers/mtd/nand/iproc_nand_ns_plus.h @@ -0,0 +1,113 @@ +/* + * Copyright 2015 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IPROC_NAND_NS_PLUS_H_ +#define _IPROC_NAND_NS_PLUS_H_ + +/* + * SoC specific definitions (NorthStar Plus) + */ + +#define REG_NAND_BASE 0x18026000 +#define REG_NAND_IDM_BASE 0x1811b000 +#define REG_NAND_STRAPS_BASE 0x1803f2a0 + +#define NAND_STRAP_TYPE_MASK 0x0000f000 +#define NAND_STRAP_TYPE_SHIFT 12 +#define NAND_STRAP_PAGE_MASK 0x00000c00 +#define NAND_STRAP_PAGE_SHIFT 10 +/* No bus width strap */ +#define NAND_STRAP_WIDTH_MASK 0x0 +#define NAND_STRAP_WIDTH_SHIFT 0 + +#define NAND_STRAP_TYPE_DATA \ +/* sector_1k, ecclevel, spare_size */ \ +{ \ + { 0, 0, 16 }, \ + { 0, 15, 16 }, /* Hamming ECC */ \ + { 0, 4, 16 }, \ + { 0, 8, 16 }, \ + { 0, 8, 27 }, \ + { 0, 12, 27 }, \ + { 1, 12, 27 }, \ + { 1, 15, 27 }, \ + { 1, 20, 45 } \ +} + +#define NAND_STRAP_PAGE_DATA \ +{ \ + 2048, 2048, 4096, 8192 \ +} + +/* + * iProc NAND timing configurations for ONFI timing modes [0-5] + * + * Clock tick = 4ns + * Multiplier: + * x1: tWP tWH tRP tREH tCLH tALH + * x4: tCS tADL tWB tWHR + */ +#define NAND_TIMING_DATA \ +{ \ + /* ONFI timing mode 0 : */ \ + /* tWC=100ns tWP=50ns tWH=30ns */ \ + /* tRC=100ns tRP=50ns tREH=30ns */ \ + /* tCS=70ns tCLH=20ns tALH=20ns tADL=200ns */ \ + /* tWB=200ns tWHR=120ns tREA=40ns */ \ + { \ + .timing1 = 0xfafa558d, \ + .timing2 = 0x00001a85, \ + }, \ + /* ONFI timing mode 1 : */ \ + /* tWC=45 tWP=25ns tWH=15ns */ \ + /* tRC=50 tRP=25ns tREH=15ns */ \ + /* tCS=35ns tCLH=10ns tALH=10ns tADL=100ns */ \ + /* tWB=100ns tWHR=80ns tREA=30ns */ \ + { \ + .timing1 = 0x85853347, \ + .timing2 = 0x00000e64, \ + }, \ + /* ONFI timing mode 2 : */ \ + /* tWC=35ns tWP=17ns tWH=15ns */ \ + /* tRC=35ns tRP=17ns tREH=15ns */ \ + /* tCS=25ns tCLH=10ns tALH=10ns tADL=100ns */ \ + /* tWB=100ns tWHR=80ns tREA=25ns */ \ + { \ + .timing1 = 0x54542347, \ + .timing2 = 0x00000e63, \ + }, \ + /* ONFI timing mode 3 : */ \ + /* tWC=30ns tWP=15ns tWH=10ns */ \ + /* tRC=30ns tRP=15ns tREH=10ns */ \ + /* tCS=25ns tCLH=5ns tALH=5ns tADL=100ns */ \ + /* tWB=100ns tWHR=60ns tREA=20ns */ \ + { \ + .timing1 = 0x44442237, \ + .timing2 = 0x00000e43, \ + }, \ + /* ONFI timing mode 4 : */ \ + /* tWC=25ns tWP=12ns tWH=10ns */ \ + /* tRC=25ns tRP=12ns tREH=10ns */ \ + /* tCS=20ns tCLH=5ns tALH=5ns tADL=70ns */ \ + /* tWB=100ns tWHR=60ns tREA=20ns */ \ + { \ + .timing1 = 0x43432235, \ + .timing2 = 0x00000e42, \ + }, \ + /* ONFI timing mode 5 : */ \ + /* tWC=20ns tWP=10ns tWH=7ns */ \ + /* tRC=20ns tRP=10ns tREH=7ns */ \ + /* tCS=15ns tCLH=5ns tALH=5ns tADL=70ns */ \ + /* tWB=100ns tWHR=60ns tREA=16ns */ \ + { \ + .timing1 = 0x32321225, \ + .timing2 = 0x00000e42, \ + }, \ +} + +#define NAND_MAX_CS 1 + +#endif /* _IPROC_NAND_NS_PLUS_H_ */ -- 1.8.5

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[U-Boot] [PATCH] arm: mmc: increase MMC SDHCI read status timeout
by Steve Rae 29 Jun '16

29 Jun '16

Otherwise, ocassionally see errors like this: Flashing sparse image at offset 2078720 Flashing Sparse Image sdhci_send_command: Timeout for status update! mmc fail to send stop cmd write_sparse_image: Write failed, block #2181088 [0] This does not affect the actual writing speed, which is controlled by the default value: CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT It only increases the retries when reading: SDHCI_INT_STATUS to avoid the timeout error. Signed-off-by: Steve Rae <steve.rae(a)raedomain.com> --- as per the discussion in: http://lists.denx.de/pipermail/u-boot/2016-June/258966.html this supercedes: http://patchwork.ozlabs.org/patch/615994/ drivers/mmc/sdhci.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 5c71ab8..aa4cd4f 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -127,6 +127,7 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200 #endif #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 +#define CONFIG_SDHCI_READ_STATUS_TIMEOUT 1000 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) @@ -243,9 +244,9 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (stat & SDHCI_INT_ERROR) break; } while (((stat & mask) != mask) && - (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT)); + (get_timer(start) < CONFIG_SDHCI_READ_STATUS_TIMEOUT)); - if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) { + if (get_timer(start) >= CONFIG_SDHCI_READ_STATUS_TIMEOUT) { if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) return 0; else { -- 1.8.5

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[U-Boot] [PATCH v5] mmc: atmel_sdhci: Convert to the driver model support
by Wenyou Yang 29 Jun '16

29 Jun '16

Convert the driver to the driver model while retaining the existing legacy code. This allows the driver to support boards that have converted to driver model as well as those that have not. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v5: - Add Reviewed-by tag. Changes in v4: - Update the clk API based on [PATCH] clk: convert API to match reset/mailbox fstyle (http://patchwork.ozlabs.org/patch/625342/). - Remove check on dev_get_parent() return. - Fixed the return value, such as -ENODEV->-EINVAL. Changes in v3: - Remove the redundant log print. Changes in v2: - Add clock support, include enabling peripheral clock and generated clock. - Retain the existing legacy code to support boards which have not converted to driver model. drivers/mmc/Kconfig | 10 +++++ drivers/mmc/atmel_sdhci.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c80efc3..518c624 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -25,6 +25,16 @@ config MSM_SDHCI SD 3.0 specifications. Both SD and eMMC devices are supported. Card-detect gpios are not supported. +config ATMEL_SDHCI + bool "Atmel SDHCI controller support" + depends on DM_MMC && ARCH_AT91 + help + This enables support for the Atmel SDHCI controller, which supports + the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD + Memory Card Specification V3.0, and the SDIO V3.0 specification. + It is compliant with the SD Host Controller Standard V3.0 + specification. + config ROCKCHIP_DWMMC bool "Rockchip SD/MMC controller support" depends on DM_MMC && OF_CONTROL diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index 24b68b6..a68d192 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -6,12 +6,16 @@ */ #include <common.h> +#include <clk_client.h> +#include <dm.h> #include <malloc.h> #include <sdhci.h> #include <asm/arch/clk.h> #define ATMEL_SDHC_MIN_FREQ 400000 +#ifndef CONFIG_DM_MMC + int atmel_sdhci_init(void *regbase, u32 id) { struct sdhci_host *host; @@ -38,3 +42,98 @@ int atmel_sdhci_init(void *regbase, u32 id) return 0; } + +#else + +DECLARE_GLOBAL_DATA_PTR; + +static int atmel_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct sdhci_host *host = dev_get_priv(dev); + u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; + u32 caps0, caps1; + u32 clk_base, clk_mul; + u32 gck_rate; + struct udevice *dev_clk; + struct clk clk; + int periph, ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_enable(&clk); + if (ret) + return ret; + + host->name = (char *)dev->name; + host->ioaddr = (void *)dev_get_addr(dev); + + host->quirks = 0; + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + + host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); + + caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); + caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); + clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; + clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; + gck_rate = clk_base * 1000000 * (clk_mul + 1); + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return ret; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_set_rate(&clk, gck_rate); + if (ret) + return ret; + + max_clk = clk_get_rate(&clk); + if (!max_clk) + return -EINVAL; + + add_sdhci(host, max_clk, min_clk); + + upriv->mmc = host->mmc; + + clk_free(&clk); + + return 0; +} + +static const struct udevice_id atmel_sdhci_ids[] = { + { .compatible = "atmel,sama5d2-sdhci" }, + { } +}; + +U_BOOT_DRIVER(atmel_sdhci_drv) = { + .name = "atmel_sdhci", + .id = UCLASS_MMC, + .of_match = atmel_sdhci_ids, + .probe = atmel_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct sdhci_host), +}; + +#endif -- 2.7.4

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[U-Boot] [RFC PATCH v1] usb: spl: fix USB errata for FSL SPL targets
by York Sun 29 Jun '16

29 Jun '16

Commit 9262367 moved USB errata workaround to a C file but didn't build it for SPL targets. Signed-off-by: York Sun <york.sun(a)nxp.com> CC: Sriram Dash <sriram.dash(a)nxp.com> CC: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> --- Please review this patch. It fixed the compiling errors introduced by 9262367. Not sure if this is the way USB errata should be handled. drivers/Makefile | 7 +++++++ drivers/usb/common/Makefile | 8 ++++++-- include/configs/km/kmp204x-common.h | 1 + 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 1723958..88774ba 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -39,6 +39,13 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += block/ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/ obj-$(CONFIG_SPL_MMC_SUPPORT) += block/ +ifdef CONFIG_USB_EHCI_FSL +CONFIG_SPL_USB_ERRATA = y +endif +ifdef CONFIG_USB_XHCI_FSL +CONFIG_SPL_USB_ERRATA = y +endif +obj-$(CONFIG_SPL_USB_ERRATA) += usb/common/ else diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile index aee7e32..f073e1c 100644 --- a/drivers/usb/common/Makefile +++ b/drivers/usb/common/Makefile @@ -4,5 +4,9 @@ # obj-$(CONFIG_DM_USB) += common.o -obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o fsl-errata.o -obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o fsl-errata.o +obj-$(CONFIG_USB_EHCI_FSL) += fsl-errata.o +obj-$(CONFIG_USB_XHCI_FSL) += fsl-errata.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o +obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o +endif diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 028623d..5bdda22 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -406,6 +406,7 @@ int get_scl(void); #endif #define __USB_PHY_TYPE utmi +#define CONFIG_USB_EHCI_FSL /* * Environment Configuration -- 2.7.4

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[U-Boot] [PATCH 1/2] usbarmory: switch to using kernel zImage
by andrej＠inversepath.com 29 Jun '16

29 Jun '16

From: Andrej Rosano <andrej(a)inversepath.com> Switch to using zImage instead of uImage. Signed-off-by: Andrej Rosano <andrej(a)inversepath.com> --- include/configs/usbarmory.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 8568663..c0e093f 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -69,17 +69,19 @@ #define CONFIG_CMD_FUSE #define CONFIG_FSL_IIM -/* Linux boot */ +/* U-Boot memory offsets */ #define CONFIG_LOADADDR 0x72000000 #define CONFIG_SYS_TEXT_BASE 0x77800000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Linux boot */ #define CONFIG_HOSTNAME usbarmory #define CONFIG_BOOTCOMMAND \ "run distro_bootcmd; " \ "setenv bootargs console=${console} ${bootargs_default}; " \ - "ext2load mmc 0:1 ${kernel_addr_r} /boot/uImage; " \ + "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \ "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}" + "bootz ${kernel_addr_r} - ${fdt_addr_r}" #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) -- 2.9.0

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[U-Boot] u-boot on NAND sunxi
by Irvin Probst 29 Jun '16

29 Jun '16

Hi, I've been playing a bit with a pcduino3 board (A20), I know mainline u-boot has no R/W support on NAND for these boards and that's not what I'm asking for :-) I've noticed that when I use an sdcard, u-boot+spl initializes the framebuffer and the screen goes on, whereas when I put u-boot.bin (without spl then) on the NAND the screen stays blank. Is there some magic done in the uboot's SPL that the defaut Allwinner's boot0/1 does not do ? The environment variables and uboot's output are identical in both boot processes: U-Boot 2016.03-dirty (Jun 28 2016 - 10:59:14 +0200) Allwinner Technology [...] HDMI connected: Setting up a 1280x1024 hdmi console (overscan 0x0) In: serial Out: vga Err: vga [...] The only difference is that the screen stays blank when uboot is read from the NAND by boot1. In this configuration booting linux (zImage+dtb read from a sdcard) afterwards does not bring the screen on either. Any idea on what's going on ? Thanks.

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[U-Boot] Problem loading boot script from ext4 mmc on sunxi H3
by Michal Suchanek 29 Jun '16

29 Jun '16

Hello, I tried loading system with recent u-boot but it does not work. Trying some ext4ls shows there is some problem accessing the filesystem. Not sure if this should be attributed to the ext driver or to the mmc driver or something else entirely. Does this work for anybody? Any debug option to turn on? Thanks Michal U-Boot SPL 2016.07-rc2-00071-gc4ba89e (Jun 28 2016 - 16:53:32) DRAM: u MiB Trying to boot from MMC1 U-Boot 2016.07-rc2-00071-gc4ba89e (Jun 28 2016 - 16:53:32 +0200) Allwinner Technology CPU: Allwinner H3 (SUN8I 1680) Model: Xunlong Orange Pi One DRAM: 512 MiB MMC: SUNXI SD/MMC: 0 In: serial Out: serial Err: serial Net: No ethernet found. starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 scanning bus 0 for devices... 1 USB Device(s) found Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0 is current device Scanning mmc 0:1... USB device 0: unknown device No ethernet found. missing environment variable: pxeuuid missing environment variable: bootfile Retrieving file: pxelinux.cfg/00000000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/0000000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/000000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/00000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/0000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/000 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/00 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/0 No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default-arm-sunxi No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default-arm No ethernet found. missing environment variable: bootfile Retrieving file: pxelinux.cfg/default No ethernet found. Config file not found No ethernet found. No ethernet found. => ext4ls mmc 0:1 boot => ext4ls mmc 0:1 opt < ? > 0 nux/drivers/mmc/core/sdio_cis.h * * Author: Nicolas Pitre * Created: June 11, 2007 * Copyright: MontaVis => ext4ls mmc 0:1 var => ext4ls mmc 0:1 <DIR> 4096 . <DIR> 4096 .. <DIR> 16384 lost+found <DIR> 4096 scripts <DIR> 4096 tmp <DIR> 4096 scratch <DIR> 4842 debug <DIR> 18704 lib <DIR> 0 run <DIR> 0 etc 0 Makefile <DIR> 0 home <DIR> 0 media 0 config-4.4.0-rc5-00131-gce3f5ce-dirty <DIR> 0 boot <DIR> 0 srv <DIR> 0 dev <DIR> 0 proc <DIR> 0 bin <DIR> 0 mnt <DIR> 0 sys <DIR> 0 include <SYM> 98629 source <DIR> 0 var <DIR> 0 sbin <DIR> 0 root <DIR> 0 usr <DIR> 647 opt

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[U-Boot] socfpga 2016.05, CV socdk Rev E1, SPL and u-boot fail when booting from QSPI
by Christian Didriksson 29 Jun '16

29 Jun '16

Hi All, I have been struggling for quite some time now to get SPL and u-boot to run from QSPI-flash. Yesterday I was able to identify a workaround to get the SPL going by disabling quad mode for the flash (seems identified by http://lists.denx.de/pipermail/u-boot/2016-June/256671.html). However u-boot always hangs after printing memory size. I have tried to search the archive and have seen posts about hanging here, but nothing I can relate to my setup. I have tested to use Altera's SPL (2013.01.01) and u-boot-2016.5 and this combo seems to work. I also notice that the frequency (max-spi-frequency) in the dts-file is not picked up for some reason? Any help to fix the u-boot hang problem would be highly appreciated. Current printout (with added debug output): U-Boot SPL 2016.05 NGA QSPI -g133f59a-dirty (Jun 09 2016 - 17:06:20) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from SPI spl_spi_load_image: bus=0, cs=0, speed=50000000, mode=3 cadence_spi_ofdata_to_platdata: regbase=ff705000 ahbbase=ffa00000 max-frequency=500000 page-size=256 spi_flash_std_probe: slave=01100368, cs=0 SF: Read data capture delay calibrated to 7 (0 - 15) cadence_spi_set_speed: speed=100000 cadence_spi_xfer: len=1 [bytes] cadence_spi_xfer: len=5 [bytes] SF: Got idcodes 00000000: 20 ba 20 10 00 . .. SF: Detected N25Q512 cadence_spi_xfer: len=1 [bytes] cadence_spi_xfer: len=1 [bytes] spi_flash_decode_fdt: Cannot decode address cadence_spi_xfer: len=0 [bytes] cadence_spi_xfer: len=0 [bytes] SF: Detected N25Q512 with page size 256 Bytes, erase size 64 KiB, total 64 MiB SF: Read data capture delay calibrated to 7 (0 - 15) cadence_spi_set_speed: speed=500000 cadence_spi_xfer: len=5 [bytes] cadence_spi_xfer: len=64 [bytes] cadence_spi_xfer: len=5 [bytes] cadence_spi_xfer: len=443714 [bytes] U-Boot 2016.05 NGA QSPI -g133f59a-dirty (Jun 09 2016 - 17:06:20 +0200) CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: QSPI Flash (1.8V) Watchdog enabled I2C: ready DRAM: 1 GiB Best regards, Christian

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