May 2016 - U-Boot

[U-Boot] [PATCH 0/2] armv8: Support loading 32-bit OS in AArch32 execution state
by Alison Wang 17 May '16

17 May '16

This series is to support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. This series is tested on LS1043ARDB board. ---------------------------------------------------------------- Alison Wang (2): armv8: Support loading 32-bit OS in AArch32 execution state armv8: fsl-layerscape: SMP support for loading 32-bit OS arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 21 +++++++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 +++++++++ arch/arm/cpu/armv8/transition.S | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++++++ arch/arm/include/asm/system.h | 2 ++ arch/arm/lib/bootm.c | 25 +++++++++++++++++++++-- common/image-fit.c | 12 ++++++++++- 7 files changed, 173 insertions(+), 3 deletions(-)

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[U-Boot] Remove sh2, sh3, sh4 architecture?
by Simon Glass 17 May '16

17 May '16

Hi, It looks like these have no maintainer and have not been converted to generic board. Should we remove the 'sh' architecture? Regards, Simon

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[U-Boot] [PATCH] ARM64: zynqmp: Align gic ranges for 64k in device tree
by Michal Simek 17 May '16

17 May '16

From: Alexander Graf <agraf(a)suse.de> The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf <agraf(a)suse.de> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index e724e59e830d..619450e1ba92 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -253,9 +253,9 @@ compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf902f000 0x2000>, + <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, - <0x0 0xf906f000 0x2000>; + <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; -- 1.9.1

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[U-Boot] [PATCH 5/8] sun8i: Display silicon revision of A83t processors
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- arch/arm/mach-sunxi/cpu_info.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 76b6719..d552061 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -50,6 +50,17 @@ uint sunxi_get_sram_id(void) return id; } + +uint sunxi_get_revision(void) +{ + uint rev; + + /* Unlock sram info reg, read it, relock */ + rev = readl(SUNXI_SRAMC_BASE + 0x24) & 0x1; + + return rev; +} + #endif #ifdef CONFIG_DISPLAY_CPUINFO @@ -84,7 +95,7 @@ int print_cpuinfo(void) #elif defined CONFIG_MACH_SUN8I_A33 printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_A83T - printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id()); + printf("CPU: Allwinner A83T (SUN8I %04x rev. %s)\n", sunxi_get_sram_id(), (sunxi_get_revision() == 0)?"A":"B"); #elif defined CONFIG_MACH_SUN8I_H3 printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN9I -- 2.8.0.rc3

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[U-Boot] [PATCH 2/8] sun8i: Add CCI-400 definitions
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 65c0441..76da00f 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -18,6 +18,9 @@ #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ +#define SUN8I_CPUXCFG_BASE 0x01700000 +#define SUN8I_CCI400_BASE 0x01790000 + #define SUNXI_SRAMC_BASE 0x01c00000 #define SUNXI_DRAMC_BASE 0x01c01000 #define SUNXI_DMA_BASE 0x01c02000 @@ -168,6 +171,10 @@ #define SUNXI_SS_BOND_ID_A31 4 #define SUNXI_SS_BOND_ID_A31S 5 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 + #ifndef __ASSEMBLY__ void sunxi_board_init(void); void sunxi_reset(void); -- 2.8.0.rc3

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[U-Boot] [Patch v2] fsl-layerscape: fdt: add IFC fixup if no IFC is avaliable in U-Boot
by Gong Qianyu 17 May '16

17 May '16

IFC is considered as a required component in Layerscape platforms' Linux. But if IFC is not enabled in U-Boot on some boards, accessing IFC memory space would cause kernel call trace. So disable IFC node in such cases. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- V2: - Revised the title and message. - Used #ifndef CONFIG_FSL_IFC rather than #ifdef CONFIG_FSL_QSPI. arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 1e875c4..96dab56 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -98,4 +98,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif + +#ifndef CONFIG_FSL_IFC + do_fixup_by_compat(blob, "fsl,ifc", + "status", "disabled", 8 + 1, 1); +#endif } -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 8/8] a83t: Enable PSCI, non-secure mode, and cluster / cache setup
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- board/sunxi/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index fa78720..4b82d3d 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -85,8 +85,13 @@ config MACH_SUN50I config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ENABLE_CLUSTER_1 + select ENABLE_CCI400_SNOOP_CLUSTERS_0_1 + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN9I bool "sun9i (Allwinner A80)" @@ -623,4 +628,12 @@ config SPL_STACK_R_ADDR default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I default 0x2fe00000 if MACH_SUN9I +config ENABLE_CLUSTER_1 + bool + default n + +config ENABLE_CCI400_SNOOP_CLUSTERS_0_1 + bool + default n + endif -- 2.8.0.rc3

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[U-Boot] [PATCH 7/8] sun8i: Enable PSCI cpu_on support for A83t
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 174 ++++++++++++++++++++++++++++++++-- 1 file changed, 164 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index d35b63e..b3090ec 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -21,6 +21,7 @@ #include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> +#include <linux/linkage.h> #include <asm/macro.h> #include <asm/psci.h> #include <asm/arch/cpu.h> @@ -45,6 +46,16 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 +@ Attempts to condense sparse ID space on multi-cluster systems to dense ID space +ENTRY(psci_get_cpu_id) + mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */ + lsr r1, r0, #6 /* extract cluster offset */ + and r1, r1, #0xff + and r0, r0, #0xff /* extract CPU ID in cluster */ + add r0, r0, r1 /* return adjusted CPU ID */ + bx lr +ENDPROC(psci_get_cpu_id) + .globl psci_fiq_enter psci_fiq_enter: push {r0-r12} @@ -106,7 +117,7 @@ psci_fiq_enter: str r10, [r8, #0x100] timer_wait r10, ONE_MS -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN8I_A83T) @ Activate power clamp lsl r12, r9, #2 @ x4 add r12, r12, r8 @@ -134,7 +145,13 @@ out: mcr p15, 0, r7, c1, c1, 0 psci_cpu_on: push {lr} - mov r0, r1 +#if defined(CONFIG_MACH_SUN8I_A83T) + lsr r3, r1, #6 @ extract cluster offset + and r0, r1, #3 @ extract CPU number + add r0, r0, r3 @ pass adjusted CPU number to setup +#else + mov r0, r1 @ pass CPU number to setup +#endif bl psci_get_cpu_stack_top @ get stack top of target CPU str r2, [r0] @ store target PC at stack top dsb @@ -142,15 +159,74 @@ psci_cpu_on: movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) movt r0, #(SUN6I_CPUCFG_BASE >> 16) + ldr r6, =psci_cpu_entry + str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) + @ CPU mask +#if defined(CONFIG_MACH_SUN8I_A83T) + lsr r3, r1, #8 @ extract cluster number + and r1, r1, #3 @ extract CPU number + + @ obtain silicon revision level + movw r0, #(SUNXI_SRAMC_BASE & 0xffff) + movt r0, #(SUNXI_SRAMC_BASE >> 16) + ldr r2, [r0, #0x24] + and r2, r2, #0x1 +#else + ldr r3, #0 @ only one cluster and r1, r1, #3 @ only care about first cluster + ldr r2, #0 @ default revision +#endif mov r4, #1 lsl r4, r4, r1 - ldr r6, =psci_cpu_entry - str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) - @ Assert reset on target CPU +#if defined(CONFIG_MACH_SUN8I_A83T) + movw r0, #(SUN8I_CPUXCFG_BASE & 0xffff) + movt r0, #(SUN8I_CPUXCFG_BASE >> 16) + + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x80 @ SUNXI_CPU_RST_CTRL + ldr r6, [r0, r5] + bic r6, r6, r4 @ assert reset + str r6, [r0, r5] + + cmp r1, #0 + bne skip_cluster_reset_assert + + lsl r5, r3, #4 @ cluster offset + add r5, r5, #0x04 @ SUNXI_CLUSTER_CTRL1 + ldr r6, [r0, r5] + orr r6, r6, #0x1 @ assert ACINACTM + str r6, [r0, r5] + + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x80 @ SUNXI_CPU_RST_CTRL + ldr r6, [r0, r5] + bic r6, r6, #0x1000 @ assert HRESET + bic r6, r6, #0x100 @ assert L2 cache reset + str r6, [r0, r5] +skip_cluster_reset_assert: + + @ re-calculate CPU control register address + movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) + movt r0, #(SUN6I_CPUCFG_BASE >> 16) + + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x30 @ SUNXI_CLUSTER_PWRON_RESET + ldr r6, [r0, r5] + bic r6, r6, r4 @ assert reset + str r6, [r0, r5] + + movw r0, #(SUN8I_CPUXCFG_BASE & 0xffff) + movt r0, #(SUN8I_CPUXCFG_BASE >> 16) + + @ l1 invalidate + lsl r5, r3, #4 @ calculate cluster offset + ldr r6, [r0, r5] @ CX_CTRL_REG0 + bic r6, r6, r4 + str r6, [r0, r5] +#else mov r6, #0 lsl r5, r1, #6 @ 64 bytes per CPU add r5, r5, #0x40 @ Offset from base @@ -166,32 +242,109 @@ psci_cpu_on: ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG bic r6, r6, r4 str r6, [r0, #0x1e4] +#endif movw r0, #(SUNXI_PRCM_BASE & 0xffff) movt r0, #(SUNXI_PRCM_BASE >> 16) -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN8I_A83T) @ Release power clamp - lsl r5, r1, #2 @ 1 register per CPU + lsl r5, r3, #2 @ calculate cluster offset + add r5, r1 @ add CPU offset + lsl r5, r5, #2 @ 1 register per CPU add r5, r5, r0 @ PRCM +#if defined(CONFIG_MACH_SUN8I_A83T) + mov r6, #0xfe + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + timer_wait r6, TEN_MS + mov r6, #0xf8 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + mov r6, #0xe0 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + mov r6, #0xc0 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + mov r6, #0x80 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + mov r6, #0x00 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS +#else movw r6, #0x1ff movt r6, #0 1: lsrs r6, r6, #1 str r6, [r5, #0x140] @ CPUx_PWR_CLAMP bne 1b #endif +#endif timer_wait r6, TEN_MS @ Clear power gating - ldr r6, [r0, #0x100] @ CPU_PWROFF_GATING - bic r6, r6, r4 - str r6, [r0, #0x100] + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x100 @ SUNXI_CLUSTER_PWROFF_GATING + ldr r6, [r0, r5] +#if defined(CONFIG_MACH_SUN8I_A83T) + cmp r2, #0 + beq skip_a83t_rev_b_fixup + cmp r1, #0 + bne skip_a83t_rev_b_fixup + bic r6, r6, #0x10 @ core 0 power gate off + b a83t_rev_b_fixup_done +#endif +skip_a83t_rev_b_fixup: + bic r6, r6, r4 @ power gating off +a83t_rev_b_fixup_done: + str r6, [r0, r5] + + movw r0, #(SUN8I_CPUXCFG_BASE & 0xffff) + movt r0, #(SUN8I_CPUXCFG_BASE >> 16) @ re-calculate CPU control register address movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) movt r0, #(SUN6I_CPUCFG_BASE >> 16) +#if defined(CONFIG_MACH_SUN8I_A83T) + timer_wait r6, TEN_MS + timer_wait r6, TEN_MS + + @ Deassert reset on target CPU + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x30 @ SUNXI_CLUSTER_PWRON_RESET + ldr r6, [r0, r5] + orr r6, r6, r4 @ deassert reset + str r6, [r0, r5] + + movw r0, #(SUN8I_CPUXCFG_BASE & 0xffff) + movt r0, #(SUN8I_CPUXCFG_BASE >> 16) + + @ Clear any applied cluster resets + cmp r1, #0 + bne skip_cluster_reset_deassert + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x80 @ SUNXI_CPU_RST_CTRL + ldr r6, [r0, r5] + orr r6, r6, #0x1000 @ deassert HRESET + orr r6, r6, #0x100 @ deassert L2 cache reset + str r6, [r0, r5] + + lsl r5, r3, #4 @ cluster offset + add r5, r5, #0x04 @ SUNXI_CLUSTER_CTRL1 + ldr r6, [r0, r5] + bic r6, r6, #0x1 @ deassert ACINACTM + str r6, [r0, r5] +skip_cluster_reset_deassert: + + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x80 @ SUNXI_CPU_RST_CTRL + ldr r6, [r0, r5] + orr r6, r6, r4 @ deassert reset + str r6, [r0, r5] +#else @ Deassert reset on target CPU mov r6, #3 lsl r5, r1, #6 @ 64 bytes per CPU @@ -203,6 +356,7 @@ psci_cpu_on: ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG orr r6, r6, r4 str r6, [r0, #0x1e4] +#endif mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS pop {pc} -- 2.8.0.rc3

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[U-Boot] [PATCH 6/8] sunxi: Add optional logic to start cluster 1 and the associated CCI-400 ports
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- arch/arm/include/asm/arch-sunxi/prcm.h | 3 ++- board/sunxi/board.c | 49 ++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 556c1af..9e8a367 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -219,7 +219,8 @@ struct sunxi_prcm_reg { u32 clk_outd; /* 0x0f0 */ u8 res6[0xc]; /* 0x0f4 */ u32 cpu_pwroff; /* 0x100 */ - u8 res7[0xc]; /* 0x104 */ + u32 cluster1_cpu_pwr; /* 0x104 */ + u8 res7[0x8]; /* 0x108 */ u32 vdd_sys_pwroff; /* 0x110 */ u8 res8[0x4]; /* 0x114 */ u32 gpu_pwroff; /* 0x118 */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 3cf3614..65029ab 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -20,6 +20,7 @@ #include <asm/arch/dram.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/prcm.h> #include <asm/arch/usb_phy.h> #ifndef CONFIG_ARM64 #include <asm/armv7.h> @@ -30,6 +31,18 @@ #include <net.h> #include <sy8106a.h> +/* CCI-400 registers */ +struct cci400_control { + uint32_t unused0[0x3]; + uint32_t status; + uint32_t unused1[0xffc]; + uint32_t snoop_ctrl_a7; + uint32_t sha_ord_a7; + uint32_t unused2[0x3fe]; + uint32_t snoop_ctrl_a15; + uint32_t sha_ord_a15; +}; + #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ int soft_i2c_gpio_sda; @@ -122,6 +135,42 @@ int board_init(void) gpio_direction_output(CONFIG_MACPWR, 1); #endif +#ifdef CONFIG_ENABLE_CLUSTER_1 + struct sunxi_prcm_reg *prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + clrbits_le32(&prcm->cluster1_cpu_pwr, 0x1); +#endif + +#ifdef CONFIG_ENABLE_CCI400_SNOOP_CLUSTERS_0_1 + printf("Enabling snoop controls..."); + struct cci400_control *cci = (struct cci400_control *)SUN8I_CCI400_BASE; + uint32_t snoop_ctl; + + /* Set up cluster 0 CCI port */ + snoop_ctl = readl(&cci->snoop_ctrl_a7); + snoop_ctl |= CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN; + writel(snoop_ctl, &cci->snoop_ctrl_a7); + + /* Wait for snoop control change to take effect */ + while (readl(&cci->status) & 0x1); + + /* Set up cluster 1 CCI port */ + snoop_ctl = readl(&cci->snoop_ctrl_a15); + snoop_ctl |= CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN; + writel(snoop_ctl, &cci->snoop_ctrl_a15); + + /* Wait for snoop control change to take effect */ + while (readl(&cci->status) & 0x1); + + /* Force non-sharable memory */ + writel(CCI400_SHAORD_NON_SHAREABLE, &cci->sha_ord_a7); + writel(CCI400_SHAORD_NON_SHAREABLE, &cci->sha_ord_a15); + + /* Synchronize CCI enable */ + __asm__ volatile ("dsb\n"); + printf("done!\n"); +#endif + /* Uses dm gpio code so do this here and not in i2c_init_board() */ return soft_i2c_board_init(); } -- 2.8.0.rc3

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[U-Boot] [PATCH 1/8] sun8i: Add A83t SMP definitions
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- include/configs/sun8i.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index b9a8731..b239548 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -26,7 +26,6 @@ #define CONFIG_SUNXI_USB_PHYS 2 #endif -#ifndef CONFIG_MACH_SUN8I_A83T #define CONFIG_ARMV7_PSCI 1 #if defined(CONFIG_MACH_SUN8I_A23) #define CONFIG_ARMV7_PSCI_NR_CPUS 2 @@ -34,10 +33,12 @@ #define CONFIG_ARMV7_PSCI_NR_CPUS 4 #elif defined(CONFIG_MACH_SUN8I_H3) #define CONFIG_ARMV7_PSCI_NR_CPUS 4 +#elif defined(CONFIG_MACH_SUN8I_A83T) +#define CONFIG_ARMV7_PSCI_NR_CPUS 8 +#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #else #error Unsupported sun8i variant #endif -#endif /* * Include common sunxi configuration where most the settings are -- 2.8.0.rc3

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