May 2016 - U-Boot

[U-Boot] [V2] [PATCH 8/8] a83t: Enable PSCI, non-secure mode, and cluster / cache setup
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Now that the groundwork has been laid, enable all the pieces to support PSCI, KVM, and SMP. This has been tested on a mainline Linux kernel, however that kernel hangs for an unknown reason during kthread execution even though all cores start normally. It is currently assumed that this is a non-PSCI related problem. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- board/sunxi/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index fa78720..4b82d3d 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -85,8 +85,13 @@ config MACH_SUN50I config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUNXI_GEN_SUN6I select SUPPORT_SPL + select ENABLE_CLUSTER_1 + select ENABLE_CCI400_SNOOP_CLUSTERS_0_1 + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN9I bool "sun9i (Allwinner A80)" @@ -623,4 +628,12 @@ config SPL_STACK_R_ADDR default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I default 0x2fe00000 if MACH_SUN9I +config ENABLE_CLUSTER_1 + bool + default n + +config ENABLE_CCI400_SNOOP_CLUSTERS_0_1 + bool + default n + endif -- 2.8.0.rc3

1 0

[U-Boot] [V2] [PATCH 7/8] sun8i: Enable PSCI cpu_on support for A83t
by tpearson＠raptorengineering.com 17 May '16

17 May '16

This patch adds support for the PSCI cpu_on command on Allwinner A83t devices. Since cluster 1 is already set up by early init, the majority of this patch focuses on adding multi-cluster support to PSCI and A83t power sequencing. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 174 ++++++++++++++++++++++++++++++++-- 1 file changed, 164 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index d35b63e..b3090ec 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -21,6 +21,7 @@ #include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> +#include <linux/linkage.h> #include <asm/macro.h> #include <asm/psci.h> #include <asm/arch/cpu.h> @@ -45,6 +46,16 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 +@ Attempts to condense sparse ID space on multi-cluster systems to dense ID space +ENTRY(psci_get_cpu_id) + mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */ + lsr r1, r0, #6 /* extract cluster offset */ + and r1, r1, #0xff + and r0, r0, #0xff /* extract CPU ID in cluster */ + add r0, r0, r1 /* return adjusted CPU ID */ + bx lr +ENDPROC(psci_get_cpu_id) + .globl psci_fiq_enter psci_fiq_enter: push {r0-r12} @@ -106,7 +117,7 @@ psci_fiq_enter: str r10, [r8, #0x100] timer_wait r10, ONE_MS -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN8I_A83T) @ Activate power clamp lsl r12, r9, #2 @ x4 add r12, r12, r8 @@ -134,7 +145,13 @@ out: mcr p15, 0, r7, c1, c1, 0 psci_cpu_on: push {lr} - mov r0, r1 +#if defined(CONFIG_MACH_SUN8I_A83T) + lsr r3, r1, #6 @ extract cluster offset + and r0, r1, #3 @ extract CPU number + add r0, r0, r3 @ pass adjusted CPU number to setup +#else + mov r0, r1 @ pass CPU number to setup +#endif bl psci_get_cpu_stack_top @ get stack top of target CPU str r2, [r0] @ store target PC at stack top dsb @@ -142,15 +159,74 @@ psci_cpu_on: movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) movt r0, #(SUN6I_CPUCFG_BASE >> 16) + ldr r6, =psci_cpu_entry + str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) + @ CPU mask +#if defined(CONFIG_MACH_SUN8I_A83T) + lsr r3, r1, #8 @ extract cluster number + and r1, r1, #3 @ extract CPU number + + @ obtain silicon revision level + movw r0, #(SUNXI_SRAMC_BASE & 0xffff) + movt r0, #(SUNXI_SRAMC_BASE >> 16) + ldr r2, [r0, #0x24] + and r2, r2, #0x1 +#else + ldr r3, #0 @ only one cluster and r1, r1, #3 @ only care about first cluster + ldr r2, #0 @ default revision +#endif mov r4, #1 lsl r4, r4, r1 - ldr r6, =psci_cpu_entry - str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector) - @ Assert reset on target CPU +#if defined(CONFIG_MACH_SUN8I_A83T) + movw r0, #(SUN8I_CPUXCFG_BASE & 0xffff) + movt r0, #(SUN8I_CPUXCFG_BASE >> 16) + + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x80 @ SUNXI_CPU_RST_CTRL + ldr r6, [r0, r5] + bic r6, r6, r4 @ assert reset + str r6, [r0, r5] + + cmp r1, #0 + bne skip_cluster_reset_assert + + lsl r5, r3, #4 @ cluster offset + add r5, r5, #0x04 @ SUNXI_CLUSTER_CTRL1 + ldr r6, [r0, r5] + orr r6, r6, #0x1 @ assert ACINACTM + str r6, [r0, r5] + + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x80 @ SUNXI_CPU_RST_CTRL + ldr r6, [r0, r5] + bic r6, r6, #0x1000 @ assert HRESET + bic r6, r6, #0x100 @ assert L2 cache reset + str r6, [r0, r5] +skip_cluster_reset_assert: + + @ re-calculate CPU control register address + movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) + movt r0, #(SUN6I_CPUCFG_BASE >> 16) + + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x30 @ SUNXI_CLUSTER_PWRON_RESET + ldr r6, [r0, r5] + bic r6, r6, r4 @ assert reset + str r6, [r0, r5] + + movw r0, #(SUN8I_CPUXCFG_BASE & 0xffff) + movt r0, #(SUN8I_CPUXCFG_BASE >> 16) + + @ l1 invalidate + lsl r5, r3, #4 @ calculate cluster offset + ldr r6, [r0, r5] @ CX_CTRL_REG0 + bic r6, r6, r4 + str r6, [r0, r5] +#else mov r6, #0 lsl r5, r1, #6 @ 64 bytes per CPU add r5, r5, #0x40 @ Offset from base @@ -166,32 +242,109 @@ psci_cpu_on: ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG bic r6, r6, r4 str r6, [r0, #0x1e4] +#endif movw r0, #(SUNXI_PRCM_BASE & 0xffff) movt r0, #(SUNXI_PRCM_BASE >> 16) -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN8I_A83T) @ Release power clamp - lsl r5, r1, #2 @ 1 register per CPU + lsl r5, r3, #2 @ calculate cluster offset + add r5, r1 @ add CPU offset + lsl r5, r5, #2 @ 1 register per CPU add r5, r5, r0 @ PRCM +#if defined(CONFIG_MACH_SUN8I_A83T) + mov r6, #0xfe + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + timer_wait r6, TEN_MS + mov r6, #0xf8 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + mov r6, #0xe0 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + mov r6, #0xc0 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + mov r6, #0x80 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS + mov r6, #0x00 + str r6, [r5, #0x140] @ CPUx_PWR_CLAMP + timer_wait r6, TEN_MS +#else movw r6, #0x1ff movt r6, #0 1: lsrs r6, r6, #1 str r6, [r5, #0x140] @ CPUx_PWR_CLAMP bne 1b #endif +#endif timer_wait r6, TEN_MS @ Clear power gating - ldr r6, [r0, #0x100] @ CPU_PWROFF_GATING - bic r6, r6, r4 - str r6, [r0, #0x100] + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x100 @ SUNXI_CLUSTER_PWROFF_GATING + ldr r6, [r0, r5] +#if defined(CONFIG_MACH_SUN8I_A83T) + cmp r2, #0 + beq skip_a83t_rev_b_fixup + cmp r1, #0 + bne skip_a83t_rev_b_fixup + bic r6, r6, #0x10 @ core 0 power gate off + b a83t_rev_b_fixup_done +#endif +skip_a83t_rev_b_fixup: + bic r6, r6, r4 @ power gating off +a83t_rev_b_fixup_done: + str r6, [r0, r5] + + movw r0, #(SUN8I_CPUXCFG_BASE & 0xffff) + movt r0, #(SUN8I_CPUXCFG_BASE >> 16) @ re-calculate CPU control register address movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) movt r0, #(SUN6I_CPUCFG_BASE >> 16) +#if defined(CONFIG_MACH_SUN8I_A83T) + timer_wait r6, TEN_MS + timer_wait r6, TEN_MS + + @ Deassert reset on target CPU + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x30 @ SUNXI_CLUSTER_PWRON_RESET + ldr r6, [r0, r5] + orr r6, r6, r4 @ deassert reset + str r6, [r0, r5] + + movw r0, #(SUN8I_CPUXCFG_BASE & 0xffff) + movt r0, #(SUN8I_CPUXCFG_BASE >> 16) + + @ Clear any applied cluster resets + cmp r1, #0 + bne skip_cluster_reset_deassert + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x80 @ SUNXI_CPU_RST_CTRL + ldr r6, [r0, r5] + orr r6, r6, #0x1000 @ deassert HRESET + orr r6, r6, #0x100 @ deassert L2 cache reset + str r6, [r0, r5] + + lsl r5, r3, #4 @ cluster offset + add r5, r5, #0x04 @ SUNXI_CLUSTER_CTRL1 + ldr r6, [r0, r5] + bic r6, r6, #0x1 @ deassert ACINACTM + str r6, [r0, r5] +skip_cluster_reset_deassert: + + lsl r5, r3, #2 @ cluster offset + add r5, r5, #0x80 @ SUNXI_CPU_RST_CTRL + ldr r6, [r0, r5] + orr r6, r6, r4 @ deassert reset + str r6, [r0, r5] +#else @ Deassert reset on target CPU mov r6, #3 lsl r5, r1, #6 @ 64 bytes per CPU @@ -203,6 +356,7 @@ psci_cpu_on: ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG orr r6, r6, r4 str r6, [r0, #0x1e4] +#endif mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS pop {pc} -- 2.8.0.rc3

1 0

[U-Boot] [V2] [PATCH 6/8] sunxi: Add optional logic to start cluster 1 and the associated CCI-400 ports
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Multi-cluster systems require that the CCI be set up if SMP is desired via PSCI later in the boot process. Start cluster 1 and set up the CCI if requested by the SoC configuration. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- arch/arm/include/asm/arch-sunxi/prcm.h | 3 ++- board/sunxi/board.c | 45 ++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 556c1af..9e8a367 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -219,7 +219,8 @@ struct sunxi_prcm_reg { u32 clk_outd; /* 0x0f0 */ u8 res6[0xc]; /* 0x0f4 */ u32 cpu_pwroff; /* 0x100 */ - u8 res7[0xc]; /* 0x104 */ + u32 cluster1_cpu_pwr; /* 0x104 */ + u8 res7[0x8]; /* 0x108 */ u32 vdd_sys_pwroff; /* 0x110 */ u8 res8[0x4]; /* 0x114 */ u32 gpu_pwroff; /* 0x118 */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 3cf3614..0d2bd2c 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -20,6 +20,7 @@ #include <asm/arch/dram.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/prcm.h> #include <asm/arch/usb_phy.h> #ifndef CONFIG_ARM64 #include <asm/armv7.h> @@ -30,6 +31,18 @@ #include <net.h> #include <sy8106a.h> +/* CCI-400 registers */ +struct cci400_control { + uint32_t unused0[0x3]; + uint32_t status; + uint32_t unused1[0xffc]; + uint32_t snoop_ctrl_a7; + uint32_t sha_ord_a7; + uint32_t unused2[0x3fe]; + uint32_t snoop_ctrl_a15; + uint32_t sha_ord_a15; +}; + #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ int soft_i2c_gpio_sda; @@ -122,6 +135,38 @@ int board_init(void) gpio_direction_output(CONFIG_MACPWR, 1); #endif +#ifdef CONFIG_ENABLE_CLUSTER_1 + struct sunxi_prcm_reg *prcm = + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; + clrbits_le32(&prcm->cluster1_cpu_pwr, 0x1); +#endif + +#ifdef CONFIG_ENABLE_CCI400_SNOOP_CLUSTERS_0_1 + printf("Enabling snoop controls..."); + struct cci400_control *cci = (struct cci400_control *)SUN8I_CCI400_BASE; + uint32_t snoop_ctl; + + /* Set up cluster 0 CCI port */ + snoop_ctl = readl(&cci->snoop_ctrl_a7); + snoop_ctl |= CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN; + writel(snoop_ctl, &cci->snoop_ctrl_a7); + + /* Wait for snoop control change to take effect */ + while (readl(&cci->status) & 0x1); + + /* Set up cluster 1 CCI port */ + snoop_ctl = readl(&cci->snoop_ctrl_a15); + snoop_ctl |= CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN; + writel(snoop_ctl, &cci->snoop_ctrl_a15); + + /* Wait for snoop control change to take effect */ + while (readl(&cci->status) & 0x1); + + /* Synchronize CCI enable */ + __asm__ volatile ("dsb\n"); + printf("done!\n"); +#endif + /* Uses dm gpio code so do this here and not in i2c_init_board() */ return soft_i2c_board_init(); } -- 2.8.0.rc3

1 0

[U-Boot] [V2] [PATCH 5/8] sun8i: Display silicon revision of A83t processors
by tpearson＠raptorengineering.com 17 May '16

17 May '16

There are two versions of the A83t processor; per the provided Linux code from Allwinner revisions A and B can be distingushed by the lower bit of the SRAM ID register. The distinction is important because revision B requires a SMP bringup workaround. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- arch/arm/mach-sunxi/cpu_info.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index 76b6719..d552061 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -50,6 +50,17 @@ uint sunxi_get_sram_id(void) return id; } + +uint sunxi_get_revision(void) +{ + uint rev; + + /* Unlock sram info reg, read it, relock */ + rev = readl(SUNXI_SRAMC_BASE + 0x24) & 0x1; + + return rev; +} + #endif #ifdef CONFIG_DISPLAY_CPUINFO @@ -84,7 +95,7 @@ int print_cpuinfo(void) #elif defined CONFIG_MACH_SUN8I_A33 printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_A83T - printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id()); + printf("CPU: Allwinner A83T (SUN8I %04x rev. %s)\n", sunxi_get_sram_id(), (sunxi_get_revision() == 0)?"A":"B"); #elif defined CONFIG_MACH_SUN8I_H3 printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN9I -- 2.8.0.rc3

1 0

[U-Boot] [V2] [PATCH 4/8] sun8i: Add TZPC setup for A83t
by tpearson＠raptorengineering.com 17 May '16

17 May '16

This patch enables non-secure access to all system peripherals controlled by the STMA, and additionally sets the secure RAM range to 64k in line with other sunxi devices. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/tzpc.c | 10 ++++++++++ arch/arm/include/asm/arch-sunxi/tzpc.h | 10 ++++++++++ arch/arm/mach-sunxi/board.c | 2 +- 4 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 4d2274a..4dd449b 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -11,6 +11,7 @@ obj-y += timer.o obj-$(CONFIG_MACH_SUN6I) += tzpc.o obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o +obj-$(CONFIG_MACH_SUN8I_A83T) += tzpc.o ifndef CONFIG_SPL_BUILD ifdef CONFIG_ARMV7_PSCI diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c index 6c8a0fd..3b94e0d 100644 --- a/arch/arm/cpu/armv7/sunxi/tzpc.c +++ b/arch/arm/cpu/armv7/sunxi/tzpc.c @@ -18,6 +18,16 @@ void tzpc_init(void) writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set); #endif +#ifdef SUN8I_A83T_TZPC_DECPORT0_ALL + /* Set secure RAM size to defined value */ + writel(R0SIZE, &tzpc->r0size); + + /* Enable non-secure access to all peripherals */ + writel(SUN8I_A83T_TZPC_DECPORT0_ALL, &tzpc->decport0_set); + writel(SUN8I_A83T_TZPC_DECPORT1_ALL, &tzpc->decport1_set); + writel(SUN8I_A83T_TZPC_DECPORT2_ALL, &tzpc->decport2_set); +#endif + #ifdef CONFIG_MACH_SUN8I_H3 /* Enable non-secure access to all peripherals */ writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set); diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h index 95c55cd..66e6abb 100644 --- a/arch/arm/include/asm/arch-sunxi/tzpc.h +++ b/arch/arm/include/asm/arch-sunxi/tzpc.h @@ -25,6 +25,16 @@ struct sunxi_tzpc { #define SUN6I_TZPC_DECPORT0_RTC (1 << 1) +#define SUN8I_A83T_TZPC_DECPORT0_ALL 0xbe +#define SUN8I_A83T_TZPC_DECPORT1_ALL 0x7f +#define SUN8I_A83T_TZPC_DECPORT2_ALL 0x10 + +/* + * TZPC Register Value : + * R0SIZE: 0x10 : Size of secured ram (64Kib) + */ +#define R0SIZE 0x10 + #define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe #define SUN8I_H3_TZPC_DECPORT1_ALL 0xff #define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 20149da..1ded4d6 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -183,7 +183,7 @@ void s_init(void) "orr r0, r0, #1 << 6\n" "mcr p15, 0, r0, c1, c0, 1\n"); #endif -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 +#if defined CONFIG_MACH_SUN6I || || defined CONFIG_MACH_SUN8I_A83T defined CONFIG_MACH_SUN8I_H3 /* Enable non-secure access to some peripherals */ tzpc_init(); #endif -- 2.8.0.rc3

1 0

[U-Boot] [V2] [PATCH 3/8] sun8i: Extend stack size to allow for up to 8 CPUs
by tpearson＠raptorengineering.com 17 May '16

17 May '16

The existing stack size was only sufficient for four CPUs. Keep lower stack range address page alignment intact, and move the lower stack range address down a page. This has the effect of expanding the stack range by a single page, which is enough for four more CPUs. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- arch/arm/cpu/armv7/psci.S | 1 + arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++-- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 4 ++-- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 87c0c0b..18a0cc2 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -203,6 +203,7 @@ ENTRY(psci_get_cpu_stack_top) add r5, r5, #0x2000 @ Skip two pages lsr r5, r5, #12 @ Align to start of page lsl r5, r5, #12 + add r5, r5, #0x1000 @ Skip an additional page sub r5, r5, #4 @ reserve 1 word for target PC sub r0, r5, r0 @ here's our stack! diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index 90b5bfd..d35b63e 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -32,8 +32,8 @@ * ._secure_text section * text_end to ALIGN_PAGE(text_end): * nothing - * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000) - * 1kB of stack per CPU (4 CPUs max). + * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x2000) + * 1kB of stack per CPU (8 CPUs max). */ .pushsection ._secure.text, "ax" diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S index e15d587..b8ac50e 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S @@ -32,8 +32,8 @@ * ._secure_text section * text_end to ALIGN_PAGE(text_end): * nothing - * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000) - * 1kB of stack per CPU (4 CPUs max). + * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x2000) + * 1kB of stack per CPU (8 CPUs max). */ .pushsection ._secure.text, "ax" -- 2.8.0.rc3

1 0

[U-Boot] [V2] [PATCH 2/8] sun8i: Add CCI-400 definitions
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Multi-cluster systems require basic initialization of the cache coherent interconnect to enable SMP via PSCI. Add the requisite definitions for general use. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 3 +++ arch/arm/include/asm/cci.h | 10 ++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/include/asm/cci.h diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 65c0441..848e13c 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -18,6 +18,9 @@ #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ +#define SUNXI_CPUXCFG_BASE 0x01700000 +#define SUNXI_CCI400_BASE 0x01790000 + #define SUNXI_SRAMC_BASE 0x01c00000 #define SUNXI_DRAMC_BASE 0x01c01000 #define SUNXI_DMA_BASE 0x01c02000 diff --git a/arch/arm/include/asm/cci.h b/arch/arm/include/asm/cci.h new file mode 100644 index 0000000..19eae99 --- /dev/null +++ b/arch/arm/include/asm/cci.h @@ -0,0 +1,10 @@ +#ifndef __CCI_H__ +#define __CCI_H__ + +/* Register offsets for the ARM cache coherent interconnect (CCI) */ + +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 +#define CCI400_SHA_ORD_NON_SHAREABLE 0x00000002 + +#endif /* __CCI_H__ */ -- 2.8.0.rc3

1 0

[U-Boot] [V2] [PATCH 1/8] sun8i: Add A83t SMP definitions
by tpearson＠raptorengineering.com 17 May '16

17 May '16

Define number of cores and secure SRAM base in preparation for A83t SMP / PSCI enablement. Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- include/configs/sun8i.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h index b9a8731..b239548 100644 --- a/include/configs/sun8i.h +++ b/include/configs/sun8i.h @@ -26,7 +26,6 @@ #define CONFIG_SUNXI_USB_PHYS 2 #endif -#ifndef CONFIG_MACH_SUN8I_A83T #define CONFIG_ARMV7_PSCI 1 #if defined(CONFIG_MACH_SUN8I_A23) #define CONFIG_ARMV7_PSCI_NR_CPUS 2 @@ -34,10 +33,12 @@ #define CONFIG_ARMV7_PSCI_NR_CPUS 4 #elif defined(CONFIG_MACH_SUN8I_H3) #define CONFIG_ARMV7_PSCI_NR_CPUS 4 +#elif defined(CONFIG_MACH_SUN8I_A83T) +#define CONFIG_ARMV7_PSCI_NR_CPUS 8 +#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #else #error Unsupported sun8i variant #endif -#endif /* * Include common sunxi configuration where most the settings are -- 2.8.0.rc3

1 0

[U-Boot] [PATCH] test/py: Add basic QSPI testing
by Michal Simek 17 May '16

17 May '16

This is the first attempt how to test qspi. Detect SPI size. Read it all, random size, erase every block, write random data with random size and read it back, erase the whole qspi and at the end load kernel image via tftp and save it to memory. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- test/py/tests/test_qspi.py | 134 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 test/py/tests/test_qspi.py diff --git a/test/py/tests/test_qspi.py b/test/py/tests/test_qspi.py new file mode 100644 index 000000000000..f8dea6de83da --- /dev/null +++ b/test/py/tests/test_qspi.py @@ -0,0 +1,134 @@ +# Copyright (c) 2016, Xilinx Inc. Michal Simek +# +# SPDX-License-Identifier: GPL-2.0 + +import pytest +import re +import random +import u_boot_utils + +qspi_detected = False +page_size = 0 +erase_size = 0 +total_size = 0 + +# Find out qspi memory parameters +def qspi_pre_commands(u_boot_console): + output = u_boot_console.run_command('sf probe') + if not "SF: Detected" in output: + pytest.skip('No QSPI device available') + + m = re.search('page size (.+?) Bytes', output) + if m: + try: + global page_size + page_size = int(m.group(1)) + except ValueError: + pytest.fail("QSPI page size not recognized") + + print 'Page size is: ' + str(page_size) + " B" + + m = re.search('erase size (.+?) KiB', output) + if m: + try: + global erase_size + erase_size = int(m.group(1)) + except ValueError: + pytest.fail("QSPI erase size not recognized") + + erase_size *= 1024 + print 'Erase size is: ' + str(erase_size) + " B" + + m = re.search('total (.+?) MiB', output) + if m: + try: + global total_size + total_size = int(m.group(1)) + except ValueError: + pytest.fail("QSPI total size not recognized") + + total_size *= 1024 * 1024 + print 'Total size is: ' + str(total_size) + " B" + + global qspi_detected + qspi_detected = True + +# Read the whole QSPI flash twice, random_size till full flash size, random till page size +(a)pytest.mark.buildconfigspec('cmd_sf') +(a)pytest.mark.buildconfigspec('cmd_memory') +def test_qspi_read_twice(u_boot_console): + qspi_pre_commands(u_boot_console) + + if not qspi_detected: + pytest.skip('QSPI not detected') + + expected_read = "Read: OK" + + # TODO maybe add alignment and different start for pages + for size in random.randint(4, page_size), random.randint(4, total_size), total_size: + addr = u_boot_utils.find_ram_base(u_boot_console) + # FIXME using 0 is failing for me + output = u_boot_console.run_command('sf read %x 0 %x' % (addr + total_size, size)) + assert expected_read in output + output = u_boot_console.run_command('crc32 %x %x' % (addr + total_size, size)) + m = re.search('==> (.+?)', output) + if not m: + pytest.fail("CRC32 failed") + expected_crc32 = m.group(1) + output = u_boot_console.run_command('sf read %x 0 %x' % (addr + total_size + 10, size)) + assert expected_read in output + output = u_boot_console.run_command('crc32 %x %x' % (addr + total_size + 10, size)) + assert expected_crc32 in output + +# This test check crossing boundary for dual/parralel configurations +(a)pytest.mark.buildconfigspec('cmd_sf') +def test_qspi_erase_block(u_boot_console): + qspi_pre_commands(u_boot_console) + + if not qspi_detected: + pytest.skip('QSPI not detected') + + expected_erase = "Erased: OK" + for start in range(0, total_size, erase_size): + output = u_boot_console.run_command('sf erase %x %x' % (start, erase_size)) + assert expected_erase in output + +# Random write till page size, random till size and full size +(a)pytest.mark.buildconfigspec('cmd_sf') +(a)pytest.mark.buildconfigspec('cmd_memory') +def test_qspi_write_twice(u_boot_console): + qspi_pre_commands(u_boot_console) + + if not qspi_detected: + pytest.skip('QSPI not detected') + + expected_write = "Written: OK" + expected_read = "Read: OK" + + # TODO maybe add alignment and different start for pages + for size in random.randint(4, page_size), random.randint(page_size, total_size), total_size: + addr = u_boot_utils.find_ram_base(u_boot_console) + output = u_boot_console.run_command('crc32 %x %x' % (addr + total_size, size)) + m = re.search('==> (.+?)', output) + if not m: + pytest.fail("CRC32 failed") + expected_crc32 = m.group(1) + + output = u_boot_console.run_command('sf write %x 0 %x' % (addr + total_size, size)) + assert expected_write in output + output = u_boot_console.run_command('sf read %x 0 %x' % (addr + total_size + 10, size)) + assert expected_read in output + output = u_boot_console.run_command('crc32 %x %x' % (addr + total_size + 10, size)) + assert expected_crc32 in output + +(a)pytest.mark.buildconfigspec('cmd_sf') +def test_qspi_erase_all(u_boot_console): + qspi_pre_commands(u_boot_console) + + if not qspi_detected: + pytest.skip('QSPI not detected') + + expected_erase = "Erased: OK" + start = 0 + output = u_boot_console.run_command('sf erase 0 ' + str(hex(total_size))) + assert expected_erase in output -- 1.9.1

2 3

[U-Boot] AR71xx / AR9331 UART initialization
by Mike Monaghan 17 May '16

17 May '16

Hello, I'm looking for some help fixing a possible issue on AR9331 platforms covered by the AR71xx target. In uBoot we're getting nothing but framing errors over serial. Once Linux initializes the port. everything works fine. Digging in the code, I've been able to find that the Linux driver for the UART: - Enables the UART - Pokes a Startup code to a register - Sets Bit rate - Set Parity, length and stop bits. All I can find in the uBoot code is it setting the bit rate. Am I missing where the driver is doing the things the Linux driver does? The data sheet seems to indicate that the UART Enable and Startup deals with pin multiplexing, defaults, and clock selection. I'm wondering if that's causing our issues. We're using 15200/n/8/1 for Linux and uBoot. I'm using a vendor provided version of uBoot. Thanks, Mike

1 0