April 2016 - U-Boot

[U-Boot] [PATCH] usb: ums - expose selected partition/s
by John Tobias 11 Apr '16

11 Apr '16

By applying this patch, it will give us some flexibility to expose a selected partition/s. e.g: 1. To expose several partitions ums 0 mmc 0:1,0:6 2. To expose the all partitions ums 0 mmc 0:0 3. To expose multiple partititions on several devices ums 0 mmc 0:1,1:6 Signed-off-by: John Tobias <john.tobias.ph(a)gmail.com> --- cmd/usb_mass_storage.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c index 0415591..3e6ec50 100644 --- a/cmd/usb_mass_storage.c +++ b/cmd/usb_mass_storage.c @@ -50,14 +50,16 @@ static void ums_fini(void) #define UMS_NAME_LEN 16 -static int ums_init(const char *devtype, const char *devnums) +static int ums_init(const char *devtype, const char *devnums_part) { - char *s, *t, *devnum, *name; + char *s, *t, *devnum_part, *name; block_dev_desc_t *block_dev; + disk_partition_t info; + int partnum; int ret; struct ums *ums_new; - s = strdup(devnums); + s = strdup(devnums_part); if (!s) return -1; @@ -65,12 +67,14 @@ static int ums_init(const char *devtype, const char *devnums) ums_count = 0; for (;;) { - devnum = strsep(&t, ","); - if (!devnum) + devnum_part = strsep(&t, ","); + if (!devnum_part) break; - ret = get_device(devtype, devnum, &block_dev); - if (ret < 0) + partnum = get_device_and_partition(devtype, devnum_part, + &block_dev, &info, 1); + + if (partnum < 0) goto cleanup; /* f_mass_storage.c assumes SECTOR_SIZE sectors */ @@ -86,10 +90,18 @@ static int ums_init(const char *devtype, const char *devnums) } ums = ums_new; + /* if partnum = 0, expose the whole device */ + if (partnum == 0) { + ums[ums_count].start_sector = 0; + ums[ums_count].num_sectors = block_dev->lba; + } else { + ums[ums_count].start_sector = info.start; + ums[ums_count].num_sectors = info.size; + } + ums[ums_count].read_sector = ums_read_sector; ums[ums_count].write_sector = ums_write_sector; - ums[ums_count].start_sector = 0; - ums[ums_count].num_sectors = block_dev->lba; + name = malloc(UMS_NAME_LEN); if (!name) { ret = -1; @@ -230,6 +242,6 @@ cleanup_ums_init: U_BOOT_CMD(ums, 4, 1, do_usb_mass_storage, "Use the UMS [USB Mass Storage]", - "<USB_controller> [<devtype>] <devnum> e.g. ums 0 mmc 0\n" + "<USB_controller> [<devtype>] <dev[:part]> e.g. ums 0 mmc 0:0\n" " devtype defaults to mmc" ); -- 2.8.1

2 1

[U-Boot] [PATCH 1/7] gpio: zynq: Convert Zynq GPIO to driver model
by Michal Simek 11 Apr '16

11 Apr '16

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Convert Zynq GPIO driver to driver model Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/gpio/zynq_gpio.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c index 83a2c465d011..92c9f0ecd12e 100644 --- a/drivers/gpio/zynq_gpio.c +++ b/drivers/gpio/zynq_gpio.c @@ -14,6 +14,17 @@ #include <asm/io.h> #include <asm/errno.h> +#ifdef CONFIG_DM_GPIO +#include <dm.h> +#include <fdtdec.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct zynq_gpio_privdata { + phys_addr_t base; +}; +#endif + /** * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank * for a given pin in the GPIO device @@ -68,6 +79,7 @@ static int check_gpio(unsigned gpio) return 0; } +#ifndef CONFIG_DM_GPIO /** * gpio_get_value - Get the state of the specified pin of GPIO device * @gpio: gpio pin number within the device @@ -218,3 +230,142 @@ int gpio_free(unsigned gpio) { return 0; } +#else +static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) +{ + u32 data; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(gpio) < 0) + return -1; + + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + + data = readl(priv->base + + ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); + + return (data >> bank_pin_num) & 1; +} + +static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value) +{ + unsigned int reg_offset, bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(gpio) < 0) + return -1; + + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + + if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { + /* only 16 data bits in bit maskable reg */ + bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; + reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); + } else { + reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); + } + + /* + * get the 32 bit value to be written to the mask/data register where + * the upper 16 bits is the mask and lower 16 bits is the data + */ + value = !!value; + value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & + ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); + + writel(value, priv->base + reg_offset); + + return 0; +} + +static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio) +{ + u32 reg; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(gpio) < 0) + return -1; + + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + + /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ + if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) + return -1; + + /* clear the bit in direction mode reg to set the pin as input */ + reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg &= ~BIT(bank_pin_num); + writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + return 0; +} + +static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, + int value) +{ + u32 reg; + unsigned int bank_num, bank_pin_num; + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + if (check_gpio(gpio) < 0) + return -1; + + zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num); + + /* set the GPIO pin as output */ + reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + reg |= BIT(bank_pin_num); + writel(reg, priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); + + /* configure the output enable reg for the pin */ + reg = readl(priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + reg |= BIT(bank_pin_num); + writel(reg, priv->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); + + /* set the state of the pin */ + gpio_set_value(gpio, value); + return 0; +} + +static const struct dm_gpio_ops gpio_zynq_ops = { + .direction_input = zynq_gpio_direction_input, + .direction_output = zynq_gpio_direction_output, + .get_value = zynq_gpio_get_value, + .set_value = zynq_gpio_set_value, +}; + +static int zynq_gpio_probe(struct udevice *dev) +{ + struct zynq_gpio_privdata *priv = dev_get_priv(dev); + + priv->base = dev_get_addr(dev); + + return 0; +} + +static int zynq_gpio_ofdata_to_platdata(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->gpio_count = ZYNQ_GPIO_NR_GPIOS; + + return 0; +} + +static const struct udevice_id zynq_gpio_ids[] = { + { .compatible = "xlnx,zynq-gpio-1.0" }, + { } +}; + +U_BOOT_DRIVER(gpio_zynq) = { + .name = "gpio_zynq", + .id = UCLASS_GPIO, + .ops = &gpio_zynq_ops, + .of_match = zynq_gpio_ids, + .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata, + .probe = zynq_gpio_probe, + .priv_auto_alloc_size = sizeof(struct zynq_gpio_privdata), +}; +#endif -- 1.9.1

1 6

[U-Boot] [PATCH] ARM64: zynqmp: Remove netdev.h from board file
by Michal Simek 11 Apr '16

11 Apr '16

Including netdev.h is causing compilation warning: + int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); + ^ w+In file included from ../board/xilinx/zynqmp/zynqmp.c:9:0: w+../include/netdev.h:204:41: warning: ‘struct eth_device’ declared inside parameter list [enabled by default] w+../include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] This patch removes it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynqmp/zynqmp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 529476b08268..132d724fbdf8 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -6,7 +6,6 @@ */ #include <common.h> -#include <netdev.h> #include <sata.h> #include <ahci.h> #include <scsi.h> -- 1.9.1

1 0

[U-Boot] [PATCH] ARM64: zynqmp: Add defconfig for zcu102 revB board
by Michal Simek 11 Apr '16

11 Apr '16

Support natively revB board. Till now support for revB was done via zcu102 defconfig where device-tree was changed to revB. This patch is adding direct defconfig for RevB. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_zcu102_revB_defconfig | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 configs/xilinx_zynqmp_zcu102_revB_defconfig diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig new file mode 100644 index 000000000000..542a24a8d5b4 --- /dev/null +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_DM_GPIO=y +CONFIG_TARGET_ZYNQMP_ZCU102=y +CONFIG_ZYNQMP_QSPI=y +CONFIG_ZYNQMP_USB=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_MMC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y -- 1.9.1

1 0

[U-Boot] [PATCH] dm: spi: Read default speed, mode values from DT
by Vignesh R 11 Apr '16

11 Apr '16

In case of DT boot, don't read default speed and mode for SPI from CONFIG_*, instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and modes. Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- cmd/sf.c | 2 ++ drivers/spi/spi-uclass.c | 8 ++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/cmd/sf.c b/cmd/sf.c index 42862d9d921a..4c40d5104422 100644 --- a/cmd/sf.c +++ b/cmd/sf.c @@ -88,6 +88,8 @@ static int do_spi_flash_probe(int argc, char * const argv[]) #ifdef CONFIG_DM_SPI_FLASH struct udevice *new, *bus_dev; int ret; + /* In DM mode defaults wiil be taken from DT */ + speed = -1, mode = -1; #else struct spi_flash *new; #endif diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 5561f36762f9..55ebb5ef19b7 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -264,6 +264,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, struct udevice **busp, struct spi_slave **devp) { struct udevice *bus, *dev; + struct dm_spi_slave_platdata *plat; bool created = false; int ret; @@ -280,8 +281,6 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, * SPI flash chip - we will bind to the correct driver. */ if (ret == -ENODEV && drv_name) { - struct dm_spi_slave_platdata *plat; - debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n", __func__, dev_name, busnum, cs, drv_name); ret = device_bind_driver(bus, drv_name, dev_name, &dev); @@ -308,6 +307,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, slave->dev = dev; } + plat = dev_get_parent_platdata(dev); + if (speed == -1) + speed = plat->max_hz; + if (mode == -1) + mode = plat->mode; ret = spi_set_speed_mode(bus, speed, mode); if (ret) goto err; -- 2.8.1

3 4

[U-Boot] [PATCH 1/2] dm: spi: soft_spi: support linux way and bug fix
by Peng Fan 11 Apr '16

11 Apr '16

1. Support compatible string "spi-gpio" which is used by Linux Linux use different bindings, so use UBOOT_COMPAT and LINUX_COMPAT to differentiate them. 2. Bug fix When doing xfer, should use device->parent, but not device When doing bit xfer, should use "!!(tmpdout & 0x80)", but not "(tmpdout & 0x80)" 3. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle no rx or no tx case. 4. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip. Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Jagan Teki <jteki(a)openedev.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/spi/soft_spi.c | 75 ++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 57 insertions(+), 18 deletions(-) diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index aa4abcc..9a2b5f2 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -26,15 +26,23 @@ struct soft_spi_platdata { struct gpio_desc mosi; struct gpio_desc miso; int spi_delay_us; + int flags; }; +#define SPI_MASTER_NO_RX BIT(0) +#define SPI_MASTER_NO_TX BIT(1) + +#define UBOOT_COMPAT BIT(0) +#define LINUX_COMPAT BIT(1) + struct soft_spi_priv { unsigned int mode; }; static int soft_spi_scl(struct udevice *dev, int bit) { - struct soft_spi_platdata *plat = dev->platdata; + struct udevice *bus = dev_get_parent(dev); + struct soft_spi_platdata *plat = dev_get_platdata(bus); dm_gpio_set_value(&plat->sclk, bit); @@ -43,7 +51,8 @@ static int soft_spi_scl(struct udevice *dev, int bit) static int soft_spi_sda(struct udevice *dev, int bit) { - struct soft_spi_platdata *plat = dev->platdata; + struct udevice *bus = dev_get_parent(dev); + struct soft_spi_platdata *plat = dev_get_platdata(bus); dm_gpio_set_value(&plat->mosi, bit); @@ -52,7 +61,8 @@ static int soft_spi_sda(struct udevice *dev, int bit) static int soft_spi_cs_activate(struct udevice *dev) { - struct soft_spi_platdata *plat = dev->platdata; + struct udevice *bus = dev_get_parent(dev); + struct soft_spi_platdata *plat = dev_get_platdata(bus); dm_gpio_set_value(&plat->cs, 0); dm_gpio_set_value(&plat->sclk, 0); @@ -63,7 +73,8 @@ static int soft_spi_cs_activate(struct udevice *dev) static int soft_spi_cs_deactivate(struct udevice *dev) { - struct soft_spi_platdata *plat = dev->platdata; + struct udevice *bus = dev_get_parent(dev); + struct soft_spi_platdata *plat = dev_get_platdata(bus); dm_gpio_set_value(&plat->cs, 0); @@ -100,8 +111,9 @@ static int soft_spi_release_bus(struct udevice *dev) static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - struct soft_spi_priv *priv = dev_get_priv(dev); - struct soft_spi_platdata *plat = dev->platdata; + struct udevice *bus = dev_get_parent(dev); + struct soft_spi_priv *priv = dev_get_priv(bus); + struct soft_spi_platdata *plat = dev_get_platdata(bus); uchar tmpdin = 0; uchar tmpdout = 0; const u8 *txd = dout; @@ -134,14 +146,16 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen, if (!cpha) soft_spi_scl(dev, 0); - soft_spi_sda(dev, tmpdout & 0x80); + if ((plat->flags & SPI_MASTER_NO_TX) == 0) + soft_spi_sda(dev, !!(tmpdout & 0x80)); udelay(plat->spi_delay_us); if (cpha) soft_spi_scl(dev, 0); else soft_spi_scl(dev, 1); tmpdin <<= 1; - tmpdin |= dm_gpio_get_value(&plat->miso); + if ((plat->flags & SPI_MASTER_NO_RX) == 0) + tmpdin |= dm_gpio_get_value(&plat->miso); tmpdout <<= 1; udelay(plat->spi_delay_us); if (cpha) @@ -202,25 +216,50 @@ static int soft_spi_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); struct soft_spi_platdata *plat = dev->platdata; + ulong driver_data = dev_get_driver_data(dev); int cs_flags, clk_flags; + int ret; cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW; clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0; - if (gpio_request_by_name(dev, "cs-gpio", 0, &plat->cs, - GPIOD_IS_OUT | cs_flags) || - gpio_request_by_name(dev, "sclk-gpio", 0, &plat->sclk, - GPIOD_IS_OUT | clk_flags) || - gpio_request_by_name(dev, "mosi-gpio", 0, &plat->mosi, - GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE) || - gpio_request_by_name(dev, "miso-gpio", 0, &plat->miso, - GPIOD_IS_IN)) - return -EINVAL; + if (driver_data & UBOOT_COMPAT) { + if (gpio_request_by_name(dev, "cs-gpio", 0, &plat->cs, + GPIOD_IS_OUT | cs_flags) || + gpio_request_by_name(dev, "sclk-gpio", 0, &plat->sclk, + GPIOD_IS_OUT | clk_flags) || + gpio_request_by_name(dev, "mosi-gpio", 0, &plat->mosi, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE) || + gpio_request_by_name(dev, "miso-gpio", 0, &plat->miso, + GPIOD_IS_IN)) + return -EINVAL; + } else if (driver_data & LINUX_COMPAT) { + if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs, + GPIOD_IS_OUT | cs_flags) || + gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, + GPIOD_IS_OUT | clk_flags)) + return -EINVAL; + + ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) + plat->flags |= SPI_MASTER_NO_TX; + + ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso, + GPIOD_IS_IN); + if (ret) + plat->flags |= SPI_MASTER_NO_RX; + + if ((plat->flags & (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) == + (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) + return -EINVAL; + } return 0; } static const struct udevice_id soft_spi_ids[] = { - { .compatible = "u-boot,soft-spi" }, + { .compatible = "u-boot,soft-spi", .data = UBOOT_COMPAT }, + { .compatible = "spi-gpio", .data = LINUX_COMPAT }, { } }; -- 2.6.2

2 5

[U-Boot] [PATCH 2/6 v3] i2c: designware_i2c: Add dw_i2c_enable() helper function
by Stefan Roese 11 Apr '16

11 Apr '16

dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes sense to add such a function, as the controller is dis-/en-abled multiple times in the code. Additionally, this function now checks, if the controller is really dis-/en-abled. This code is copied from the Linux I2C driver version. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Heiko Schocher <hs(a)denx.de> --- v3: - Rework dw_i2c_enable() as suggested by Marek v2: - Use true / false for binary values as suggested by Bin drivers/i2c/designware_i2c.c | 47 +++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index e768cde..d5b3e29 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -34,6 +34,27 @@ static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) return NULL; } +static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) +{ + u32 ena = enable ? IC_ENABLE_0B : 0; + int timeout = 100; + + do { + writel(ena, &i2c_base->ic_enable); + if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena) + return; + + /* + * Wait 10 times the signaling period of the highest I2C + * transfer supported by the driver (for 400KHz this is + * 25us) as described in the DesignWare I2C databook. + */ + udelay(25); + } while (timeout--); + + printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis"); +} + /* * set_speed - Set the i2c speed mode (standard, high, fast) * @i2c_spd: required i2c speed mode @@ -45,12 +66,9 @@ static void set_speed(struct i2c_adapter *adap, int i2c_spd) struct i2c_regs *i2c_base = i2c_get_base(adap); unsigned int cntl; unsigned int hcnt, lcnt; - unsigned int enbl; /* to set speed cltr must be disabled */ - enbl = readl(&i2c_base->ic_enable); - enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, false); cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); @@ -84,8 +102,7 @@ static void set_speed(struct i2c_adapter *adap, int i2c_spd) writel(cntl, &i2c_base->ic_con); /* Enable back i2c now speed set */ - enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, true); } /* @@ -123,12 +140,9 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) { struct i2c_regs *i2c_base = i2c_get_base(adap); - unsigned int enbl; /* Disable i2c */ - enbl = readl(&i2c_base->ic_enable); - enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, false); writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); writel(IC_RX_TL, &i2c_base->ic_rx_tl); @@ -138,9 +152,7 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed, writel(slaveaddr, &i2c_base->ic_sar); /* Enable i2c */ - enbl = readl(&i2c_base->ic_enable); - enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, true); } /* @@ -152,19 +164,14 @@ static void dw_i2c_init(struct i2c_adapter *adap, int speed, static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr) { struct i2c_regs *i2c_base = i2c_get_base(adap); - unsigned int enbl; /* Disable i2c */ - enbl = readl(&i2c_base->ic_enable); - enbl &= ~IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, false); writel(i2c_addr, &i2c_base->ic_tar); /* Enable i2c */ - enbl = readl(&i2c_base->ic_enable); - enbl |= IC_ENABLE_0B; - writel(enbl, &i2c_base->ic_enable); + dw_i2c_enable(i2c_base, true); } /* -- 2.7.4

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[U-Boot] [PATCH] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
by Yunhui Cui 11 Apr '16

11 Apr '16

From: Yunhui Cui <yunhui.cui(a)nxp.com> The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance. Signed-off-by: Yunhui Cui <yunhui.cui(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 ++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ board/freescale/ls2080ardb/ls2080ardb.c | 2 ++ 4 files changed, 23 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a76447e..06c950f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -17,6 +17,24 @@ #endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +/* + * Set the bit corresponding to our watchDog-id in the + * PMU-Physical Core Time Base Enable Register (PCTBENR) + * to allow the WDT counter to decrement and raise a reset + * request (if configured in the WDTCONTROL register). + */ +void enable_watchdog_clk(void) +{ + #define FSL_PMU_REG_BASE 0x1E30000 + #define FSL_PMU_PCTBENR_OFFSET 0x8A0 + u32 pmu_val; + + pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET); + *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff; +} +#endif + #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) /* diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 56989e1..32c9185 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void); #endif void cpu_name(char *name); +void enable_watchdog_clk(void); #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 void erratum_a009635(void); #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index e1a521d..8ebc96a 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -213,6 +213,8 @@ int board_init(void) select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); rtc_enable_32khz_output(); + enable_watchdog_clk(); + return 0; } diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 8201048..ad8324a 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -181,6 +181,8 @@ int board_init(void) /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); + enable_watchdog_clk(); + return 0; } -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2] armv8/ls2080a: configure PMU's PCTBENR to enable WDT
by Yunhui Cui 11 Apr '16

11 Apr '16

From: Yunhui Cui <yunhui.cui(a)nxp.com> The SP805-WDT module on LS2080A and LS2085A, requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. In order not to affect the sp805wdt driver frame, we enable the watchdog clk in advance. Signed-off-by: Yunhui Cui <yunhui.cui(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 17 +++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + board/freescale/ls2080aqds/ls2080aqds.c | 2 ++ board/freescale/ls2080ardb/ls2080ardb.c | 2 ++ 5 files changed, 26 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index a76447e..e6f3566 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -17,6 +17,23 @@ #endif DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +/* + * There are eight SP805 watchdog units on ls2080a/ls2085a,So + * Set PMU-Physical Core Time Base Enable Register (PCTBENR) + * low eight bits to enable clocks to eight Cortext-A57 cores + * timebase, which allows the WDT counter to decrement and raise + * a reset request (if configured in the WDTCONTROL register). + */ +void enable_watchdog_clk(void) +{ + u32 pmu_val; + + pmu_val = *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET); + *(u32 *)(FSL_PMU_REG_BASE + FSL_PMU_PCTBENR_OFFSET) = pmu_val | 0xff; +} +#endif + #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) /* diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ceefe43..b9656d7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -148,6 +148,10 @@ #define CONFIG_ARM_ERRATA_829520 #define CONFIG_ARM_ERRATA_833471 +/* PMU-Physical Core Time Base Enable Register */ +#define FSL_PMU_REG_BASE 0x1E30000 +#define FSL_PMU_PCTBENR_OFFSET 0x8A0 + #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 56989e1..32c9185 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -91,6 +91,7 @@ void fsl_lsch2_early_init_f(void); #endif void cpu_name(char *name); +void enable_watchdog_clk(void); #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 void erratum_a009635(void); #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index e1a521d..8ebc96a 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -213,6 +213,8 @@ int board_init(void) select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); rtc_enable_32khz_output(); + enable_watchdog_clk(); + return 0; } diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 8201048..ad8324a 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -181,6 +181,8 @@ int board_init(void) /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); + enable_watchdog_clk(); + return 0; } -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] serial: add BCM283x mini UART driver
by Stephen Warren 11 Apr '16

11 Apr '16

The RPi3 typically uses the regular UART for high-speed communication with the Bluetooth device, leaving us the mini UART to use for the serial console. Add support for this UART so we can use it. Signed-off-by: Stephen Warren <swarren(a)wwwdotorg.org> --- (This will be a dependency for the RPi 3 patches, so it'd be good if it could make it into mainline pretty quickly if acceptable.) drivers/serial/Makefile | 1 + drivers/serial/serial_bcm283x_mu.c | 138 +++++++++++++++++++++++++++ include/dm/platform_data/serial_bcm283x_mu.h | 22 +++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/serial/serial_bcm283x_mu.c create mode 100644 include/dm/platform_data/serial_bcm283x_mu.h diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 05bdf56c6fe9..ee7147a77abc 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o +obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c new file mode 100644 index 000000000000..97b57cc52163 --- /dev/null +++ b/drivers/serial/serial_bcm283x_mu.c @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2016 Stephen Warren <swarren(a)wwwdotorg.org> + * + * Derived from pl01x code: + * + * (C) Copyright 2000 + * Rob Taylor, Flying Pig Systems. robt(a)flyingpig.com. + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, <philippe.robin(a)arm.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Simple U-Boot driver for the BCM283x mini UART */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <watchdog.h> +#include <asm/io.h> +#include <serial.h> +#include <dm/platform_data/serial_bcm283x_mu.h> +#include <linux/compiler.h> +#include <fdtdec.h> + +struct bcm283x_mu_regs { + u32 io; + u32 iir; + u32 ier; + u32 lcr; + u32 mcr; + u32 lsr; + u32 msr; + u32 scratch; + u32 cntl; + u32 stat; + u32 baud; +}; + +#define BCM283X_MU_LCR_DATA_SIZE_8 3 + +#define BCM283X_MU_LSR_TX_IDLE BIT(6) +/* This actually means not full, but is named not empty in the docs */ +#define BCM283X_MU_LSR_TX_EMPTY BIT(5) +#define BCM283X_MU_LSR_RX_READY BIT(0) + +struct bcm283x_mu_priv { + struct bcm283x_mu_regs *regs; +}; + +static int bcm283x_mu_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct bcm283x_mu_priv *priv = dev_get_priv(dev); + struct bcm283x_mu_regs *regs = priv->regs; + /* FIXME: Get this from plat data later */ + u32 clock_rate = 250000000; + u32 divider; + + divider = clock_rate / (baudrate * 8); + + writel(BCM283X_MU_LCR_DATA_SIZE_8, &regs->lcr); + writel(divider - 1, &regs->baud); + + return 0; +} + +static int bcm283x_mu_serial_probe(struct udevice *dev) +{ + struct bcm283x_mu_serial_platdata *plat = dev_get_platdata(dev); + struct bcm283x_mu_priv *priv = dev_get_priv(dev); + + priv->regs = (struct bcm283x_mu_regs *)plat->base; + + return 0; +} + +static int bcm283x_mu_serial_getc(struct udevice *dev) +{ + struct bcm283x_mu_priv *priv = dev_get_priv(dev); + struct bcm283x_mu_regs *regs = priv->regs; + u32 data; + + /* Wait until there is data in the FIFO */ + if (!(readl(&regs->lsr) & BCM283X_MU_LSR_RX_READY)) + return -EAGAIN; + + data = readl(&regs->io); + + return (int)data; +} + +static int bcm283x_mu_serial_putc(struct udevice *dev, const char data) +{ + struct bcm283x_mu_priv *priv = dev_get_priv(dev); + struct bcm283x_mu_regs *regs = priv->regs; + + /* Wait until there is space in the FIFO */ + if (!(readl(&regs->lsr) & BCM283X_MU_LSR_TX_EMPTY)) + return -EAGAIN; + + /* Send the character */ + writel(data, &regs->io); + + return 0; +} + +static int bcm283x_mu_serial_pending(struct udevice *dev, bool input) +{ + struct bcm283x_mu_priv *priv = dev_get_priv(dev); + struct bcm283x_mu_regs *regs = priv->regs; + unsigned int lsr = readl(&regs->lsr); + + if (input) { + WATCHDOG_RESET(); + return lsr & BCM283X_MU_LSR_RX_READY; + } else { + return !(lsr & BCM283X_MU_LSR_TX_IDLE); + } +} + +static const struct dm_serial_ops bcm283x_mu_serial_ops = { + .putc = bcm283x_mu_serial_putc, + .pending = bcm283x_mu_serial_pending, + .getc = bcm283x_mu_serial_getc, + .setbrg = bcm283x_mu_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_bcm283x_mu) = { + .name = "serial_bcm283x_mu", + .id = UCLASS_SERIAL, + .platdata_auto_alloc_size = sizeof(struct bcm283x_mu_serial_platdata), + .probe = bcm283x_mu_serial_probe, + .ops = &bcm283x_mu_serial_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct bcm283x_mu_priv), +}; diff --git a/include/dm/platform_data/serial_bcm283x_mu.h b/include/dm/platform_data/serial_bcm283x_mu.h new file mode 100644 index 000000000000..441594579549 --- /dev/null +++ b/include/dm/platform_data/serial_bcm283x_mu.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2016 Stephen Warren <swarren(a)wwwdotorg.org> + * + * Derived from pl01x code: + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __serial_bcm283x_mu_h +#define __serial_bcm283x_mu_h + +/* + *Information about a serial port + * + * @base: Register base address + */ +struct bcm283x_mu_serial_platdata { + unsigned long base; +}; + +#endif -- 2.7.3

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