April 2016 - U-Boot

[U-Boot] Please pull u-boot-mpc85xx master
by York Sun 11 Apr '16

11 Apr '16

Tom, The following changes since commit 46a16bd895144617575c788d9c2554aeef76ac44: kirkwood_nand: claim MPP pins on the fly (2016-04-06 15:40:33 +0200) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master for you to fetch changes up to 50689461205e0125759eb1a43787383a3fa09b48: powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx (2016-04-08 15:42:10 -0700) ---------------------------------------------------------------- Codrin Ciubotariu (1): powerpc: t1040qds: Use generic ethsw commands York Sun (1): powerpc: Replace CONFIG_SYS_INIT_RAM_END with CONFIG_SYS_INIT_RAM_SIZE mario.six(a)gdsys.cc (1): powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 9 ++------- arch/powerpc/cpu/mpc85xx/start.S | 30 +++++++++++++++++++++++++++++ include/configs/BSC9131RDB.h | 4 ++-- include/configs/BSC9132QDS.h | 4 ++-- include/configs/C29XPCIE.h | 4 ++-- include/configs/P1010RDB.h | 4 ++-- include/configs/T1040QDS.h | 2 +- include/configs/a3m071.h | 4 ++-- include/configs/ac14xx.h | 4 ++-- include/configs/dlvision-10g.h | 4 ++-- include/configs/io.h | 4 ++-- include/configs/iocon.h | 4 ++-- include/configs/o2dnt-common.h | 6 +++--- include/ppc_asm.tmpl | 3 +++ 14 files changed, 57 insertions(+), 29 deletions(-) Thanks. York

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[U-Boot] [PATCH 1/2] dm: gpio: mxc: fix mxc_gpio_bank_get_value
by Peng Fan 11 Apr '16

11 Apr '16

When configured a gpio to output direction, directly reading PSR register can not return the output value, since we did not set SION bit for gpio iomux. So, we can use data register to reflect what value is outputed. If not, "regulator status" always return disabled, even if already "regulator enable": " => regulator enable => regulator status Regulator VSD_3V3 status: * enable: 0 (false) * value uV: 3300000 * current uA: No data available (err: -61) * mode id: Function not implemented (err: -38) " Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> --- drivers/gpio/mxc_gpio.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 70fe5b6..b6ae3fc 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -201,6 +201,9 @@ static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset, static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset) { + if (mxc_gpio_is_output(regs, offset)) + return (readl(&regs->gpio_dr) >> offset) & 0x01; + return (readl(&regs->gpio_psr) >> offset) & 0x01; } -- 2.6.2

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[U-Boot] [PATCH v8 6/9] drivers: serial: add serial driver for ar933x SOC
by Wills Wang 11 Apr '16

11 Apr '16

This patch add support for ar933x serial. Reviewed-by: Thomas Chou <thomas(a)wytron.com.tw> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v8: - Remove ath79_serial_write/read - Use pinctrl for serial - Add Kconfig dependence for serial option Changes in v7: - remove map_physmem for debug port Changes in v6: - Remove wait loop in putc and getc - Use map_physmem instead of KSEG1ADDR Changes in v5: - remove ar933x_serial_platdata - Import document "qca,ar9330-uart.txt" from kernel - Add support for debug UART Changes in v4: - Auto calculate baudrate for serial driver - Move pinctrl code in serial driver into arch/mips/mach-ath79 - Use get_serial_clock to serial clock source Changes in v3: - Convert serial driver to driver model Changes in v2: - Move serial driver code into drivers/serial .../serial/qca,ar9330-uart.txt | 24 ++ drivers/serial/Kconfig | 18 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 255 +++++++++++++++++++++ 4 files changed, 298 insertions(+) create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt create mode 100644 drivers/serial/serial_ar933x.c diff --git a/doc/device-tree-bindings/serial/qca,ar9330-uart.txt b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt new file mode 100644 index 0000000..ec576a1 --- /dev/null +++ b/doc/device-tree-bindings/serial/qca,ar9330-uart.txt @@ -0,0 +1,24 @@ +* Qualcomm Atheros AR9330 High-Speed UART + +Required properties: + +- compatible: Must be "qca,ar9330-uart" + +- reg: Specifies the physical base address of the controller and + the length of the memory mapped region. + +Additional requirements: + + Each UART port must have an alias correctly numbered in "aliases" + node. + +Example: + + aliases { + serial0 = &uart0; + }; + + uart0: uart@18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 92d4212..d451441 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -89,6 +89,15 @@ config DEBUG_UART_ALTERA_UART You will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_AR933X + bool "QCA/Atheros ar933x" + depends on AR933X_UART + help + Select this to enable a debug UART using the ar933x uart driver. + You will need to provide parameters to make this work. The + driver will be available until the real driver model serial is + running. + config DEBUG_UART_NS16550 bool "ns16550" help @@ -254,6 +263,15 @@ config ALTERA_UART Select this to enable an UART for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config AR933X_UART + bool "QCA/Atheros ar933x UART support" + depends on DM_SERIAL && SOC_AR933X + help + Select this to enable UART support for QCA/Atheros ar933x + devices. This driver uses driver model and requires a device + tree binding to operate, please refer to the document at + doc/device-tree-bindings/serial/qca,ar9330-uart.txt. + config FSL_LPUART bool "Freescale LPUART support" help diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 05bdf56..42e493a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_UART) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.o diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c new file mode 100644 index 0000000..d43f9c9 --- /dev/null +++ b/drivers/serial/serial_ar933x.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <serial.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <dm/pinctrl.h> +#include <mach/ar71xx_regs.h> + +#define AR933X_UART_DATA_REG 0x00 +#define AR933X_UART_CS_REG 0x04 +#define AR933X_UART_CLK_REG 0x08 + +#define AR933X_UART_DATA_TX_RX_MASK 0xff +#define AR933X_UART_DATA_RX_CSR BIT(8) +#define AR933X_UART_DATA_TX_CSR BIT(9) +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_M 0x3 +#define AR933X_UART_CS_IF_MODE_DTE 1 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_TX_RDY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_RDY_ORIDE BIT(8) +#define AR933X_UART_CLK_STEP_M 0xffff +#define AR933X_UART_CLK_SCALE_M 0xfff +#define AR933X_UART_CLK_SCALE_S 16 +#define AR933X_UART_CLK_STEP_S 0 + +struct ar933x_serial_priv { + void __iomem *regs; +}; + +/* + * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17)) + */ +static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step) +{ + u64 t; + u32 div; + + div = (2 << 16) * (scale + 1); + t = clk; + t *= step; + t += (div / 2); + do_div(t, div); + + return t; +} + +static void ar933x_serial_get_scale_step(u32 clk, u32 baud, + u32 *scale, u32 *step) +{ + u32 tscale, baudrate; + long min_diff; + + *scale = 0; + *step = 0; + + min_diff = baud; + for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++) { + u64 tstep; + int diff; + + tstep = baud * (tscale + 1); + tstep *= (2 << 16); + do_div(tstep, clk); + + if (tstep > AR933X_UART_CLK_STEP_M) + break; + + baudrate = ar933x_serial_get_baud(clk, tscale, tstep); + diff = abs(baudrate - baud); + if (diff < min_diff) { + min_diff = diff; + *scale = tscale; + *step = tstep; + } + } +} + +static int ar933x_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct ar933x_serial_priv *priv = dev_get_priv(dev); + u32 val, scale, step; + + val = get_serial_clock(); + ar933x_serial_get_scale_step(val, baudrate, &scale, &step); + + val = (scale & AR933X_UART_CLK_SCALE_M) + << AR933X_UART_CLK_SCALE_S; + val |= (step & AR933X_UART_CLK_STEP_M) + << AR933X_UART_CLK_STEP_S; + writel(val, priv->regs + AR933X_UART_CLK_REG); + + return 0; +} + +static int ar933x_serial_putc(struct udevice *dev, const char c) +{ + struct ar933x_serial_priv *priv = dev_get_priv(dev); + u32 data; + + data = readl(priv->regs + AR933X_UART_DATA_REG); + if (!(data & AR933X_UART_DATA_TX_CSR)) + return -EAGAIN; + + data = (u32)c | AR933X_UART_DATA_TX_CSR; + writel(data, priv->regs + AR933X_UART_DATA_REG); + + return 0; +} + +static int ar933x_serial_getc(struct udevice *dev) +{ + struct ar933x_serial_priv *priv = dev_get_priv(dev); + u32 data; + + data = readl(priv->regs + AR933X_UART_DATA_REG); + if (!(data & AR933X_UART_DATA_RX_CSR)) + return -EAGAIN; + + writel(AR933X_UART_DATA_RX_CSR, priv->regs + AR933X_UART_DATA_REG); + return data & AR933X_UART_DATA_TX_RX_MASK; +} + +static int ar933x_serial_pending(struct udevice *dev, bool input) +{ + struct ar933x_serial_priv *priv = dev_get_priv(dev); + u32 data; + + data = readl(priv->regs + AR933X_UART_DATA_REG); + if (input) + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0; + else + return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1; +} + +static int ar933x_serial_probe(struct udevice *dev) +{ + struct ar933x_serial_priv *priv = dev_get_priv(dev); + struct udevice *pinctrl; + fdt_addr_t addr; + u32 val; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) + return ret; + ret = pinctrl_get_periph_id(pinctrl, dev); + if (ret < 0) + return ret; + ret = pinctrl_request(pinctrl, ret, 0); + if (ret < 0) + return ret; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_physmem(addr, + AR933X_UART_SIZE, + MAP_NOCACHE); + + /* + * UART controller configuration: + * - no DMA + * - no interrupt + * - DCE mode + * - no flow control + * - set RX ready oride + * - set TX ready oride + */ + val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) | + AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE; + writel(val, priv->regs + AR933X_UART_CS_REG); + return 0; +} + +static const struct dm_serial_ops ar933x_serial_ops = { + .putc = ar933x_serial_putc, + .pending = ar933x_serial_pending, + .getc = ar933x_serial_getc, + .setbrg = ar933x_serial_setbrg, +}; + +static const struct udevice_id ar933x_serial_ids[] = { + { .compatible = "qca,ar9330-uart" }, + { } +}; + +U_BOOT_DRIVER(serial_ar933x) = { + .name = "serial_ar933x", + .id = UCLASS_SERIAL, + .of_match = ar933x_serial_ids, + .priv_auto_alloc_size = sizeof(struct ar933x_serial_priv), + .probe = ar933x_serial_probe, + .ops = &ar933x_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#ifdef CONFIG_DEBUG_UART_AR933X + +#include <debug_uart.h> + +static inline void _debug_uart_init(void) +{ + void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE; + u32 val, scale, step; + + /* + * UART controller configuration: + * - no DMA + * - no interrupt + * - DCE mode + * - no flow control + * - set RX ready oride + * - set TX ready oride + */ + val = (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) | + AR933X_UART_CS_TX_RDY_ORIDE | AR933X_UART_CS_RX_RDY_ORIDE; + writel(val, regs + AR933X_UART_CS_REG); + + ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE, &scale, &step); + + val = (scale & AR933X_UART_CLK_SCALE_M) + << AR933X_UART_CLK_SCALE_S; + val |= (step & AR933X_UART_CLK_STEP_M) + << AR933X_UART_CLK_STEP_S; + writel(val, regs + AR933X_UART_CLK_REG); +} + +static inline void _debug_uart_putc(int c) +{ + void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE; + u32 data; + + do { + data = readl(regs + AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_TX_CSR)); + + data = (u32)c | AR933X_UART_DATA_TX_CSR; + writel(data, regs + AR933X_UART_DATA_REG); +} + +DEBUG_UART_FUNCS + +#endif -- 1.9.1

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[U-Boot] [PATCH 0/8] usb: Move DWC3 and some gadget options to Kconfig
by Semen Protsenko 11 Apr '16

11 Apr '16

Hi All, This patch series move next options to Kconfigs/defconfigs: - CONFIG_USB_DWC3* - CONFIG_USB_GADGET_VBUS_DRAW - CONFIG_USB_GADGET_DUALSPEED (partially, only for DWC3 platforms for now) - CONFIG_USB_GADGET_DOWNLOAD - CONFIG_G_DNL_* All defconfig files were post-processed via "make savedefconfig" rule to keep correct order of options in defconfigs. The whole series was tested using buildman tool for all arm boards.

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[U-Boot] [uboot] [PATCH 1/7] drivers: net: cpsw: Add readinf of DT phy-handle node
by Dan Murphy 11 Apr '16

11 Apr '16

Add the ability to read the phy-handle node of the cpsw slave. Upon reading this handle the phy-id can be stored based on the reg node in the DT. The phy-handle also needs to be stored and passed to the phy to access any phy data that is available. Signed-off-by: Dan Murphy <dmurphy(a)ti.com> --- drivers/net/cpsw.c | 18 ++++++++++++++++-- include/cpsw.h | 1 + 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 7104754..8ee33a6 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -965,6 +965,9 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) phydev->supported &= supported; phydev->advertising = phydev->supported; + if (slave->data->phy_of_handle) + phydev->dev->of_offset = slave->data->phy_of_handle; + priv->phydev = phydev; phy_config(phydev); @@ -1217,8 +1220,19 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) if (phy_mode) priv->data.slave_data[slave_index].phy_if = phy_get_interface_by_name(phy_mode); - fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2); - priv->data.slave_data[slave_index].phy_addr = phy_id[1]; + + priv->data.slave_data[slave_index].phy_of_handle = + fdtdec_lookup_phandle(fdt, subnode, "phy-handle"); + + if (priv->data.slave_data[slave_index].phy_of_handle) { + priv->data.slave_data[slave_index].phy_addr = + fdtdec_get_int(gd->fdt_blob, + priv->data.slave_data[slave_index].phy_of_handle, + "reg", -1); + } else { + fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2); + priv->data.slave_data[slave_index].phy_addr = phy_id[1]; + } slave_index++; } diff --git a/include/cpsw.h b/include/cpsw.h index cf1d30b..ba9d068 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -21,6 +21,7 @@ struct cpsw_slave_data { u32 sliver_reg_ofs; int phy_addr; int phy_if; + int phy_of_handle; }; enum { -- 2.8.0.rc3

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[U-Boot] [PATCH] GPIO: pca953x: Remove compilation warnings on arm64
by Michal Simek 11 Apr '16

11 Apr '16

Warnings: w+../drivers/gpio/pca953x.c: In function ‘do_pca953x’: w+../drivers/gpio/pca953x.c:220:5: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] w+../drivers/gpio/pca953x.c:233:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/gpio/pca953x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 932dfe9f34e1..238e02805cb6 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -217,7 +217,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* All commands but "device" require 'maxargs' arguments */ if (!c || !((argc == (c->maxargs)) || - (((int)c->cmd == PCA953X_CMD_DEVICE) && + (((long)c->cmd == PCA953X_CMD_DEVICE) && (argc == (c->maxargs - 1))))) { return CMD_RET_USAGE; } @@ -230,7 +230,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc > 3) ul_arg3 = simple_strtoul(argv[3], NULL, 16) & 0x1; - switch ((int)c->cmd) { + switch ((long)c->cmd) { #ifdef CONFIG_CMD_PCA953X_INFO case PCA953X_CMD_INFO: ret = pca953x_info(chip); -- 1.9.1

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[U-Boot] [PATCH] ARM64: zynqmp: Enable pca953x driver for zcu102
by Michal Simek 11 Apr '16

11 Apr '16

zcu102 has two pca953x on i2c bus 0. Chips 0x20 and 0x21. Enable option to work with these two chips. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/xilinx_zynqmp_zcu102.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h index 4f580207bb30..30db2e453246 100644 --- a/include/configs/xilinx_zynqmp_zcu102.h +++ b/include/configs/xilinx_zynqmp_zcu102.h @@ -37,6 +37,10 @@ } #define CONFIG_SYS_I2C_ZYNQ +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO + #define CONFIG_AHCI #define CONFIG_SATA_CEVA -- 1.9.1

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[U-Boot] Ethernet via USB on Sinlinx SinA33
by Quentin Schulz 11 Apr '16

11 Apr '16

Hi, I am trying to get Ethernet to work through the USB port of the Sinlinx SinA33 on U-Boot to use TFTP to get the kernel and dtb files. However, I am getting 'data abort' when using dhcp or tftp after adding: #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX to include/configs/sunxi-common.h and checking CONFIG_USB_EHCI_HCD as told in the documentation [1] I tested this configuration with the C.H.I.P. and it is working well. Steps to reproduce: 1) Add the following lines to include/configs/sunxi-common.h: #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX 2) make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- Sinlinx_SinA33_defconfig 3) make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- menuconfig 4) Check CONFIG_USB_EHCI_HC and save configuration 5) make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j$(nproc) 6) Prepare SDCard: sudo dd if=u-boot-sunxi-with-spl.bin of=/dev/sdX bs=1024 seek=8 7) Boot the board and run dhcp or tftp 8) Get 'data abort' and board gets reset (ethact is also not defined) The log file is attached. Thank you, Quentin [1] https://github.com/lentinj/u-boot/blob/master/doc/README.usb#L132

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[U-Boot] [PATCH] USB: g_dnl: Change device class
by John Tobias 11 Apr '16

11 Apr '16

The USB Mass Storage (ums) works in Windows, Linux and OS X (EL Capitan). But, not in OS X (Yosemite). By applying the said patch, it extends the ums support. Signed-off-by: John Tobias <john.tobias.ph(a)gmail.com> --- drivers/usb/gadget/g_dnl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index 2fa6da4..bd3aad9 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -58,8 +58,8 @@ static struct usb_device_descriptor device_desc = { .bDescriptorType = USB_DT_DEVICE, .bcdUSB = __constant_cpu_to_le16(0x0200), - .bDeviceClass = USB_CLASS_COMM, - .bDeviceSubClass = 0x02, /*0x02:CDC-modem , 0x00:CDC-serial*/ + .bDeviceClass = USB_CLASS_PER_INTERFACE, + .bDeviceSubClass = 0, /*0x02:CDC-modem , 0x00:CDC-serial*/ .idVendor = __constant_cpu_to_le16(CONFIG_G_DNL_VENDOR_NUM), .idProduct = __constant_cpu_to_le16(CONFIG_G_DNL_PRODUCT_NUM), -- 2.8.1

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[U-Boot] [PATCH 01/10] ddr: altera: Replace ad-hoc constant with macro
by Marek Vasut 11 Apr '16

11 Apr '16

The bit 22 is in fact DQS tracking enable bit (dqstrken) and there is a macro for this bit already, so use it. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Chin Liang See <clsee(a)altera.com> --- drivers/ddr/altera/sequencer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 79c265f..34b1aa7 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -3486,7 +3486,7 @@ static int run_mem_calibrate(void) writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status); /* Stop tracking manager. */ - clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22); + clrbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK); phy_mgr_initialize(); rw_mgr_mem_initialize(); @@ -3507,7 +3507,7 @@ static int run_mem_calibrate(void) writel(0x2, &phy_mgr_cfg->mux_sel); /* Start tracking manager. */ - setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22); + setbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK); return pass; } -- 2.7.0

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