March 2016 - U-Boot

[U-Boot] [U-BOOT.V2] usb: xhci: Fix vendor command error if the request
by Anand Moon 14 Mar '16

14 Mar '16

From: Ted Chen <tedchen(a)realtek.com> From: Ted Chen <tedchen(a)realtek.com> type is USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION. To: marex(a)denx.de, swarren(a)nvidia.com, u-boot(a)lists.denx.de Cc: linux.amoon(a)gmail.com, Ted Chen <tedchen(a)realtek.com> Add a condition of set_address and set_configuration to check if the request is standardized. Signed-off-by: Ted Chen <tedchen(a)realtek.com> --- Resend this patch it some how got missed Changes since v1: None. Tested on Odroid XU4: with Ethernet USB3.0 RT8153-VB --- drivers/usb/host/xhci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index ca598aa..cb8a04b 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -941,10 +941,12 @@ static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe, if (usb_pipedevice(pipe) == ctrl->rootdev) return xhci_submit_root(udev, pipe, buffer, setup); - if (setup->request == USB_REQ_SET_ADDRESS) + if (setup->request == USB_REQ_SET_ADDRESS && + (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) return xhci_address_device(udev, root_portnr); - if (setup->request == USB_REQ_SET_CONFIGURATION) { + if (setup->request == USB_REQ_SET_CONFIGURATION && + (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) { ret = xhci_set_configuration(udev); if (ret) { puts("Failed to configure xHCI endpoint\n"); -- 1.9.1

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Re: [U-Boot] Olimex-A20-EVB ethernet stops working with latest U-boot, works with tag v2016.01
by Hans de Goede 14 Mar '16

14 Mar '16

Hi, On 13-03-16 12:14, Karsten Merker wrote: > On Wed, Mar 09, 2016 at 02:39:11PM -0700, Simon Glass wrote: >> On 9 March 2016 at 14:04, Karsten Merker <merker(a)debian.org> wrote: >>> [Olimex A20-SOM-EVB: ethernet non-functional with current u-boot >>> git head, but no problems with v2016.01] > [...] >>> I am not the original poster, but I have bisected the issue down >>> to the following commit: >>> >>> commit c32a6fd07b1839e4a45729587ebc8e1c55601a4d >>> Author: Simon Glass <sjg(a)chromium.org> >>> Date: Sun Jan 17 14:51:56 2016 -0700 >>> >>> net: Don't call board/cpu_eth_init() with driver model >>> >>> We should avoid weak functions with driver model. Existing boards that use >>> driver model don't need them, so let's kill them off. >>> >>> Signed-off-by: Simon Glass <sjg(a)chromium.org> >>> Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com> >>> Acked-by: Joe Hershberger <joe.hershberger(a)ni.com> >> >> Is this board-specific init, or sunxi-specific? > > Hello Simon, > > I am unsure whether I understand your question correctly. There > is only one cpu_eth_init() function for sunxi-based devices, but > its behaviour depends on several configuration options. Some of > those depend on the SoC type (and are thereby indirectly > board-specific) and some of those (e.g. the GPIO pin controlling > the regulator that powers the PHY) are directly board-specific. > >> Can you just call the init on start-up, instead of from the >> Ethernet driver? > > From a look at the source in arch/arm/cpu/armv7/sunxi/board.c and > board/sunxi/gmac.c I guess that should be possible, but I don't > know enough about u-boot's internals to really assess that. > > Hans, could you take a look at the issue? Yes I've had this thread on my radar / todo the whole time already, not sure when I'll get around to it. I'll make sure to get this fixed soon though, as we'll have a new u-boot release soonish. Regards, Hans

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[U-Boot] [PATCH 1/3] armv8/ls1043aqds: fix fman ucode address to an offset in QSPI flash
by Gong Qianyu 14 Mar '16

14 Mar '16

Modify the value as the SPI interface is changed. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)nxp.com> --- include/configs/ls1043a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 7018cb5..c78ba47 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -222,7 +222,7 @@ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_QE_FW_IN_SPIFLASH -#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_SYS_FMAN_FW_ADDR 0xd0000 #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 1000000 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v2 00/51] x86: Add support for samus
by Simon Glass 14 Mar '16

14 Mar '16

This series adds support for samus, the Chromebook Pixel 2015. Since it is only the second board added that does not use an FSP, there is quite a bit of refactoring involved to avoid code duplication. Samus uses roughly the same binary blobs as link, except now there is one more called the reference code binary. The only available binary for this is a coreboot 'rmodule' extracted from flash. This is a simplified ELF format so it fairly easy to load and use. It is also possible to boot U-Boot from coreboot on samus. This works well but for a delay for non-existent IDE on start-up. The standard build does not work with binaries taken from flash, so it isn't easy to replicate this - you'll just have to take my word for it. I am working on getting that figured out - coreboot recently gained upstream support for loading U-Boot as a payload, so it should be possible to get this working nicely before long. In any case much of the code comes from coreboot - individual files are credited with their source. Perhaps the main value of this series is the improved non-FSP support and additions for broadwell, which samus uses. It should make it easier to add support for future non-FSP platforms. Changes in v2: - Use a #define for the output flush command - Adjust the code order slightly - Simplify the code in serial_initialize() - Use gd->arch.x86_mask to get the stepping value - Rename microcode_intel.c to microcode.c - Use capitals for header guard - Use capitals for header guard - Move cougarcanyon lpc_common.h include to this patch - Use capitals for header guard - Use capitals for header guard - Rename sdram_common.c to mrc.c - Rename sdram to mrc - Use setio_32() instead of setio_le32(), etc. - Add Kconfig help for the moved options - Fix tab indentation - Don't try to read microcode version on quark - Use gd->arch.x86_device instead of reading the device ID again - Rename subject to 'core' instead of 'code' - Fix micrcode typo - Don't try to update microcode on FSP platforms - Add GPIO output definition for a1 and a6 - Use setio_32() instead of setio_le32(), etc. - Fix 'PCB' typo (should be 'PCH') - Use setio_32() instead of setio_le32(), etc. - Use capitals for header guard - Use capitals for header guard - Use capitals for header guard - Fix comment style - Use capitals for header guard - Rename sdram to mrc - Use setio_32() instead of setio_le32(), etc. - Fix 'configure' typo - Correct naming of Intel platforms Simon Glass (51): dm: timer: Correct timer init ordering after relocation arm: Add a 64-bit division routine to the private library dhry: Correct dhrystone calculation for fast machines syscon: Avoid returning a device on failure input: i8042: Make sure the keyboard is enabled x86: Allow use of serial soon after relocation x86: cpu: Add functions to return the family and stepping x86: Move cache-as-RAM code into a common location x86: Move microcode code to a common location x86: Create a common header for Intel register access x86: Add the root-complex block to common intel registers x86: Move common LPC code to its own place x86: Move common CPU code to its own place x86: Rename PORT_RESET to IO_PORT_RESET x86: Move Intel Management Engine code to a common place x86: ivybridge: Drop sandybridge_early_init() x86: Move common PCH code into a common place x86: Add common SDRAM-init code x86: ivybridge: Convert to use the common SDRAM code x86: dts: Drop memory SPD compatible string x86: Add macros to clear and set I/O bits x86: Allow I/O functions to use pointers x86: Move common MRC Kconfig options to the common file x86: Record the CPU details when starting each core x86: ivybridge: Show microcode version for each core x86: Update microcode for secondary CPUs x86: link: Add pin configuration to the device tree x86: Add an ICH6 pin configuration driver x86: gpio: Allow the pinctrl driver to set up the pin config x86: Drop all the old pin configuration code x86: Add support for running Intel reference code x86: dts: Update the pinctrl binding a little x86: Add basic support for broadwell x86: broadwell: Add a PCH driver x86: broadwell: Add a pinctrl driver x86: broadwell: Add a SATA driver x86: broadwell: Add a northbridge driver x86: broadwell: Add an LPC driver x86: broadwell: Add reference code support x86: broadwell: Add power-control support x86: broadwell: Add support for SDRAM setup x86: broadwell: Add a GPIO driver x86: broadwell: Add support for high-speed I/O lane with ME x86: Support a chained-boot development flow x86: broadwell: Add video support x86: Add a default address for reference code x86: Use white on black for the console on chromebooks x86: Update README for new developments x86: Add a function to set the IOAPIC ID x86: Fix a header nit in x86-chromebook.h x86: Add support for the samus chromebook Makefile | 14 +- arch/arm/lib/Makefile | 3 +- arch/arm/lib/_uldivmod.S | 245 +++++++ arch/x86/Kconfig | 73 ++ arch/x86/cpu/Makefile | 2 + arch/x86/cpu/broadwell/Kconfig | 30 + arch/x86/cpu/broadwell/Makefile | 17 + arch/x86/cpu/broadwell/cpu.c | 761 ++++++++++++++++++++ arch/x86/cpu/broadwell/iobp.c | 144 ++++ arch/x86/cpu/broadwell/lpc.c | 77 ++ arch/x86/cpu/broadwell/me.c | 57 ++ arch/x86/cpu/broadwell/northbridge.c | 59 ++ arch/x86/cpu/broadwell/pch.c | 540 ++++++++++++++ arch/x86/cpu/broadwell/pinctrl_broadwell.c | 278 +++++++ arch/x86/cpu/broadwell/power_state.c | 89 +++ arch/x86/cpu/broadwell/refcode.c | 113 +++ arch/x86/cpu/broadwell/sata.c | 269 +++++++ arch/x86/cpu/broadwell/sdram.c | 307 ++++++++ arch/x86/cpu/cpu.c | 15 +- arch/x86/cpu/intel_common/Makefile | 16 + arch/x86/cpu/{ivybridge => intel_common}/car.S | 4 +- arch/x86/cpu/intel_common/cpu.c | 111 +++ arch/x86/cpu/intel_common/lpc.c | 100 +++ .../cpu/{ivybridge => intel_common}/me_status.c | 20 +- .../microcode_intel.c => intel_common/microcode.c} | 11 +- arch/x86/cpu/intel_common/mrc.c | 271 +++++++ arch/x86/cpu/intel_common/pch_common.c | 25 + .../{ivybridge => intel_common}/report_platform.c | 2 +- arch/x86/cpu/ioapic.c | 16 + arch/x86/cpu/ivybridge/Kconfig | 27 +- arch/x86/cpu/ivybridge/Makefile | 4 - arch/x86/cpu/ivybridge/bd82x6x.c | 17 +- arch/x86/cpu/ivybridge/cpu.c | 86 +-- arch/x86/cpu/ivybridge/early_me.c | 31 +- arch/x86/cpu/ivybridge/gma.c | 1 + arch/x86/cpu/ivybridge/lpc.c | 77 +- arch/x86/cpu/ivybridge/model_206ax.c | 3 +- arch/x86/cpu/ivybridge/northbridge.c | 5 +- arch/x86/cpu/ivybridge/sata.c | 47 +- arch/x86/cpu/ivybridge/sdram.c | 400 +++-------- arch/x86/cpu/mp_init.c | 11 +- arch/x86/cpu/start.S | 79 ++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_link.dts | 156 +++- arch/x86/dts/chromebook_samus.dts | 628 ++++++++++++++++ arch/x86/include/asm/arch-broadwell/cpu.h | 48 ++ arch/x86/include/asm/arch-broadwell/gpio.h | 91 +++ arch/x86/include/asm/arch-broadwell/iomap.h | 53 ++ arch/x86/include/asm/arch-broadwell/lpc.h | 32 + arch/x86/include/asm/arch-broadwell/me.h | 200 ++++++ arch/x86/include/asm/arch-broadwell/pch.h | 153 ++++ arch/x86/include/asm/arch-broadwell/pei_data.h | 177 +++++ arch/x86/include/asm/arch-broadwell/pm.h | 129 ++++ arch/x86/include/asm/arch-broadwell/rcb.h | 58 ++ arch/x86/include/asm/arch-broadwell/spi.h | 87 +++ arch/x86/include/asm/arch-ivybridge/me.h | 333 +-------- arch/x86/include/asm/arch-ivybridge/pch.h | 62 -- arch/x86/include/asm/arch-ivybridge/sandybridge.h | 7 - arch/x86/include/asm/cpu.h | 27 + arch/x86/include/asm/cpu_common.h | 35 + arch/x86/include/asm/global_data.h | 24 + arch/x86/include/asm/gpio.h | 141 ---- arch/x86/include/asm/intel_regs.h | 28 + arch/x86/include/asm/io.h | 34 +- arch/x86/include/asm/ioapic.h | 2 + arch/x86/include/asm/lpc_common.h | 59 ++ arch/x86/include/asm/me_common.h | 372 ++++++++++ .../include/asm/{arch-ivybridge => }/microcode.h | 12 + arch/x86/include/asm/mrc_common.h | 55 ++ arch/x86/include/asm/pch_common.h | 56 ++ arch/x86/include/asm/processor.h | 2 +- arch/x86/include/asm/report_platform.h | 19 + arch/x86/lib/Makefile | 1 + arch/x86/lib/fsp/fsp_car.S | 2 + arch/x86/lib/pinctrl_ich6.c | 216 ++++++ board/coreboot/coreboot/coreboot.c | 5 - board/efi/efi-x86/efi.c | 5 - board/google/Kconfig | 13 + board/google/chromebook_link/link.c | 138 ---- board/google/chromebook_samus/Kconfig | 40 ++ board/google/chromebook_samus/MAINTAINERS | 6 + board/google/chromebook_samus/Makefile | 7 + board/google/chromebook_samus/samus.c | 18 + board/google/chromebox_panther/panther.c | 4 - board/intel/bayleybay/bayleybay.c | 5 - board/intel/cougarcanyon2/cougarcanyon2.c | 6 +- board/intel/crownbay/crownbay.c | 5 - board/intel/galileo/galileo.c | 5 - board/intel/minnowmax/minnowmax.c | 8 - common/board_f.c | 7 + common/board_r.c | 4 +- configs/bayleybay_defconfig | 2 + configs/chromebook_samus_defconfig | 51 ++ configs/cougarcanyon2_defconfig | 2 + configs/crownbay_defconfig | 2 + configs/galileo_defconfig | 2 + configs/minnowmax_defconfig | 6 +- doc/README.x86 | 97 ++- .../gpio/intel,x86-broadwell-pinctrl.txt | 208 ++++++ .../gpio/intel,x86-pinctrl.txt | 22 +- drivers/core/syscon-uclass.c | 1 + drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/intel_broadwell_gpio.c | 198 +++++ drivers/gpio/intel_ich6_gpio.c | 191 +---- drivers/input/i8042.c | 4 + drivers/serial/serial-uclass.c | 2 +- drivers/video/Kconfig | 14 +- drivers/video/Makefile | 2 + drivers/video/broadwell_igd.c | 797 +++++++++++++++++++++ drivers/video/i915_reg.h | 362 ++++++++++ include/configs/chromebook_samus.h | 29 + include/configs/x86-chromebook.h | 8 +- include/dt-bindings/gpio/x86-gpio.h | 12 + include/fdtdec.h | 2 - include/i8042.h | 1 + lib/dhry/cmd_dhry.c | 8 +- lib/fdtdec.c | 2 - 118 files changed, 8550 insertions(+), 1518 deletions(-) create mode 100644 arch/arm/lib/_uldivmod.S create mode 100644 arch/x86/cpu/broadwell/Kconfig create mode 100644 arch/x86/cpu/broadwell/Makefile create mode 100644 arch/x86/cpu/broadwell/cpu.c create mode 100644 arch/x86/cpu/broadwell/iobp.c create mode 100644 arch/x86/cpu/broadwell/lpc.c create mode 100644 arch/x86/cpu/broadwell/me.c create mode 100644 arch/x86/cpu/broadwell/northbridge.c create mode 100644 arch/x86/cpu/broadwell/pch.c create mode 100644 arch/x86/cpu/broadwell/pinctrl_broadwell.c create mode 100644 arch/x86/cpu/broadwell/power_state.c create mode 100644 arch/x86/cpu/broadwell/refcode.c create mode 100644 arch/x86/cpu/broadwell/sata.c create mode 100644 arch/x86/cpu/broadwell/sdram.c create mode 100644 arch/x86/cpu/intel_common/Makefile rename arch/x86/cpu/{ivybridge => intel_common}/car.S (98%) create mode 100644 arch/x86/cpu/intel_common/cpu.c create mode 100644 arch/x86/cpu/intel_common/lpc.c rename arch/x86/cpu/{ivybridge => intel_common}/me_status.c (93%) rename arch/x86/cpu/{ivybridge/microcode_intel.c => intel_common/microcode.c} (96%) create mode 100644 arch/x86/cpu/intel_common/mrc.c create mode 100644 arch/x86/cpu/intel_common/pch_common.c rename arch/x86/cpu/{ivybridge => intel_common}/report_platform.c (98%) create mode 100644 arch/x86/dts/chromebook_samus.dts create mode 100644 arch/x86/include/asm/arch-broadwell/cpu.h create mode 100644 arch/x86/include/asm/arch-broadwell/gpio.h create mode 100644 arch/x86/include/asm/arch-broadwell/iomap.h create mode 100644 arch/x86/include/asm/arch-broadwell/lpc.h create mode 100644 arch/x86/include/asm/arch-broadwell/me.h create mode 100644 arch/x86/include/asm/arch-broadwell/pch.h create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h create mode 100644 arch/x86/include/asm/arch-broadwell/pm.h create mode 100644 arch/x86/include/asm/arch-broadwell/rcb.h create mode 100644 arch/x86/include/asm/arch-broadwell/spi.h create mode 100644 arch/x86/include/asm/cpu_common.h create mode 100644 arch/x86/include/asm/intel_regs.h create mode 100644 arch/x86/include/asm/lpc_common.h create mode 100644 arch/x86/include/asm/me_common.h rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (63%) create mode 100644 arch/x86/include/asm/mrc_common.h create mode 100644 arch/x86/include/asm/pch_common.h create mode 100644 arch/x86/include/asm/report_platform.h create mode 100644 arch/x86/lib/pinctrl_ich6.c create mode 100644 board/google/chromebook_samus/Kconfig create mode 100644 board/google/chromebook_samus/MAINTAINERS create mode 100644 board/google/chromebook_samus/Makefile create mode 100644 board/google/chromebook_samus/samus.c create mode 100644 configs/chromebook_samus_defconfig create mode 100644 doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt create mode 100644 drivers/gpio/intel_broadwell_gpio.c create mode 100644 drivers/video/broadwell_igd.c create mode 100644 drivers/video/i915_reg.h create mode 100644 include/configs/chromebook_samus.h -- 2.7.0.rc3.207.g0ac5344

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[U-Boot] [PATCH 00/69] x86: Add support for samus
by Simon Glass 14 Mar '16

14 Mar '16

This series adds support for samus, the Chromebook Pixel 2015. Since it is only the second board added that does not use an FSP, there is quite a bit of refactoring involved to avoid code duplication. Samus uses roughly the same binary blobs as link, except now there is one more called the reference code binary. The only available binary for this is a coreboot 'rmodule' extracted from flash. This is a simplified ELF format so it fairly easy to load and use. It is also possible to boot U-Boot from coreboot on samus. This works well but for a delay for non-existent IDE on start-up. The standard build does not work with binaries taken from flash, so it isn't easy to replicate this - you'll just have to take my word for it. I am working on getting that figured out - coreboot recently gained upstream support for loading U-Boot as a payload, so it should be possible to get this working nicely before long. In any case much of the code comes from coreboot - individual files are credited with their source. Perhaps the main value of this series is the improved non-FSP support and additions for broadwell, which samus uses. It should make it easier to add support for future non-FSP platforms. Simon Glass (69): dm: timer: Correct timer init ordering after relocation arm: Add a 64-bit division routine to the private library dhry: Correct dhrystone calculation for fast machines syscon: Avoid returning a device on failure video: Allow simple-panel to be used without regulators cpu: Add support for microcode version and CPU ID gpio: Add a function to obtain a GPIO vector value gpio: Use const where possible pci: Add functions to update PCI configuration registers pci: Correct a few comments and nits input: i8042: Make sure the keyboard is enabled malloc_simple: Add a little more debugging x86: Allow use of serial soon after relocation x86: cpu: Make the vendor table const x86: cpu: Add functions to return the family and stepping x86: Move cache-as-RAM code into a common location x86: Move microcode code to a common location x86: Create a common header for Intel register access x86: Add the root-complex block to common intel registers x86: Move common LPC code to its own place x86: Add some more common MSR indexes x86: Move common CPU code to its own place x86: Rename PORT_RESET to IO_PORT_RESET x86: Move Intel Management Engine code to a common place x86: ivybridge: Drop sandybridge_early_init() x86: Move common PCH code into a common place x86: link: Add required GPIO properties x86: dts: link: Move SPD info into the memory controller x86: dts: link: Add board ID GPIOs x86: gpio: Correct GPIO setup ordering x86: Add common SDRAM-init code x86: ivybridge: Convert to use the common SDRAM code x86: dts: Drop memory SPD compatible string x86: Add a script to aid code conversion from coreboot x86: Correct duplicate POST values x86: Add macros to clear and set I/O bits x86: Allow I/O functions to use pointers x86: Move common MRC Kconfig options to the common file x86: Tidy up mp_init to reduce duplication x86: Record the CPU details when starting each core x86: ivybridge: Show microcode version for each code x86: Add comments to the SIPI vector x86: Update microcode for secondary CPUs x86: link: Add pin configuration to the device tree x86: Add an ICH6 pin configuration driver x86: gpio: Allow the pinctrl driver to set up the pin config x86: Drop all the old pin configuration code x86: Add support for running Intel reference code x86: dts: Update the pinctrl binding a little x86: Add basic support for broadwell x86: broadwell: Add a few microcode files x86: broadwell: Add a PCH driver x86: broadwell: Add a pinctrl driver x86: broadwell: Add a SATA driver x86: broadwell: Add a northbridge driver x86: broadwell: Add an LPC driver x86: broadwell: Add reference code support x86: broadwell: Add power-control support x86: broadwell: Add support for SDRAM setup x86: broadwell: Add a GPIO driver x86: broadwell: Add support for high-speed I/O lane with ME x86: Support a chained-boot development flow x86: broadwell: Add video support x86: Add a default address for reference code x86: Use white on black for the console on chromebooks x86: Update README for new developments x86: Add a function to set the IOAPIC ID x86: Fix a header nit in x86-chromebook.h x86: Add support for the samus chromebook Makefile | 14 +- arch/arm/lib/Makefile | 3 +- arch/arm/lib/_uldivmod.S | 245 ++++ arch/x86/Kconfig | 51 + arch/x86/cpu/Makefile | 2 + arch/x86/cpu/broadwell/Kconfig | 30 + arch/x86/cpu/broadwell/Makefile | 17 + arch/x86/cpu/broadwell/cpu.c | 761 +++++++++++ arch/x86/cpu/broadwell/iobp.c | 144 +++ arch/x86/cpu/broadwell/lpc.c | 77 ++ arch/x86/cpu/broadwell/me.c | 57 + arch/x86/cpu/broadwell/northbridge.c | 59 + arch/x86/cpu/broadwell/pch.c | 540 ++++++++ arch/x86/cpu/broadwell/pinctrl_broadwell.c | 278 ++++ arch/x86/cpu/broadwell/power_state.c | 89 ++ arch/x86/cpu/broadwell/refcode.c | 108 ++ arch/x86/cpu/broadwell/sata.c | 269 ++++ arch/x86/cpu/broadwell/sdram.c | 307 +++++ arch/x86/cpu/cpu.c | 17 +- arch/x86/cpu/intel_common/Makefile | 16 + arch/x86/cpu/{ivybridge => intel_common}/car.S | 4 +- arch/x86/cpu/intel_common/cpu_common.c | 111 ++ arch/x86/cpu/intel_common/lpc_common.c | 102 ++ .../cpu/{ivybridge => intel_common}/me_status.c | 20 +- .../{ivybridge => intel_common}/microcode_intel.c | 6 +- arch/x86/cpu/intel_common/pch_common.c | 25 + .../{ivybridge => intel_common}/report_platform.c | 2 +- arch/x86/cpu/intel_common/sdram_common.c | 271 ++++ arch/x86/cpu/ioapic.c | 16 + arch/x86/cpu/ivybridge/Kconfig | 27 +- arch/x86/cpu/ivybridge/Makefile | 4 - arch/x86/cpu/ivybridge/bd82x6x.c | 17 +- arch/x86/cpu/ivybridge/cpu.c | 86 +- arch/x86/cpu/ivybridge/early_me.c | 31 +- arch/x86/cpu/ivybridge/gma.c | 1 + arch/x86/cpu/ivybridge/lpc.c | 77 +- arch/x86/cpu/ivybridge/model_206ax.c | 8 +- arch/x86/cpu/ivybridge/northbridge.c | 5 +- arch/x86/cpu/ivybridge/sata.c | 47 +- arch/x86/cpu/ivybridge/sdram.c | 400 ++---- arch/x86/cpu/mp_init.c | 90 +- arch/x86/cpu/sipi_vector.S | 1 + arch/x86/cpu/start.S | 79 ++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_link.dts | 379 ++++-- arch/x86/dts/chromebook_samus.dts | 628 +++++++++ arch/x86/dts/microcode/m7240651_0000001c.dtsi | 1328 ++++++++++++++++++++ arch/x86/dts/microcode/mc0306d4_00000018.dtsi | 944 ++++++++++++++ arch/x86/include/asm/arch-broadwell/cpu.h | 48 + arch/x86/include/asm/arch-broadwell/gpio.h | 91 ++ arch/x86/include/asm/arch-broadwell/iomap.h | 53 + arch/x86/include/asm/arch-broadwell/lpc.h | 32 + arch/x86/include/asm/arch-broadwell/me.h | 200 +++ arch/x86/include/asm/arch-broadwell/pch.h | 153 +++ arch/x86/include/asm/arch-broadwell/pei_data.h | 177 +++ arch/x86/include/asm/arch-broadwell/pm.h | 129 ++ arch/x86/include/asm/arch-broadwell/rcb.h | 58 + arch/x86/include/asm/arch-broadwell/spi.h | 87 ++ arch/x86/include/asm/arch-ivybridge/me.h | 333 +---- arch/x86/include/asm/arch-ivybridge/model_206ax.h | 17 - arch/x86/include/asm/arch-ivybridge/pch.h | 62 - arch/x86/include/asm/arch-ivybridge/sandybridge.h | 7 - arch/x86/include/asm/cpu.h | 27 + arch/x86/include/asm/cpu_common.h | 35 + arch/x86/include/asm/global_data.h | 24 + arch/x86/include/asm/gpio.h | 138 +- arch/x86/include/asm/intel_regs.h | 28 + arch/x86/include/asm/io.h | 34 +- arch/x86/include/asm/ioapic.h | 2 + arch/x86/include/asm/lpc_common.h | 59 + arch/x86/include/asm/me_common.h | 372 ++++++ .../include/asm/{arch-ivybridge => }/microcode.h | 12 + arch/x86/include/asm/msr-index.h | 41 +- arch/x86/include/asm/pch_common.h | 56 + arch/x86/include/asm/post.h | 4 +- arch/x86/include/asm/processor.h | 2 +- arch/x86/include/asm/report_platform.h | 19 + arch/x86/include/asm/sdram_common.h | 56 + arch/x86/include/asm/sipi.h | 1 + arch/x86/lib/Makefile | 1 + arch/x86/lib/fsp/fsp_car.S | 2 + arch/x86/lib/pinctrl_ich6.c | 216 ++++ board/coreboot/coreboot/coreboot.c | 5 - board/efi/efi-x86/efi.c | 5 - board/google/Kconfig | 13 + board/google/chromebook_link/link.c | 138 -- board/google/chromebook_samus/Kconfig | 40 + board/google/chromebook_samus/MAINTAINERS | 6 + board/google/chromebook_samus/Makefile | 7 + board/google/chromebook_samus/samus.c | 18 + board/google/chromebox_panther/panther.c | 4 - board/intel/bayleybay/bayleybay.c | 5 - board/intel/cougarcanyon2/cougarcanyon2.c | 6 +- board/intel/crownbay/crownbay.c | 5 - board/intel/galileo/galileo.c | 5 - board/intel/minnowmax/minnowmax.c | 8 - cmd/cpu.c | 7 + common/board_f.c | 7 + common/board_r.c | 4 +- common/malloc_simple.c | 7 +- configs/bayleybay_defconfig | 2 + configs/chromebook_samus_defconfig | 51 + configs/cougarcanyon2_defconfig | 2 + configs/crownbay_defconfig | 2 + configs/galileo_defconfig | 2 + configs/minnowmax_defconfig | 6 +- doc/README.x86 | 106 +- .../gpio/intel,x86-broadwell-pinctrl.txt | 208 +++ .../gpio/intel,x86-pinctrl.txt | 22 +- drivers/core/syscon-uclass.c | 1 + drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uclass.c | 26 +- drivers/gpio/intel_broadwell_gpio.c | 198 +++ drivers/gpio/intel_ich6_gpio.c | 191 +-- drivers/input/i8042.c | 6 + drivers/pci/pci-uclass.c | 58 +- drivers/serial/serial-uclass.c | 1 + drivers/video/Kconfig | 14 +- drivers/video/Makefile | 2 + drivers/video/broadwell_igd.c | 797 ++++++++++++ drivers/video/i915_reg.h | 362 ++++++ drivers/video/simple_panel.c | 18 +- include/asm-generic/gpio.h | 20 +- include/configs/chromebook_samus.h | 29 + include/configs/x86-chromebook.h | 8 +- include/cpu.h | 5 + include/dt-bindings/gpio/x86-gpio.h | 12 + include/fdtdec.h | 2 - include/pci.h | 29 +- lib/dhry/cmd_dhry.c | 8 +- lib/fdtdec.c | 2 - scripts/coreboot.sed | 17 + 133 files changed, 11158 insertions(+), 1719 deletions(-) create mode 100644 arch/arm/lib/_uldivmod.S create mode 100644 arch/x86/cpu/broadwell/Kconfig create mode 100644 arch/x86/cpu/broadwell/Makefile create mode 100644 arch/x86/cpu/broadwell/cpu.c create mode 100644 arch/x86/cpu/broadwell/iobp.c create mode 100644 arch/x86/cpu/broadwell/lpc.c create mode 100644 arch/x86/cpu/broadwell/me.c create mode 100644 arch/x86/cpu/broadwell/northbridge.c create mode 100644 arch/x86/cpu/broadwell/pch.c create mode 100644 arch/x86/cpu/broadwell/pinctrl_broadwell.c create mode 100644 arch/x86/cpu/broadwell/power_state.c create mode 100644 arch/x86/cpu/broadwell/refcode.c create mode 100644 arch/x86/cpu/broadwell/sata.c create mode 100644 arch/x86/cpu/broadwell/sdram.c create mode 100644 arch/x86/cpu/intel_common/Makefile rename arch/x86/cpu/{ivybridge => intel_common}/car.S (98%) create mode 100644 arch/x86/cpu/intel_common/cpu_common.c create mode 100644 arch/x86/cpu/intel_common/lpc_common.c rename arch/x86/cpu/{ivybridge => intel_common}/me_status.c (93%) rename arch/x86/cpu/{ivybridge => intel_common}/microcode_intel.c (98%) create mode 100644 arch/x86/cpu/intel_common/pch_common.c rename arch/x86/cpu/{ivybridge => intel_common}/report_platform.c (98%) create mode 100644 arch/x86/cpu/intel_common/sdram_common.c create mode 100644 arch/x86/dts/chromebook_samus.dts create mode 100644 arch/x86/dts/microcode/m7240651_0000001c.dtsi create mode 100644 arch/x86/dts/microcode/mc0306d4_00000018.dtsi create mode 100644 arch/x86/include/asm/arch-broadwell/cpu.h create mode 100644 arch/x86/include/asm/arch-broadwell/gpio.h create mode 100644 arch/x86/include/asm/arch-broadwell/iomap.h create mode 100644 arch/x86/include/asm/arch-broadwell/lpc.h create mode 100644 arch/x86/include/asm/arch-broadwell/me.h create mode 100644 arch/x86/include/asm/arch-broadwell/pch.h create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h create mode 100644 arch/x86/include/asm/arch-broadwell/pm.h create mode 100644 arch/x86/include/asm/arch-broadwell/rcb.h create mode 100644 arch/x86/include/asm/arch-broadwell/spi.h create mode 100644 arch/x86/include/asm/cpu_common.h create mode 100644 arch/x86/include/asm/intel_regs.h create mode 100644 arch/x86/include/asm/lpc_common.h create mode 100644 arch/x86/include/asm/me_common.h rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (63%) create mode 100644 arch/x86/include/asm/pch_common.h create mode 100644 arch/x86/include/asm/report_platform.h create mode 100644 arch/x86/include/asm/sdram_common.h create mode 100644 arch/x86/lib/pinctrl_ich6.c create mode 100644 board/google/chromebook_samus/Kconfig create mode 100644 board/google/chromebook_samus/MAINTAINERS create mode 100644 board/google/chromebook_samus/Makefile create mode 100644 board/google/chromebook_samus/samus.c create mode 100644 configs/chromebook_samus_defconfig create mode 100644 doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt create mode 100644 drivers/gpio/intel_broadwell_gpio.c create mode 100644 drivers/video/broadwell_igd.c create mode 100644 drivers/video/i915_reg.h create mode 100644 include/configs/chromebook_samus.h create mode 100644 scripts/coreboot.sed -- 2.7.0.rc3.207.g0ac5344

4 172

[U-Boot] [PATCH] ls102xa: dm: serial: Disable CONFIG_DM_STDIO for LCD/HDMI display
by Alison Wang 14 Mar '16

14 Mar '16

When LCD/HDMI is connected to LS1021ATWR or LS1021AQDS, the console output should be shown on the monitor. If CONFIG_DM_SERIAL and CONFIG_DM_STDIO are both enabled, serial device is registered and added to the stdio list in serial-uclass.c. Then, vga device will be registered and added to the stdio list in cfb_console.c. So serial device is at the head of the stdio list and will be chosen as the input and output device in console_init_r(). It will cause the console output can't be shown on the monitor. If CONFIG_DM_STDIO is disabled when using CONFIG_DM_SERIAL. First, vga device is registered and added to the stdio list in cfb_console.c. Then serial device will be registered and added to the stdio list in drv_system_init(). So vga device is at the head of the stdio list and will be chosen as the input and output device in console_init_r(). The console output will be shown on the monitor. The patch is to disabled CONFIG_DM_STDIO for LCD/HDMI display. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- include/configs/ls1021aqds.h | 4 ++++ include/configs/ls1021atwr.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ff5ca22..fbb1f46 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -384,6 +384,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BAUDRATE 115200 +#ifdef CONFIG_DM_SERIAL +#undef CONFIG_DM_STDIO +#endif + /* * I2C */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 166061d..9054774 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -280,6 +280,10 @@ #define CONFIG_BAUDRATE 115200 +#ifdef CONFIG_DM_SERIAL +#undef CONFIG_DM_STDIO +#endif + /* * I2C */ -- 2.1.0.27.g96db324

3 2

[U-Boot] [PATCH v2 00/18] Add support for 96boards Dragonboard410C board
by Mateusz Kulikowski 13 Mar '16

13 Mar '16

Hi All, This is (hopefully) last version of Dragonboard410c series. As always - for "simplicity" this series is available on my github: https://github.com/hallor/u-boot/tree/dragonboard-for-mainline-v3 There are almost no changes (none that should break anything): - Updated dragonboard readme.txt with info on how to stop @ fastboot - Added SPMI entries into test.dts (so automatic DM tests would not fail) - Added Tested-by and Reviewed-by Simon (from v2 comments) - Rebased to recent master @Simon: Thanks for the tests! Regards, Mateusz V2 cover contents: This is updated series. 99% of review changes are applied, specific changes are (as always) include in each patch. You can find this series on my github (if anyone just want to try it - that branch has also wait_for_bit applied): https://github.com/hallor/u-boot/tree/dragonboard-for-mainline-v2 I did target tests on Dragonboard410c, and build tested platforms that may be affected by ULPI changes. @Simon: I decided not to rewrite pm8916_gpio for now, but for sake of "cleannes" moved offending bindings to separate file (and they are now properly childs of pm8916_gpio). I will update it during rework of SoC gpio driver (I will have to create proper pinmux/pinctrl drivers to get rid of Little Kernel eventually). This series still needs wait_for_bit series that is not included (yet). V1 cover contents: I finally managed to cleanup RFC for submission. I've included changes in each patch, there is a bit of them, but all are needed :) This series requires wait_for_bit patch that I send few days ago: https://patchwork.ozlabs.org/patch/561185/ RFC cover contents: http://lists.denx.de/pipermail/u-boot/2015-December/237365.html Changes in v3: - Updated test.dts to include SPMI like sandbox.dts does - readme: Added info on how to enter fastboot mode and that dtbTool is also part of skales Changes in v2: - Added newline before return... (globally) - Renamed p to priv (priv data) - it required some rewrapping - Added Reviewed-by - Reordered includes (again) - Added newlines between returns - Fixed error handling in msm_gpio_probe - Added reviewed-by - Add reviewed-by - Add Reviewed-by (sjg) - Add better (any) descriptions for Kconfig items. - New patch, independent of the rest - Should compile cleanly on all affected platforms - Is orthogonal to series (i.e. if get's NAK will not break rest of series) - Add acked-by - Add reviewed-by - Add Acked-by - Use PORT_... macro to write to portsc - Remove extra whitespace in probe() - Add acked-by - Use proper entry order in Kconfig - Rename CONFIG_DM_SPMI -> CONFIG_SPMI - Fix header ordering - Add reviewed-by - Rename CONFIG_DM_SPMI -> CONFIG_SPMI - Rename r -> regs, p -> priv - Add reviewed-by - Update binding doc (drop unused bindig) - Rename DM_SPMI -> SPMI - Rename p -> priv (in write/read) - Fix header ordering (again) - Add reviewed-by - Add reviewed-by - Reordered Kconfig & Makefile (to keep alphabetical ordering) - Added link to dt binding @ help - Add Reviewed-by - Rename DM_SPMI -> SPMI - Make MND divider comments more compact :) - p -> priv - Add reviewed-by - Reordered Kconfig to keep alphabetical order - Renamed reset_sandbox -> msm_reset (typo in reset.c) - Renamed CONFIG_DM_SPMI -> CONFIG_SPMI - Removed extra enter in dragonboard file - Added ULPI* to defconfig - Added MAINTAINERS to board - Cleaned up config file - use distro defaults/environment: - Dropped multiple CONFIG_CMD* and other CONFIG_* - Added distro env/config - Dropped old boot commands - Split dts - pm8916_gpio entries are taken directly from Linux Dragonboard dts; Add handles for u-boot in -uboot.dtsi; They will be removed once gpio drivers are converted to pinctrl. - Renamed some pmic nodes, fixed dragonboard.c to find them properly. - Added header and converted comments to c98-style in head.S - Print error if pmic gpio node is not found. - New patch Changes in v1: - Added (better) help to KConfig - Added dt binding documentation - Fixed include ordering - Reworked msm_serial_getc - Added error handling to msm_uart_clk_init (that is ignored later for now) - Dropped unneeded DM_FLAG_PRE_RELOC - Added dt binding documentation - Added help to KConfig - Use clrsetbits() to switch direction - Fixed include order - Added #defines for registers/register fields - Added secondary compatible string - Added commit message - Added DT binding documentation - Added Kconfig help - Reordered includes - Dropped redundant fields from msm_sdhc - Cleaned up clock init code (+ added error handling) - Dropped mdelay - use wait_for_bit instead in reset code - Added missing newline after declarations - Added error handling if "reg" is missing - Converted base address to pointer - No changes, just added Acked-by, Reviewed-by - Reordered header files - Removed braces around constant - Added more verbose help to KConfig - Added ULPI dependency to Kconfig - Drop register #defines - use ehci-ci.h instead - Create fixed ulpi viewport for device - Use setbits/clearbits where possible - Use wait_for_bit to reset controller - Add dt binding documents - Reorder includes - Add read/write arguments documentation - add binding documentation and better Kconfig help - Changed a bit mapping - Change include order - Use clrsetbits* where possible - Add one more supported dts id - Handle missing fields in dt properly - Added dt bindings - Reoder includes - Replaced extract_* macros with ordinary shift/mask - Added error checking and whitespaces in probe - Add binding doc - Fixed inlcude ordering - Merged direction_input and direction_output functions - gpio_get: use switch instead of stacked if - use pmic_clrsetbits - add possibility to change prwkey bank name - Handle invalid bindings - Sanity HW check (i.e. check type/subtype registers) - Fix include order - Cleanup defines (added spaces for readibility) - Base address is integer to avoid casting - Use setbits_* family where possible - Drop unneded comments, added newlines where needed - Check return value of dev_get_addr - Add binding for apq8016 - Cleaned up divider calculation - Drop most of gpio.h (only empty file is needed) - Add better help for dragonboard - Move static structures to board_prepare_usb - Add DM_SPMI to defconfig Mateusz Kulikowski (18): serial: Add support for Qualcomm serial port gpio: Add support for Qualcomm gpio controller mmc: Add support for Qualcomm SDHCI controller ehci-hcd: Add init_after_reset usb: ulpi: Add Kconfig options for ULPI Migrate CONFIG_ULPI* to Kconfig usb: Rename ehci-fsl.h to ehci-ci.h usb: ehci-ci: Add missing registers. ehci-ci.h: drop generic USBCMD fields ehci: Add support for Qualcomm EHCI drivers: Add SPMI bus uclass spmi: Add sandbox test driver drivers: spmi: Add support for Qualcomm SPMI bus driver pmic: Add support for Qualcomm PM8916 PMIC gpio: Add support for Qualcomm PM8916 gpios arm: Add support for Qualcomm Snapdragon family board: Add Qualcomm Dragonboard 410C support Add myself as Snapdragon and SPMI maintainer MAINTAINERS | 11 + arch/arm/Kconfig | 12 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/dragonboard410c-uboot.dtsi | 28 ++ arch/arm/dts/dragonboard410c.dts | 148 ++++++++++ arch/arm/mach-snapdragon/Kconfig | 26 ++ arch/arm/mach-snapdragon/Makefile | 8 + arch/arm/mach-snapdragon/clock-apq8016.c | 262 ++++++++++++++++++ arch/arm/mach-snapdragon/include/mach/gpio.h | 9 + .../mach-snapdragon/include/mach/sysmap-apq8016.h | 14 + arch/arm/mach-snapdragon/reset.c | 40 +++ arch/sandbox/dts/sandbox.dts | 20 ++ arch/sandbox/dts/test.dts | 20 ++ board/qualcomm/dragonboard410c/Kconfig | 15 + board/qualcomm/dragonboard410c/MAINTAINERS | 6 + board/qualcomm/dragonboard410c/Makefile | 8 + board/qualcomm/dragonboard410c/dragonboard410c.c | 131 +++++++++ board/qualcomm/dragonboard410c/head.S | 28 ++ board/qualcomm/dragonboard410c/readme.txt | 43 +++ board/qualcomm/dragonboard410c/u-boot.lds | 90 ++++++ configs/colibri_t20_defconfig | 2 + configs/dragonboard410c_defconfig | 31 +++ configs/harmony_defconfig | 2 + configs/mcx_defconfig | 3 + configs/mt_ventoux_defconfig | 3 + configs/sandbox_defconfig | 4 + configs/twister_defconfig | 3 + configs/zynq_picozed_defconfig | 3 + configs/zynq_zc702_defconfig | 3 + configs/zynq_zc706_defconfig | 3 + configs/zynq_zed_defconfig | 3 + configs/zynq_zybo_defconfig | 3 + doc/device-tree-bindings/gpio/gpio-msm.txt | 22 ++ doc/device-tree-bindings/gpio/pm8916_gpio.txt | 48 ++++ doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 ++ doc/device-tree-bindings/pmic/pm8916.txt | 18 ++ doc/device-tree-bindings/serial/msm-serial.txt | 6 + doc/device-tree-bindings/spmi/spmi-msm.txt | 26 ++ doc/device-tree-bindings/spmi/spmi-sandbox.txt | 31 +++ doc/device-tree-bindings/usb/ehci-msm.txt | 10 + doc/git-mailrc | 3 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/gpio/Kconfig | 24 ++ drivers/gpio/Makefile | 2 + drivers/gpio/msm_gpio.c | 135 +++++++++ drivers/gpio/pm8916_gpio.c | 302 +++++++++++++++++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/msm_sdhci.c | 180 ++++++++++++ drivers/power/pmic/Kconfig | 16 ++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pm8916.c | 96 +++++++ drivers/serial/Kconfig | 8 + drivers/serial/Makefile | 1 + drivers/serial/serial_msm.c | 212 +++++++++++++++ drivers/spmi/Kconfig | 23 ++ drivers/spmi/Makefile | 9 + drivers/spmi/spmi-msm.c | 189 +++++++++++++ drivers/spmi/spmi-sandbox.c | 157 +++++++++++ drivers/spmi/spmi-uclass.c | 48 ++++ drivers/usb/Kconfig | 2 + drivers/usb/host/Kconfig | 11 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-fsl.c | 2 +- drivers/usb/host/ehci-hcd.c | 6 + drivers/usb/host/ehci-mpc512x.c | 6 +- drivers/usb/host/ehci-msm.c | 178 ++++++++++++ drivers/usb/host/ehci-mx5.c | 2 +- drivers/usb/host/ehci-mx6.c | 2 +- drivers/usb/host/ehci-mxc.c | 2 +- drivers/usb/host/ehci-vf.c | 2 +- drivers/usb/host/ehci-zynq.c | 2 +- drivers/usb/host/ehci.h | 1 + drivers/usb/ulpi/Kconfig | 33 +++ include/configs/colibri_t20.h | 2 - include/configs/dragonboard410c.h | 153 +++++++++++ include/configs/harmony.h | 2 - include/configs/mcx.h | 2 - include/configs/tam3517-common.h | 2 - include/configs/zynq-common.h | 2 - include/dm/uclass-id.h | 1 + include/spmi/spmi.h | 47 ++++ include/usb/{ehci-fsl.h => ehci-ci.h} | 16 +- test/dm/Makefile | 1 + test/dm/spmi.c | 115 ++++++++ 87 files changed, 3156 insertions(+), 27 deletions(-) create mode 100644 arch/arm/dts/dragonboard410c-uboot.dtsi create mode 100644 arch/arm/dts/dragonboard410c.dts create mode 100644 arch/arm/mach-snapdragon/Kconfig create mode 100644 arch/arm/mach-snapdragon/Makefile create mode 100644 arch/arm/mach-snapdragon/clock-apq8016.c create mode 100644 arch/arm/mach-snapdragon/include/mach/gpio.h create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h create mode 100644 arch/arm/mach-snapdragon/reset.c create mode 100644 board/qualcomm/dragonboard410c/Kconfig create mode 100644 board/qualcomm/dragonboard410c/MAINTAINERS create mode 100644 board/qualcomm/dragonboard410c/Makefile create mode 100644 board/qualcomm/dragonboard410c/dragonboard410c.c create mode 100644 board/qualcomm/dragonboard410c/head.S create mode 100644 board/qualcomm/dragonboard410c/readme.txt create mode 100644 board/qualcomm/dragonboard410c/u-boot.lds create mode 100644 configs/dragonboard410c_defconfig create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt create mode 100644 doc/device-tree-bindings/gpio/pm8916_gpio.txt create mode 100644 doc/device-tree-bindings/mmc/msm_sdhci.txt create mode 100644 doc/device-tree-bindings/pmic/pm8916.txt create mode 100644 doc/device-tree-bindings/serial/msm-serial.txt create mode 100644 doc/device-tree-bindings/spmi/spmi-msm.txt create mode 100644 doc/device-tree-bindings/spmi/spmi-sandbox.txt create mode 100644 doc/device-tree-bindings/usb/ehci-msm.txt create mode 100644 drivers/gpio/msm_gpio.c create mode 100644 drivers/gpio/pm8916_gpio.c create mode 100644 drivers/mmc/msm_sdhci.c create mode 100644 drivers/power/pmic/pm8916.c create mode 100644 drivers/serial/serial_msm.c create mode 100644 drivers/spmi/Kconfig create mode 100644 drivers/spmi/Makefile create mode 100644 drivers/spmi/spmi-msm.c create mode 100644 drivers/spmi/spmi-sandbox.c create mode 100644 drivers/spmi/spmi-uclass.c create mode 100644 drivers/usb/host/ehci-msm.c create mode 100644 drivers/usb/ulpi/Kconfig create mode 100644 include/configs/dragonboard410c.h create mode 100644 include/spmi/spmi.h rename include/usb/{ehci-fsl.h => ehci-ci.h} (96%) create mode 100644 test/dm/spmi.c -- 2.5.0

6 37

[U-Boot] [PATCH] usb: Add new command to regress USB devices
by Rajat Srivastava 13 Mar '16

13 Mar '16

This patch adds a new 'usb regress' command, that can be used to regress test a USB device. It performs the following operations: 1. starts the USB device 2. performs read/write operations 3. stops the USB device 4. verifies the contents of read/write operations Sample Output: => usb regress 81000000 82000000 32m regressing USB.. starting USB... USB0: Register 200017f NbrPorts 2 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found USB write: device 0 block # 0, count 65536 ... 65536 blocks write: OK USB read: device 0 block # 0, count 65536 ... 65536 blocks read: OK stopping USB.. verifying data on addresses 0x81000000 and 0x82000000 Total of 65536 word(s) were the same Signed-off-by: Rajat Srivastava <rajat.srivastava(a)nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat(a)nxp.com> --- common/cmd_usb.c | 174 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 173 insertions(+), 1 deletion(-) diff --git a/common/cmd_usb.c b/common/cmd_usb.c index a540b42..25fdeab 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -20,6 +20,7 @@ #include <asm/unaligned.h> #include <part.h> #include <usb.h> +#include <mapmem.h> #ifdef CONFIG_USB_STORAGE static int usb_stor_curr_dev = -1; /* current device */ @@ -616,6 +617,167 @@ static int usb_device_info(void) } #endif +static unsigned long calc_blockcount(char * const size) +{ + unsigned long value, multiplier; + int size_len = strlen(size); + char unit; + + /* extract the unit of size passed */ + unit = size[size_len - 1]; + /* updating the source string to remove unit */ + size[size_len - 1] = '\0'; + + value = simple_strtoul(size, NULL, 10); + if (value <= 0) { + printf("invalid size\n"); + return 0; + } + + if (unit == 'G' || unit == 'g') { + multiplier = 2 * 1024 * 1024; + } else if (unit == 'M' || unit == 'm') { + multiplier = 2 * 1024; + } else if (unit == 'K' || unit == 'k') { + multiplier = 2; + } else if (unit == 'B' || unit == 'b') { + if (value % 512 != 0) { + printf("size can only be multiples of 512 bytes\n"); + return 0; + } + multiplier = 1; + value /= 512; + } else { + printf("syntax mismatch\n"); + return 0; + } + + return value * multiplier; +} + +static int usb_read_write_verify(unsigned long w_addr, unsigned long r_addr, + unsigned long cnt) +{ + cmd_tbl_t *c; + char str[3][16]; + char *ptr[4] = { "cmp", str[0], str[1], str[2] }; + + c = find_cmd("cmp"); + if (!c) { + printf("compare command not found\n"); + return -1; + } + printf("verifying data on addresses 0x%lx and 0x%lx\n", w_addr, r_addr); + sprintf(str[0], "%lx", w_addr); + sprintf(str[1], "%lx", r_addr); + sprintf(str[2], "%lx", cnt); + (c->cmd)(c, 0, 4, ptr); + return 0; +} + + +static int do_usb_regress(int argc, char * const argv[]) +{ + unsigned long loopcount, iteration; + unsigned long w_addr, r_addr, cnt, n; + unsigned long blk = 0; + extern char usb_started; + +#ifdef CONFIG_USB_STORAGE + block_dev_desc_t *stor_dev; +#endif + + if (argc < 5 || argc > 6) { + printf("syntax mismatch\n"); + return -1; + } + + if (argc == 5) + loopcount = 1; + else + loopcount = simple_strtoul(argv[5], NULL, 10); + + if (loopcount <= 0) { + printf("syntax mismatch\n"); + return -1; + } + + cnt = calc_blockcount(argv[4]); + if (cnt == 0) + return -1; + + iteration = loopcount; + while (loopcount--) { + if (argc > 5) + printf("\niteration #%lu\n\n", iteration - loopcount); + + /* start USB */ + if (usb_started) { + printf("USB already started\n"); + } else { + printf("starting USB...\n"); + do_usb_start(); + } + if (!usb_started) { + printf("USB did not start\n"); + return -1; + } + if (usb_stor_curr_dev < 0) { + printf("no current device selected\nstopping USB...\n"); + usb_stop(); + return -1; + } + +#ifdef CONFIG_USB_STORAGE + /* write on USB from address (w_addr) of RAM */ + w_addr = simple_strtoul(argv[2], NULL, 16); + printf("USB write: device %d block # %ld, count %ld ... ", + usb_stor_curr_dev, blk, cnt); + stor_dev = usb_stor_get_dev(usb_stor_curr_dev); + n = stor_dev->block_write(usb_stor_curr_dev, blk, cnt, + (ulong *)w_addr); + printf("%ld blocks write: %s\n", n, (n == cnt) ? + "OK" : "ERROR"); + if (n != cnt) { + printf("aborting.. USB write failed\n"); + usb_stop(); + return -1; + } + + /* read from USB and write on to address (r_addr) on RAM */ + r_addr = simple_strtoul(argv[3], NULL, 16); + printf("USB read: device %d block # %ld, count %ld ... ", + usb_stor_curr_dev, blk, cnt); + stor_dev = usb_stor_get_dev(usb_stor_curr_dev); + n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt, + (ulong *)r_addr); + printf("%ld blocks read: %s\n", n, (n == cnt) ? "OK" : "ERROR"); + if (n != cnt) { + printf("aborting.. USB read failed\n"); + usb_stop(); + return -1; + } +#endif + + /* stop USB */ + printf("stopping USB..\n"); + usb_stop(); + +#ifdef CONFIG_USB_STORAGE + /* + * verify the content written on USB and + * content read from USB. + */ + if (usb_read_write_verify(w_addr, r_addr, cnt) == -1) + return -1; +#endif + if (ctrlc()) + return -1; + } + + return 0; +} + /****************************************************************************** * usb command intepreter */ @@ -656,6 +818,13 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) usb_stop(); return 0; } + if (strncmp(argv[1], "regress", 6) == 0) { + if (do_usb_stop_keyboard(0) != 0) + return 1; + printf("regressing USB..\n"); + do_usb_regress(argc, argv); + return 0; + } if (!usb_started) { printf("USB is stopped. Please issue 'usb start' first.\n"); return 1; @@ -821,7 +990,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - usb, 5, 1, do_usb, + usb, 6, 1, do_usb, "USB sub-system", "start - start (scan) USB controller\n" "usb reset - reset (rescan) USB controller\n" @@ -831,6 +1000,9 @@ U_BOOT_CMD( "usb test [dev] [port] [mode] - set USB 2.0 test mode\n" " (specify port 0 to indicate the device's upstream port)\n" " Available modes: J, K, S[E0_NAK], P[acket], F[orce_Enable]\n" + "usb regress waddr raddr size [iterations] - regress a USB device\n" + " (starts, writes to waddr, reads from raddr, stops and verifies.\n" + " `size' format 1B/1K/1M/1G)\n " #ifdef CONFIG_USB_STORAGE "usb storage - show details of USB storage devices\n" "usb dev [dev] - show or set current USB storage device\n" -- 1.9.1

6 10

[U-Boot] [PATCH v2 1/3] Add a binding file for rockchip video
by Jacob Chen 13 Mar '16

13 Mar '16

and include it in rk3288 device tree Signed-off-by: Jacob Chen <jacob-chen(a)iotwrt.com> --- arch/arm/dts/rk3288.dtsi | 1 + include/dt-bindings/video/rk3288.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/dt-bindings/video/rk3288.h diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index ba29b38..3dab0fc 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/power-domain/rk3288.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/video/rk3288.h> #include "skeleton.dtsi" / { diff --git a/include/dt-bindings/video/rk3288.h b/include/dt-bindings/video/rk3288.h new file mode 100644 index 0000000..7bfd247 --- /dev/null +++ b/include/dt-bindings/video/rk3288.h @@ -0,0 +1,11 @@ +#ifndef __DT_BINDINGS_VIDEO_RK3288_H__ +#define __DT_BINDINGS_VIDEO_RK3288_H__ + +#define LVDS_OUTPUT_RGB 0 +#define LVDS_OUTPUT_SINGLE 1 +#define LVDS_OUTPUT_DUAL 2 + +#define LVDS_FORMAT_VESA 0 +#define LVDS_FORMAT_JEIDA 1 + +#endif -- 2.3.5

2 1

[U-Boot] [PATCH v2 0/3] Add LVDS support for rk3288
by Jacob Chen 13 Mar '16

13 Mar '16

This series patches add LVDS support for rk3288. Jacob Chen (3): Add a bingding file for rockchip video rockchip: video: Add a display driver for rockchip LVDS doc: dt-bindings: Describe rockchip LVDS interface arch/arm/dts/rk3288.dtsi | 1 + arch/arm/include/asm/arch-rockchip/lvds_rk3288.h | 97 +++++++++ doc/device-tree-bindings/video/rockchip-lvds.txt | 77 +++++++ drivers/video/rockchip/Makefile | 2 +- drivers/video/rockchip/rk_lvds.c | 254 +++++++++++++++++++++++ include/dt-bindings/video/rk3288.h | 11 + 6 files changed, 441 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-rockchip/lvds_rk3288.h create mode 100644 doc/device-tree-bindings/video/rockchip-lvds.txt create mode 100644 drivers/video/rockchip/rk_lvds.c create mode 100644 include/dt-bindings/video/rk3288.h -- 2.3.5

2 4