March 2016 - U-Boot

[U-Boot] [PATCH 1/4] arm: iproc: add NAND driver
by Steve Rae 11 Mar '16

11 Mar '16

From: Jiandong Zheng <jdzheng(a)broadcom.com> Add support for the iproc NAND, and enable on Cygnus and NSP boards. Signed-off-by: Jiandong Zheng <jdzheng(a)broadcom.com> Signed-off-by: Steve Rae <srae(a)broadcom.com> --- There was a previous attempt to implement this "iproc NAND" (see: http://patchwork.ozlabs.org/patch/505399), however, due to the amount of changes required, it seemed better to implement the code in a series of steps. This is the first step, where the "iproc_nand.c" is essentially an empty file (with one function required to allow this commit to build successfully). arch/arm/include/asm/arch-bcmcygnus/configs.h | 11 +++ arch/arm/include/asm/arch-bcmnsp/configs.h | 11 +++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/iproc_nand.c | 11 +++ drivers/mtd/nand/iproc_nand_cygnus.h | 111 +++++++++++++++++++++++++ drivers/mtd/nand/iproc_nand_ns_plus.h | 113 ++++++++++++++++++++++++++ 6 files changed, 258 insertions(+) create mode 100644 drivers/mtd/nand/iproc_nand.c create mode 100644 drivers/mtd/nand/iproc_nand_cygnus.h create mode 100644 drivers/mtd/nand/iproc_nand_ns_plus.h diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 3c07160..3bf7395 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -10,6 +10,7 @@ #include <asm/iproc-common/configs.h> /* uArchitecture specifics */ +#include <../../../drivers/mtd/nand/iproc_nand_cygnus.h> /* Serial Info */ /* Post pad 3 bytes after each reg addr */ @@ -33,4 +34,14 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_MII +/* NAND configuration */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_IPROC +#define CONFIG_SYS_NAND_IPROC_TIMING_MODE 5 +#define CONFIG_SYS_NAND_BASE 0 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 786deae..aeaea6a 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -10,6 +10,7 @@ #include <asm/iproc-common/configs.h> /* uArchitecture specifics */ +#include <../../../drivers/mtd/nand/iproc_nand_ns_plus.h> /* Serial Info */ /* no padding */ @@ -19,4 +20,14 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 0x18000300 +/* NAND configuration */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_IPROC +#define CONFIG_SYS_NAND_IPROC_TIMING_MODE 5 +#define CONFIG_SYS_NAND_BASE 0 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_NAND_ONFI_DETECTION + #endif /* __ARCH_CONFIGS_H */ diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 6fb3718..bb3adbc 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o +obj-$(CONFIG_NAND_IPROC) += iproc_nand.o obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o diff --git a/drivers/mtd/nand/iproc_nand.c b/drivers/mtd/nand/iproc_nand.c new file mode 100644 index 0000000..74f885a --- /dev/null +++ b/drivers/mtd/nand/iproc_nand.c @@ -0,0 +1,11 @@ +/* + * Copyright 2015 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +void board_nand_init(void) +{ +} diff --git a/drivers/mtd/nand/iproc_nand_cygnus.h b/drivers/mtd/nand/iproc_nand_cygnus.h new file mode 100644 index 0000000..26a00a9 --- /dev/null +++ b/drivers/mtd/nand/iproc_nand_cygnus.h @@ -0,0 +1,111 @@ +/* + * Copyright 2015 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IPROC_NAND_CYGNUS_H_ +#define _IPROC_NAND_CYGNUS_H_ + +/* + * SoC specific definitions (Cygnus) + */ + +#define REG_NAND_BASE 0x18046000 +#define REG_NAND_IDM_BASE 0xf8105000 + +#define NAND_STRAP_TYPE_MASK 0x000f0000 +#define NAND_STRAP_TYPE_SHIFT 16 +#define NAND_STRAP_PAGE_MASK 0x00300000 +#define NAND_STRAP_PAGE_SHIFT 20 +#define NAND_STRAP_WIDTH_MASK 0x01000000 +#define NAND_STRAP_WIDTH_SHIFT 24 + +#define NAND_STRAP_TYPE_DATA \ +/* sector_1k, ecclevel, spare_size */ \ +{ \ + { 0, 0, 16 }, \ + { 0, 1, 16 }, \ + { 0, 4, 16 }, \ + { 0, 8, 16 }, \ + { 0, 8, 27 }, \ + { 0, 12, 27 }, \ + { 1, 12, 27 }, \ + { 1, 15, 27 }, \ + { 1, 20, 45 } \ +} + +#define NAND_STRAP_PAGE_DATA \ +{ \ + 1024, 2048, 4096, 8192 \ +} + +/* + * iProc NAND timing configurations for ONFI timing modes [0-5] + * + * Clock tick = 10ns + * Multiplier: + * x1: tWP tWH tRP tREH tCLH tALH + * x2: tCS tADL tWB tWHR + */ +#define NAND_TIMING_DATA \ +{ \ + /* ONFI timing mode 0 : */ \ + /* tWC=100ns tWP=50ns tWH=30ns */ \ + /* tRC=100ns tRP=50ns tREH=30ns */ \ + /* tCS=70ns tCLH=20ns tALH=20ns tADL=200ns */ \ + /* tWB=200ns tWHR=120ns tREA=40ns */ \ + { \ + .timing1 = 0x6565435b, \ + .timing2 = 0x00001e85, \ + }, \ + /* ONFI timing mode 1 : */ \ + /* tWC=45 tWP=25ns tWH=15ns */ \ + /* tRC=50 tRP=25ns tREH=15ns */ \ + /* tCS=35ns tCLH=10ns tALH=10ns tADL=100ns */ \ + /* tWB=100ns tWHR=80ns tREA=30ns */ \ + { \ + .timing1 = 0x33333236, \ + .timing2 = 0x00001064, \ + }, \ + /* ONFI timing mode 2 : */ \ + /* tWC=35ns tWP=17ns tWH=15ns */ \ + /* tRC=35ns tRP=17ns tREH=15ns */ \ + /* tCS=25ns tCLH=10ns tALH=10ns tADL=100ns */ \ + /* tWB=100ns tWHR=80ns tREA=25ns */ \ + { \ + .timing1 = 0x32322226, \ + .timing2 = 0x00001063, \ + }, \ + /* ONFI timing mode 3 : */ \ + /* tWC=30ns tWP=15ns tWH=10ns */ \ + /* tRC=30ns tRP=15ns tREH=10ns */ \ + /* tCS=25ns tCLH=5ns tALH=5ns tADL=100ns */ \ + /* tWB=100ns tWHR=60ns tREA=20ns */ \ + { \ + .timing1 = 0x22222126, \ + .timing2 = 0x00001043, \ + }, \ + /* ONFI timing mode 4 : */ \ + /* tWC=25ns tWP=12ns tWH=10ns */ \ + /* tRC=25ns tRP=12ns tREH=10ns */ \ + /* tCS=20ns tCLH=5ns tALH=5ns tADL=70ns */ \ + /* tWB=100ns tWHR=60ns tREA=20ns */ \ + { \ + .timing1 = 0x21212114, \ + .timing2 = 0x00001042, \ + }, \ + /* ONFI timing mode 5 : */ \ + /* tWC=20ns tWP=10ns tWH=7ns */ \ + /* tRC=20ns tRP=10ns tREH=7ns */ \ + /* tCS=15ns tCLH=5ns tALH=5ns tADL=70ns */ \ + /* tWB=100ns tWHR=60ns tREA=16ns */ \ + { \ + .timing1 = 0x11111114, \ + .timing2 = 0x00001042, \ + }, \ +} + +#define NAND_MAX_CS 2 + +#endif /* _IPROC_NAND_CYGNUS_H_ */ diff --git a/drivers/mtd/nand/iproc_nand_ns_plus.h b/drivers/mtd/nand/iproc_nand_ns_plus.h new file mode 100644 index 0000000..41d5da7 --- /dev/null +++ b/drivers/mtd/nand/iproc_nand_ns_plus.h @@ -0,0 +1,113 @@ +/* + * Copyright 2015 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IPROC_NAND_NS_PLUS_H_ +#define _IPROC_NAND_NS_PLUS_H_ + +/* + * SoC specific definitions (NorthStar Plus) + */ + +#define REG_NAND_BASE 0x18026000 +#define REG_NAND_IDM_BASE 0x1811b000 +#define REG_NAND_STRAPS_BASE 0x1803f2a0 + +#define NAND_STRAP_TYPE_MASK 0x0000f000 +#define NAND_STRAP_TYPE_SHIFT 12 +#define NAND_STRAP_PAGE_MASK 0x00000c00 +#define NAND_STRAP_PAGE_SHIFT 10 +/* No bus width strap */ +#define NAND_STRAP_WIDTH_MASK 0x0 +#define NAND_STRAP_WIDTH_SHIFT 0 + +#define NAND_STRAP_TYPE_DATA \ +/* sector_1k, ecclevel, spare_size */ \ +{ \ + { 0, 0, 16 }, \ + { 0, 15, 16 }, /* Hamming ECC */ \ + { 0, 4, 16 }, \ + { 0, 8, 16 }, \ + { 0, 8, 27 }, \ + { 0, 12, 27 }, \ + { 1, 12, 27 }, \ + { 1, 15, 27 }, \ + { 1, 20, 45 } \ +} + +#define NAND_STRAP_PAGE_DATA \ +{ \ + 2048, 2048, 4096, 8192 \ +} + +/* + * iProc NAND timing configurations for ONFI timing modes [0-5] + * + * Clock tick = 4ns + * Multiplier: + * x1: tWP tWH tRP tREH tCLH tALH + * x4: tCS tADL tWB tWHR + */ +#define NAND_TIMING_DATA \ +{ \ + /* ONFI timing mode 0 : */ \ + /* tWC=100ns tWP=50ns tWH=30ns */ \ + /* tRC=100ns tRP=50ns tREH=30ns */ \ + /* tCS=70ns tCLH=20ns tALH=20ns tADL=200ns */ \ + /* tWB=200ns tWHR=120ns tREA=40ns */ \ + { \ + .timing1 = 0xfafa558d, \ + .timing2 = 0x00001a85, \ + }, \ + /* ONFI timing mode 1 : */ \ + /* tWC=45 tWP=25ns tWH=15ns */ \ + /* tRC=50 tRP=25ns tREH=15ns */ \ + /* tCS=35ns tCLH=10ns tALH=10ns tADL=100ns */ \ + /* tWB=100ns tWHR=80ns tREA=30ns */ \ + { \ + .timing1 = 0x85853347, \ + .timing2 = 0x00000e64, \ + }, \ + /* ONFI timing mode 2 : */ \ + /* tWC=35ns tWP=17ns tWH=15ns */ \ + /* tRC=35ns tRP=17ns tREH=15ns */ \ + /* tCS=25ns tCLH=10ns tALH=10ns tADL=100ns */ \ + /* tWB=100ns tWHR=80ns tREA=25ns */ \ + { \ + .timing1 = 0x54542347, \ + .timing2 = 0x00000e63, \ + }, \ + /* ONFI timing mode 3 : */ \ + /* tWC=30ns tWP=15ns tWH=10ns */ \ + /* tRC=30ns tRP=15ns tREH=10ns */ \ + /* tCS=25ns tCLH=5ns tALH=5ns tADL=100ns */ \ + /* tWB=100ns tWHR=60ns tREA=20ns */ \ + { \ + .timing1 = 0x44442237, \ + .timing2 = 0x00000e43, \ + }, \ + /* ONFI timing mode 4 : */ \ + /* tWC=25ns tWP=12ns tWH=10ns */ \ + /* tRC=25ns tRP=12ns tREH=10ns */ \ + /* tCS=20ns tCLH=5ns tALH=5ns tADL=70ns */ \ + /* tWB=100ns tWHR=60ns tREA=20ns */ \ + { \ + .timing1 = 0x43432235, \ + .timing2 = 0x00000e42, \ + }, \ + /* ONFI timing mode 5 : */ \ + /* tWC=20ns tWP=10ns tWH=7ns */ \ + /* tRC=20ns tRP=10ns tREH=7ns */ \ + /* tCS=15ns tCLH=5ns tALH=5ns tADL=70ns */ \ + /* tWB=100ns tWHR=60ns tREA=16ns */ \ + { \ + .timing1 = 0x32321225, \ + .timing2 = 0x00000e42, \ + }, \ +} + +#define NAND_MAX_CS 1 + +#endif /* _IPROC_NAND_NS_PLUS_H_ */ -- 1.8.5

4 8

[U-Boot] [PATCH v2 0/4] usb: Reduce USB scanning time
by Stefan Roese 11 Mar '16

11 Mar '16

My current x86 platform (Bay Trail, not in mainline yet) has a quite complex USB infrastructure with many USB hubs. Here the USB scan takes an incredible huge amount of time: starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 28.415 seconds This is of course not acceptable on platforms, where USB needs to get scanned at every bootup. As this increases the bootup time of this device by nearly 30 seconds! This patch series greatly reduces the USB scanning time. This is done by multiple means: - Remove or reduce delays and timeouts - Remove a 2nd reset of the USB hubs - Change USB port timeout handling and introduce quasi parallel USB port scanning As a result, the USB scanning time is greatly reduced: starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 4.606 seconds As you can see, the time is reduced from 28.4 to 4.6 seconds! Please find more details to the changes in the patch description. Testing and comments welcome! Thanks, Stefan Changes in v2: - Add Acked-by / Tested-by from Hans and Stephen - Make this change unconditional - Add Acked-by / Tested-by from Hans and Stephen - Make this change unconditional - Add Tested-by from Stephen - Remove static USB port configuration patch (for now) Stefan Roese (4): usb: legacy_hub_port_reset(): Speedup hub reset handling usb: Remove 200 ms delay in usb_hub_port_connect_change() usb: Don't reset the USB hub a 2nd time usb: Change power-on / scanning timeout handling common/usb.c | 13 +------ common/usb_hub.c | 110 +++++++++++++++++++++++++++++++++++++++---------------- include/usb.h | 2 + 3 files changed, 81 insertions(+), 44 deletions(-) -- 2.7.3

3 6

[U-Boot] please pull u-boot-samsung master
by Minkyu Kang 11 Mar '16

11 Mar '16

Dear Tom, The following changes since commit cf77f6ffd96a243d2e4f81fe8bc0aa4fe8fef623: Merge git://git.denx.de/u-boot-rockchip (2016-03-10 10:55:06 -0500) are available in the git repository at: git://git.denx.de/u-boot-samsung master for you to fetch changes up to 76aab9eb8b4618891914e41fa1ea84441f8c53fd: exynos5: common: Enable CONFIG_USB_ETHER_RTL8152 ethernet support (2016-03-11 10:59:51 +0900) ---------------------------------------------------------------- Anand Moon (1): exynos5: common: Enable CONFIG_USB_ETHER_RTL8152 ethernet support include/configs/exynos5-common.h | 1 + 1 file changed, 1 insertion(+) -- Thanks, Minkyu Kang.

2 1

[U-Boot] [PATCH] omap24xx_i2c: Implement CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
by Guy Thouret 11 Mar '16

11 Mar '16

Signed-off-by: Guy Thouret <guy.thouret(a)wems.co.uk> Cc: Heiko Schocher <hs(a)denx.de> --- drivers/i2c/omap24xx_i2c.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 79a5c94..a7f3fb4 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -371,6 +371,23 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, return 1; } +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); +#endif + /* Wait until bus not busy */ if (wait_for_bb(adap)) return 1; @@ -501,6 +518,23 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, return 1; } +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); +#endif + /* Wait until bus not busy */ if (wait_for_bb(adap)) return 1; -- 2.5.0

1 0

[U-Boot] [PATCH 0/6] usb: Reduce USB scanning time
by Stefan Roese 11 Mar '16

11 Mar '16

My current x86 platform (Bay Trail, not in mainline yet) has a quite complex USB infrastructure with many USB hubs. Here the USB scan takes an incredible huge amount of time: starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 28.415 seconds This is of course not acceptable on platforms, where USB needs to get scanned at every bootup. As this increases the bootup time of this device by nearly 30 seconds! This patch series greatly reduces the USB scanning time. This is done by multiple means: - Remove or reduce delays and timeouts - Remove a 2nd reset of the USB hubs - Introduce a static USB configuration method to skip specific USB ports while scanning Even without the new static configuration (which can disable specified ports), the resulting USB scanning time is greatly reduced: starting USB... USB0: USB EHCI 1.00 scanning bus 0 for devices... 9 USB Device(s) found time: 3.777 seconds As you can see, the time is reduced from 28.4 to 3.8 seconds! And with the static configuration, which can disable specific ports, the time can be reduced even further. Please find more details to the changes in the patch description. This patch introduces the new configuration option CONFIG_USB_FAST_SCAN to enable most of the speed enhancements. I'm actually not sure, if we should introduce this config option at all. Or better unconditionally apply all these changes to make this speedup default for all boards. As this could break some USB configurations, it needs thorough testing on many platforms before it becomes the default configuration. Testing and comments welcome! Thanks, Stefan Stefan Roese (6): usb: legacy_hub_port_reset(): Speedup hub reset handling usb: Remove 200 ms delay in usb_hub_port_connect_change() usb: Remove 1 second per port timeout in usb_hub_configure() usb: usb_hub_power_on(): Use 100ms power-on delay instead of 1 sec (optionally) usb: Don't reset the USB hub a 2nd time usb: Implement static USB port configuration to speed up USB scanning common/usb.c | 6 ++++++ common/usb_hub.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 69 insertions(+), 2 deletions(-) -- 2.7.2

3 24

[U-Boot] ums command using dwc3
by Poonam Aggrwal 11 Mar '16

11 Mar '16

Hello Marek Vasut I am working on u-boot 2016.01. Using a platform with DWC3 USB 3.0 controller. My objective is to configure the USB in device mode and it gets exposed to an X86 as a USB mass storage. The memory exposed would be a SATA disk. Is it possible to do it via ums command? I gave it some try on a Freescale platform; but basic enumeration also does not start. We get a Connect Done and a setup packet. Any pointers in this regard will help. Regards Poonam

1 0

[U-Boot] [PATCH] sunxi: Add defconfig and dts for Difrence DIT4350 tablet
by Hans de Goede 11 Mar '16

11 Mar '16

The Difrnce dit4350 tablet is a tiny tablet with a 4.3" 16:9 480x272 LCD, A13 SoC, 512M RAM, 4G NAND, solomon systech ssd2532qn6 touchscreen at i2c1 address 0x48, Memsic MXC622X accelerometer at i2c1 address 0x15 and rtl8188etv wifi. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun5i-a13-difrnce-dit4350.dts | 226 +++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 1 + configs/difrnce_dit4350_defconfig | 23 +++ 4 files changed, 251 insertions(+) create mode 100644 arch/arm/dts/sun5i-a13-difrnce-dit4350.dts create mode 100644 configs/difrnce_dit4350_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a8bc7b0..9566c81 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -135,6 +135,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-r7-tv-dongle.dtb \ sun5i-a10s-wobo-i5.dtb \ sun5i-a13-ampe-a76.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ sun5i-a13-empire-electronix-d709.dtb \ sun5i-a13-hsg-h702.dtb \ sun5i-a13-inet-86vs.dtb \ diff --git a/arch/arm/dts/sun5i-a13-difrnce-dit4350.dts b/arch/arm/dts/sun5i-a13-difrnce-dit4350.dts new file mode 100644 index 0000000..6546fa0 --- /dev/null +++ b/arch/arm/dts/sun5i-a13-difrnce-dit4350.dts @@ -0,0 +1,226 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede(a)redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Difrnce DIT4350"; + compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + /* TODO: backlight uses axp gpio1 as enable pin */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <&reg_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&lradc { + vref-supply = <&reg_ldo2>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>; + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_d709: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + status = "okay"; +}; + +&reg_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +&reg_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-pll"; +}; + +&reg_ldo1 { + regulator-name = "vdd-rtc"; +}; + +&reg_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +&reg_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&reg_usb0_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG12"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <&reg_usb0_vbus>; + usb1_vbus-supply = <&reg_ldo3>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 34729d2..7c1c025 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -25,6 +25,7 @@ F: configs/A13-OLinuXinoM_defconfig F: configs/Auxtek-T003_defconfig F: configs/Auxtek-T004_defconfig F: configs/CHIP_defconfig +F: configs/difrnce_dit4350_defconfig F: configs/Empire_electronix_d709_defconfig F: configs/inet98v_rev2_defconfig F: configs/mk802_a10s_defconfig diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig new file mode 100644 index 0000000..8fc6532 --- /dev/null +++ b/configs/difrnce_dit4350_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN5I=y +CONFIG_DRAM_CLK=408 +CONFIG_MMC0_CD_PIN="PG0" +CONFIG_USB0_VBUS_PIN="PG12" +CONFIG_USB0_VBUS_DET="PG1" +CONFIG_USB0_ID_DET="PG2" +CONFIG_AXP_GPIO=y +# CONFIG_VIDEO_HDMI is not set +CONFIG_VIDEO_LCD_MODE="x:480,y:272,depth:18,pclk_khz:12000,le:1,ri:43,up:1,lo:12,hs:1,vs:1,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="AXP0-0" +CONFIG_VIDEO_LCD_BL_EN="AXP0-1" +CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_USB_MUSB_HOST=y -- 2.7.2

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[U-Boot] [PATCH 1/2] sunxi: A23: Fix some revisions needing a different magic sram poke
by Hans de Goede 11 Mar '16

11 Mar '16

I've had this one a23 tablet which would not boot and I've finally figured out what the problem is by looking at the released boot0 code, it seems the magic sram controller poke which we need to do in s_init() depends on the revision of the a23. Specifically this change is needed to get the A23 SoC I have with the following serial to boot: "E6071AB 26Y7". Signed-off-by: Hans de Goede <hdegoede(a)redhat.com> --- arch/arm/cpu/armv7/sunxi/board.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index eb5f4b6..cb94855 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -113,11 +113,27 @@ int spl_board_load_image(void) void s_init(void) { -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23 - /* Magic (undocmented) value taken from boot0, without this DRAM - * access gets messed up (seems cache related) */ + /* + * Undocmented magic taken from boot0, without this DRAM + * access gets messed up (seems cache related). + * The boot0 sources describe this as: "config ema for cache sram" + */ +#if defined CONFIG_MACH_SUN6I setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); +#elif defined CONFIG_MACH_SUN8I_A23 + uint version; + + /* Unlock sram version info reg, read it, relock */ + setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); + version = readl(SUNXI_SRAMC_BASE + 0x24); + clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15)); + + if ((version & 0xffff0000) == 0x16500000) + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); + else /* 0x1661 ? */ + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0); #endif + #if defined CONFIG_MACH_SUN6I || \ defined CONFIG_MACH_SUN7I || \ defined CONFIG_MACH_SUN8I -- 2.7.2

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[U-Boot] exynos5: common: Enable CONFIG_USB_ETHER_RTL8152 ethernet support
by Anand Moon 11 Mar '16

11 Mar '16

Enable CONFIG_USB_ETHER_RTL8152 support for Odroid XU4 which has support for RTL8153-CG gigabit Ethernet adapter, connected over USB 3.0. commit 9dc8ba19c50fc0b1623c654bcfe6caa903a4c36c added support for Realtek 8152/8153 driver. Signed-off-by: Anand Moon <linux.amoon(a)gmail.com> --- Depends on: https://patchwork.ozlabs.org/patch/548453/ --- include/configs/exynos5-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 834a22f..5a7915c 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -170,6 +170,7 @@ #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_RTL8152 /* USB boot mode */ #define CONFIG_USB_BOOTING -- 1.9.1

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[U-Boot] [PATCH v2 0/3] x86: Support booting SeaBIOS
by Bin Meng 11 Mar '16

11 Mar '16

This is the initial attempt to support booting SeaBIOS from U-Boot. This is tested: - On Intel Crown Bay board with a PCIe graphics card, booting SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally. - On QEMU x86 target with U-Boot chain-loading SeaBIOS to install/boot a Windows XP OS. This series is available on u-boot-x86/seabios-working. Previous RFC patch @ http://patchwork.ozlabs.org/patch/523764/ Changes in v2: - Drop patches which were already applied - Add more detailed information for testing QEMU/SeaBIOS (eg: how to create 'disk.img') Bin Meng (3): x86: Support booting SeaBIOS x86: qemu: Enable ACPI table generation by default x86: Document how to play with SeaBIOS arch/x86/Kconfig | 10 ++++++++ arch/x86/include/asm/tables.h | 3 +++ arch/x86/lib/tables.c | 15 ++++++++++++ configs/qemu-x86_defconfig | 1 + doc/README.x86 | 57 +++++++++++++++++++++++++++++++++++++++++-- 5 files changed, 84 insertions(+), 2 deletions(-) -- 1.8.2.1

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