March 2016 - U-Boot

[U-Boot] [PATCH v1 1/3] fastboot: OUT transaction length must be aligned to wMaxPacketSize
by Dileep Katta 11 Mar '16

11 Mar '16

OUT transactions must be aligned to wMaxPacketSize for each transfer, or else transfer will not complete successfully. This patch modifies rx_bytes_expected to return a transfer length that is aligned to wMaxPacketSize. Note that the value of ep->desc->wMaxPacketSize and ep->maxpacket may not be the same value, and it is the value of ep->desc->wMaxPacketSize that should be used for alignment. Signed-off-by: Dileep Katta <dileep.katta(a)linaro.org> --- drivers/usb/gadget/f_fastboot.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index a8d8205..0d53a61 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -370,13 +370,20 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str(response); } -static unsigned int rx_bytes_expected(void) +static unsigned int rx_bytes_expected(unsigned maxpacket) { int rx_remain = download_size - download_bytes; + int rem = 0; if (rx_remain < 0) return 0; if (rx_remain > EP_BUFFER_SIZE) return EP_BUFFER_SIZE; + if (rx_remain < maxpacket) { + rx_remain = maxpacket; + } else if (rx_remain % maxpacket != 0) { + rem = rx_remain % maxpacket; + rx_remain = rx_remain + (maxpacket - rem); + } return rx_remain; } @@ -425,7 +432,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) printf("\ndownloading of %d bytes finished\n", download_bytes); } else { - req->length = rx_bytes_expected(); + req->length = rx_bytes_expected(ep->desc->wMaxPacketSize); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } @@ -453,7 +460,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) } else { sprintf(response, "DATA%08x", download_size); req->complete = rx_handler_dl_image; - req->length = rx_bytes_expected(); + req->length = rx_bytes_expected(ep->desc->wMaxPacketSize); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } -- 1.8.3.2

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[U-Boot] [PATCH 1/2] defconfig: ls1021aqds_sdcard_qspi: Enable SPI-NOR
by Alison Wang 10 Mar '16

10 Mar '16

As QSPI driver is supported in ls1021aqds_sdcard_qspi_defconfig, SPI-NOR with MTD uclass, CONFIG_MTD_DATAFLASH and new flash vendor config CONFIG_SPI_NOR_SPANSION need be enabled. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- configs/ls1021aqds_sdcard_qspi_defconfig | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index cd75af6..25ab3ee 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -7,8 +7,11 @@ CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart" # CONFIG_CMD_SETEXPR is not set CONFIG_OF_CONTROL=y CONFIG_DM=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_SPANSION=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_DATAFLASH=y +CONFIG_SPI_NOR_SPANSION=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_SYS_NS16550=y -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 0/5 v6] support mapping PCI device ids to stream ids for MSIs
by Stuart Yoder 10 Mar '16

10 Mar '16

From: Stuart Yoder <stuart.yoder(a)nxp.com> A binding for PCI nodes has been finalized specifying how PCI device IDs can be mapped to MSI specifiers. See Documentation/devicetree/bindings/pci/pci-msi.txt in the kernel. For ls2080a and similar Layerscape SoCs, the MSI specifier is the stream id. A programmable table (LUT) in the PCI controller defines the hardware mapping of PCI requester IDs to stream IDs. This patch series implements support for this mapping. Version 6 of the series squashes patches 4-7 together to avoid static functions defined but not used. This results in 5 patches: Patch 1 removes the obsolete available-stream-id support. Patch 2 updates stream ID partitioning info to be current Patch 3 updates pci.h so pci_get_hose_head() is available Patch 4 defines LUT register offsets Patch 5 implements a function to iterate over all PCI buses and set up a LUT entry and msi-map for all discovered devices. Helper functions allocate LUT entries, streamIDs, and append msi-map entries. This patch series enables MSIs on ls2080a on v4.5-rc5 and later kernels. The obsolete support removed was unused in any upstream kernels. -v2 changes -in patch 7 removed skip of the host bridge when scanning the bus -v3 changes -patch 4: moved LUT #defines to immap_lsch3.h, made index allocator return an int -patch 5: return 0xffffffff on error -patch 7: fixed return value checks -v4 changes -put all device ID to stream ID mapping under LS2 #ifdefs -v5 changes -check CONFIG_FSL_LSCH3 instead of SoC specific defines -v6 changes -squashed patches 4-7 together, split out LUT #defines into separate patch, replaced a remaining SoC define with CONFIG_FSL_LSCH3 Stuart Yoder (5): armv8: ls2080a: remove obsolete stream ID partitioning support armv8: ls2080a: update stream ID partitioning info pci: make pci_get_hose_head() available to external users pci/layerscape: add defines for LUT pci/layerscape: set LUT and msi-map for discovered PCI devices arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 113 ---------- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 + .../asm/arch-fsl-layerscape/ls2080a_stream_id.h | 55 +++-- drivers/pci/pcie_layerscape.c | 217 +++++++++++++------- include/pci.h | 1 + 5 files changed, 186 insertions(+), 204 deletions(-) -- 1.7.9.5

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[U-Boot] Invalid Certificate using imx28 and HAB
by Per Smitt 10 Mar '16

10 Mar '16

Hi everyone I am having a problem with a Freescale imx28 to get HAB (High Assurance Boot) working with U-Boot. I understand that this is a question regarding one specific processor model but since I have seen several patches from Marek Vasut which deal with this specific processor I am taking a chance that I can get some help here. What I have done is that I have started with a mainline U-Boot (v2016.01) and I have added/modified a few hab-related items. * board/freescale/mx28evk/sign/u-boot-spl.csf * board/freescale/mx28evk/sign/u-boot.csf * board/freescale/mx28evk/hab.h * board/freescale/mx28evk/hab_types.h * board/freescale/mx28evk/mx28evk.c A complete patch of these files is included. I am also not certain that my csf files are correct but I get HAB errors even before I get to that point so it should be irrelevant at the moment. The following files have been copied from the cst tool to the u-boot root directory. * CSF1_1_sha256_1024_65537_v3_usr_crt.pem * CSF1_1_sha256_1024_65537_v3_usr_key.pem * IMG1_1_sha256_1024_65537_v3_usr_crt.pem * IMG1_1_sha256_1024_65537_v3_usr_key.pem * srk_table.bin * srk_fuses.bin * key_pass.txt The certificates are generated with the CST tool downloaded from Freescale. The above example uses a 1024 bit RSA key but I have also tested with 2048 bits without any luck. The srk_table is generated using the Freescale srktool $ srktool -h 4 -t srk_table.bin -e srk_fuses.bin -d sha256 -c crts/SRK1_sha256_1024_65537_v3_ca_crt.pem -f 1 Once all this was in placed I built and ran it using $ make mrproper $ make mx28evk_nand_config $ make u-boot-signed.sb $ sudo mxsldr u-boot-signed.sb I get the following result: --------- HAB Event 1 ----------------- event data: 0xdb 0x00 0x14 0x40 0x33 0x21 0xc0 0x00 0xbe 0x00 0x0c 0x00 0x03 0x17 0x00 0x00 0x00 0x00 0x00 0x50 (HAB_INV_CERTIFICATE 0x21) --------- HAB Event 2 ----------------- event data: 0xdb 0x00 0x14 0x40 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0x00 0x00 0x00 0x20 (HAB_INV_ASSERTION 0x0C) --------- HAB Event 3 ----------------- event data: 0xdb 0x00 0x14 0x40 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x00 0x00 0x00 0x00 0x04 (HAB_INV_ASSERTION 0x0C) --------- HAB Event 4 ----------------- event data: 0xdb 0x00 0x14 0x40 0x33 0x21 0xc0 0x00 0xbe 0x00 0x0c 0x00 0x03 0x17 0x00 0x00 0x00 0x00 0x00 0x50 (HAB_INV_CERTIFICATE 0x21) --------- HAB Event 5 ----------------- event data: 0xdb 0x00 0x14 0x40 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x10 0x00 0x00 0x00 0x00 0x20 (HAB_INV_ASSERTION 0x0C) --------- HAB Event 6 ----------------- event data: 0xdb 0x00 0x14 0x40 0x33 0x0c 0xa0 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x20 0x00 0x00 0x00 0x00 0x04 (HAB_INV_ASSERTION 0x0C) We get two invalid certificates. These are from u-boot-spl and u-boot. The asserts are the execution of the unverified code. I'm at a loss what I might have done wrong and I am hoping Marek perhaps can help me with this issue. As I mentioned before I am not certain my csf files are correct. I suspect the Authenticate Data part might be wrong but if I get a signature error it would be another error code indicating a CSF verification error (HAB_INV_CSF 0x11). Another issue I also have is that I am not certain I have burned the fuses properly in the hardware but yet again that should cause a verification error and not an invalid certificate error. At least that is what I believe but now when typing this I am getting uncertain. If Marek or anyone can shed any light on this I am thankful for any assistance. Many thanks in advance, Per Smitt

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[U-Boot] [GIT PULL] u-boot-mips/master
by Daniel Schwierzeck 10 Mar '16

10 Mar '16

Hi Tom, two fixes for MIPS: - fix a build error on Travis CI for pic32mzdask board - fix cache op for toolchains not supporting __builtin_mips_cache() please consider pulling, thanks The following changes since commit deff6fb3a7790e93264292982000275e78bb12e5: malloc: remove !gd handling (2016-03-08 15:01:47 -0500) are available in the git repository at: git://git.denx.de/u-boot-mips.git master for you to fetch changes up to 40a09be2e925e6e4b56a236fec5aed2c002e9d6f: MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=y (2016-03-09 11:54:01 +0100) ---------------------------------------------------------------- Daniel Schwierzeck (1): MIPS: pic32mzdask: use CONFIG_USE_PRIVATE_LIBGCC=y Matthias Schiffer (1): MIPS: fix mips_cache fallback without __builtin_mips_cache arch/mips/include/asm/cacheops.h | 2 +- configs/pic32mzdask_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

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[U-Boot] Please pull u-boot-rockchip
by Simon Glass 10 Mar '16

10 Mar '16

Hi Tom, A few last-minute fixes. The following changes since commit deff6fb3a7790e93264292982000275e78bb12e5: malloc: remove !gd handling (2016-03-08 15:01:47 -0500) are available in the git repository at: git://git.denx.de/u-boot-rockchip.git for you to fetch changes up to b5788dc0dd9570e98552833767f4373db965985d: rockchip: rk3288: correct sdram setting (2016-03-10 08:32:01 -0700) ---------------------------------------------------------------- Chris Zhong (1): rockchip: rk3288: correct sdram setting FUKAUMI Naoki (1): rockchip: make configure_emmc() empty for Firefly-RK3288 Lin Huang (1): rockchip: rk3036: change ddr frequency to 400M arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) Regards, Simon

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[U-Boot] [PATCH] rockchip: rk3288: correct sdram setting
by Chris Zhong 10 Mar '16

10 Mar '16

The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2, and it expects uboot to store the value using a same protocol. But now the ddr setting value is different with DMC, so if you enable the DMC, system would crash in kernel. Correct the sdram setting here, according to the requirements of kernel. [0] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/ chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c Signed-off-by: Chris Zhong <zyw(a)rock-chips.com> --- arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 42 ++++++++--------- arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 61 +++++++++++-------------- 2 files changed, 48 insertions(+), 55 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h index fccabcd..f2e3130 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h @@ -459,26 +459,26 @@ enum { * [3:2] bw_ch0 * [1:0] dbw_ch0 */ -#define SYS_REG_DDRTYPE_SHIFT 13 -#define SYS_REG_DDRTYPE_MASK 7 -#define SYS_REG_NUM_CH_SHIFT 12 -#define SYS_REG_NUM_CH_MASK 1 -#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) -#define SYS_REG_ROW_3_4_MASK 1 -#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) -#define SYS_REG_RANK_MASK 1 -#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) -#define SYS_REG_COL_MASK 3 -#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) -#define SYS_REG_BK_MASK 1 -#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) -#define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) -#define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) -#define SYS_REG_BW_MASK 3 -#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) -#define SYS_REG_DBW_MASK 3 +#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) +#define SYS_REG_DEC_ROW_3_4(n, ch) ((n >> (30 + ch)) & 0x1) +#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) +#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) +#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) +#define SYS_REG_DEC_NUM_CH(n) (1 + ((n >> 12) & 0x1)) +#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) +#define SYS_REG_DEC_RANK(n, ch) (1 + ((n >> (11 + 16 * ch)) & 0x1)) +#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) +#define SYS_REG_DEC_COL(n, ch) (9 + ((n >> (9 + 16 * ch)) & 0x3)) +#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) \ + << (8 + ((ch) * 16))) +#define SYS_REG_DEC_BK(n, ch) (3 - ((n >> (8 + 16 * ch)) & 0x1)) +#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + ((ch) * 16))) +#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + ((n >> (6 + 16 * ch)) & 0x3)) +#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + ((ch) * 16))) +#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + ((n >> (4 + 16 * ch)) & 0x3)) +#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) +#define SYS_REG_DEC_BW(n, ch) (2 >> ((n >> (2 + 16 * ch)) & 0x3)) +#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) +#define SYS_REG_DEC_DBW(n, ch) (2 >> ((n >> (0 + 16 * ch)) & 0x3)) #endif diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index e9e2211..4db39ec 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -551,27 +551,27 @@ static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, static void dram_all_config(const struct dram_info *dram, const struct rk3288_sdram_params *sdram_params) { - unsigned int chan; + unsigned int channel; u32 sys_reg = 0; - sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; - sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; - for (chan = 0; chan < sdram_params->num_channels; chan++) { + sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->base.dramtype); + sys_reg |= SYS_REG_ENC_NUM_CH(sdram_params->num_channels); + for (channel = 0; channel < sdram_params->num_channels; channel++) { const struct rk3288_sdram_channel *info = - &sdram_params->ch[chan]; - - sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); - sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan); - sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); - sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); - sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0; - sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); - sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); - sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan); - sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan); - - dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); + &(sdram_params->ch[channel]); + sys_reg |= SYS_REG_ENC_ROW_3_4(info->row_3_4, channel); + sys_reg |= SYS_REG_ENC_CHINFO(channel); + sys_reg |= SYS_REG_ENC_RANK(info->rank, channel); + sys_reg |= SYS_REG_ENC_COL(info->col, channel); + sys_reg |= SYS_REG_ENC_BK(info->bk, channel); + sys_reg |= SYS_REG_ENC_CS0_ROW(info->cs0_row, channel); + sys_reg |= SYS_REG_ENC_CS1_ROW(info->cs1_row, channel); + sys_reg |= SYS_REG_ENC_BW(info->bw, channel); + sys_reg |= SYS_REG_ENC_DBW(info->dbw, channel); + + dram_cfg_rbc(&dram->chan[channel], channel, sdram_params); } + writel(sys_reg, &dram->pmu->sys_reg[2]); rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); } @@ -712,23 +712,16 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu) size_t size_mb = 0; u32 ch; u32 sys_reg = readl(&pmu->sys_reg[2]); - u32 chans; - - chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); - - for (ch = 0; ch < chans; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0; - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK; - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; + u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg); + + for (ch = 0; ch < ch_num; ch++) { + rank = SYS_REG_DEC_RANK(sys_reg, ch); + col = SYS_REG_DEC_COL(sys_reg, ch); + bk = SYS_REG_DEC_BK(sys_reg, ch); + cs0_row = SYS_REG_DEC_CS0_ROW(sys_reg, ch); + cs1_row = SYS_REG_DEC_CS1_ROW(sys_reg, ch); + bw = SYS_REG_DEC_BW(sys_reg, ch); + row_3_4 = SYS_REG_DEC_ROW_3_4(sys_reg, ch); chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); -- 2.6.3

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[U-Boot] [PATCH] rockchip: make configure_emmc() empty for Firefly-RK3288
by FUKAUMI Naoki 10 Mar '16

10 Mar '16

on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for Firefly-RK3288. (it's fine for Rock2) $ gcc --version gcc (Ubuntu/Linaro 5.3.0-3ubuntu1~14.04) 5.3.0 20151204 Copyright (C) 2015 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ ./tools/mkimage -n rk3288 -T rksd -d spl/u-boot-spl-dtb.bin u-boot-spl-dtb.img Warning: SPL image is too large (size 0x80d0) and will not boot to reduce size of SPL image, this patch makes configure_emmc() empty for Firefly-RK3288 as same as Rock2. Signed-off-by: FUKAUMI Naoki <naobsd(a)gmail.com> --- arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 6a54368..e133cca 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -114,7 +114,7 @@ static void configure_l2ctlr(void) #ifdef CONFIG_SPL_MMC_SUPPORT static int configure_emmc(struct udevice *pinctrl) { -#ifndef CONFIG_TARGET_ROCK2 +#if !defined(CONFIG_TARGET_ROCK2) && !defined(CONFIG_TARGET_FIREFLY_RK3288) struct gpio_desc desc; int ret; -- 2.7.2

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[U-Boot] [PATCH] rockchip: rk3036: change ddr frequency to 400M
by Jeffy Chen 10 Mar '16

10 Mar '16

From: Lin Huang <hl(a)rock-chips.com> emac may use dpll as clock parent, and it request the clock frequency multiples of 50, so change ddr frequency to 400M. Signed-off-by: Lin Huang <hl(a)rock-chips.com> Signed-off-by: Jeffy Chen <jeffy.chen(a)rock-chips.com> --- arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index e3ca870..ec8305c 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -37,7 +37,7 @@ struct rk3036_sdram_priv { /* use integer mode, 396MHz dpll setting * refdiv, fbdiv, postdiv1, postdiv2 */ -const struct pll_div dpll_init_cfg = {1, 66, 4, 1}; +const struct pll_div dpll_init_cfg = {1, 50, 3, 1}; /* 396Mhz ddr timing */ const struct rk3036_ddr_timing ddr_timing = {0x18c, -- 2.1.4

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[U-Boot] Possible using U-boot to load FreeRTOS and How ?
by Bertrand MERCIER 10 Mar '16

10 Mar '16

Hello, Is it possible to use U-boot in order to load FreeRTOS operating system (or other OS like microCOS), and how ? Thank you very much for your help Best Regards *Mr Bertrand MERCIER* *Ingénieur-Architecte Logiciel Temps Réel - * *06 11 73 13 85* *Real Time Software Architect Engineer* *+33 6 11 73 13 85*

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