March 2016 - U-Boot

[U-Boot] [PATCH] drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.
by Purna Chandra Mandal 16 Mar '16

16 Mar '16

PIC32 embedded flash banks are memory mapped, directly read by CPU, and programming (erase followed by write) operation on them are handled by on-chip NVM controller. Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- drivers/mtd/Kconfig | 6 + drivers/mtd/Makefile | 1 + drivers/mtd/pic32_flash.c | 377 ++++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 5 +- 4 files changed, 388 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/pic32_flash.c diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index c58841e..e3c6b9f 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -30,6 +30,12 @@ config ALTERA_QSPI endmenu +config FLASH_PIC32 + bool "Microchip PIC32 Flash driver" + help + This enables access to Microchip PIC32 internal non-CFI flash + chips through PIC32 Non-Volatile-Memory Controller. + source "drivers/mtd/nand/Kconfig" source "drivers/mtd/spi/Kconfig" diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 7f018a4..9380085 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -19,4 +19,5 @@ obj-$(CONFIG_HAS_DATAFLASH) += dataflash.o obj-$(CONFIG_FTSMC020) += ftsmc020.o obj-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o obj-$(CONFIG_MW_EEPROM) += mw_eeprom.o +obj-$(CONFIG_FLASH_PIC32) += pic32_flash.o obj-$(CONFIG_ST_SMI) += st_smi.o diff --git a/drivers/mtd/pic32_flash.c b/drivers/mtd/pic32_flash.c new file mode 100644 index 0000000..9a226b1 --- /dev/null +++ b/drivers/mtd/pic32_flash.c @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2015 + * Cristian Birsan <cristian.birsan(a)microchip.com> + * Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <flash.h> +#include <mach/pic32.h> +#include <wait_bit.h> + +/* NVM Controller registers */ +struct pic32_reg_nvm { + struct pic32_reg_atomic ctrl; + struct pic32_reg_atomic key; + struct pic32_reg_atomic addr; + struct pic32_reg_atomic data; +}; + +/* NVM operations */ +#define NVMOP_NOP 0 +#define NVMOP_WORD_WRITE 1 +#define NVMOP_PAGE_ERASE 4 + +/* NVM control bits */ +#define NVM_WR BIT(15) +#define NVM_WREN BIT(14) +#define NVM_WRERR BIT(13) +#define NVM_LVDERR BIT(12) + +/* NVM programming unlock register */ +#define LOCK_KEY 0x0 +#define UNLOCK_KEY1 0xaa996655 +#define UNLOCK_KEY2 0x556699aa + +/* PIC32 flash banks consist of number of pages, each page + * into number of row and rows are into number of words. + * Here we will maintain page information instead of sector. + */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; +static struct pic32_reg_nvm *nvm_regs_p; + +static inline void flash_initiate_operation(u32 nvmop) +{ + /* set operation */ + writel(nvmop, &nvm_regs_p->ctrl.raw); + + /* enable flash write */ + writel(NVM_WREN, &nvm_regs_p->ctrl.set); + + /* unlock sequence */ + writel(LOCK_KEY, &nvm_regs_p->key.raw); + writel(UNLOCK_KEY1, &nvm_regs_p->key.raw); + writel(UNLOCK_KEY2, &nvm_regs_p->key.raw); + + /* initiate operation */ + writel(NVM_WR, &nvm_regs_p->ctrl.set); +} + +static int flash_wait_till_busy(const char *func, ulong timeout) +{ + int ret = wait_for_bit(__func__, &nvm_regs_p->ctrl.raw, + NVM_WR, false, timeout, false); + + return ret ? ERR_TIMOUT : ERR_OK; +} + +static inline int flash_complete_operation(void) +{ + u32 v; + + v = readl(&nvm_regs_p->ctrl.raw); + if (v & NVM_WRERR) { + printf("Error in Block Erase - Lock Bit may be set!\n"); + flash_initiate_operation(NVMOP_NOP); + return ERR_PROTECTED; + } + + if (v & NVM_LVDERR) { + printf("Error in Block Erase - low-vol detected!\n"); + flash_initiate_operation(NVMOP_NOP); + return ERR_NOT_ERASED; + } + + /* disable flash write or erase operation */ + writel(NVM_WREN, &nvm_regs_p->ctrl.clr); + + return ERR_OK; +} + +int flash_erase(flash_info_t *info, int s_first, int s_last) +{ + ulong sect_start, sect_end, flags; + int prot, sect; + int rc; + + if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_MCHP) { + printf("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return ERR_UNKNOWN_FLASH_VENDOR; + } + + if ((s_first < 0) || (s_first > s_last)) { + printf("- no sectors to erase\n"); + return ERR_INVAL; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) + prot++; + } + + if (prot) + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + else + printf("\n"); + + /* erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect]) + continue; + + /* disable interrupts */ + flags = disable_interrupts(); + + /* write destination page address (physical) */ + sect_start = virt_to_phys((void *)info->start[sect]); + writel(sect_start, &nvm_regs_p->addr.raw); + + /* page erase */ + flash_initiate_operation(NVMOP_PAGE_ERASE); + + /* wait */ + rc = flash_wait_till_busy(__func__, + CONFIG_SYS_FLASH_ERASE_TOUT); + + /* re-enable interrupts if necessary */ + if (flags) + enable_interrupts(); + + if (rc != ERR_OK) + return rc; + + rc = flash_complete_operation(); + if (rc != ERR_OK) + return rc; + + /* flash content is updated but cache might contain stale + * data, so invalidate dcache. + */ + sect_end = info->start[sect] + info->size / info->sector_count; + invalidate_dcache_range(info->start[sect], sect_end); + } + + printf(" done\n"); + return ERR_OK; +} + +int page_erase(flash_info_t *info, int sect) +{ + return 0; +} + +/* Write a word to flash */ +static int write_word(flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong flags; + int rc; + + /* check if flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf("Error, Flash not erased!\n"); + return ERR_NOT_ERASED; + } + + /* disable interrupts */ + flags = disable_interrupts(); + + /* update destination page address (physical) */ + writel(virt_to_phys(addr), &nvm_regs_p->addr.raw); + writel(data, &nvm_regs_p->data.raw); + + /* word write */ + flash_initiate_operation(NVMOP_WORD_WRITE); + + /* wait for operation to complete */ + rc = flash_wait_till_busy(__func__, CONFIG_SYS_FLASH_WRITE_TOUT); + + /* re-enable interrupts if necessary */ + if (flags) + enable_interrupts(); + + if (rc != ERR_OK) + return rc; + + return flash_complete_operation(); +} + +/* Copy memory to flash, returns: + * ERR_OK - OK + * ERR_TIMOUT - write timeout + * ERR_NOT_ERASED - Flash not erased + */ +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong wp, data, len = cnt; + int i, l, rc; + uchar *cp; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + l = addr - wp; + if (l != 0) { + data = 0; + for (i = 0, cp = (uchar *)wp; i < l; ++i, ++cp) + data = (data << 8) | *cp; + + for (; (i < 4) && (cnt > 0); ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; (cnt == 0) && (i < 4); ++i, ++cp) + data = (data << 8) | *cp; + + rc = write_word(info, wp, __swab32(data)); + if (rc) + goto out; + + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) + data = (data << 8) | *src++; + + rc = write_word(info, wp, __swab32(data)); + if (rc) + goto out; + + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + rc = ERR_OK; + goto out; + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = (uchar *)wp; (i < 4) && (cnt > 0); ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + + for (; i < 4; ++i, ++cp) + data = (data << 8) | *cp; + + rc = write_word(info, wp, __swab32(data)); + +out: + /* flash content updated by nvm controller, + * but cache might have stale, so invalidate dcache. + */ + invalidate_dcache_range(addr, addr + len); + + printf(" done\n"); + return rc; +} + +void flash_print_info(flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_MCHP: + printf("Microchip Technology"); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_MCHP100T: + printf("Internal (8 Mbit, 64 x 16k)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + + printf(" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf("\n"); +} + +unsigned long flash_init(void) +{ + phys_addr_t flash_banks[] = CONFIG_SYS_FLASH_BANKS_LIST; + flash_info_t *info = &flash_info[0]; + ulong total_size = 0; + ulong sect_size; + ulong base; + int bank, sect; + + sect_size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_SECT; + for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) { + /* combined device & manufacturer code */ + info->flash_id = FLASH_MAN_MCHP | FLASH_MCHP100T; + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + info->size = CONFIG_SYS_FLASH_SIZE; + + /* update sector (i.e page) info */ + base = (ulong)phys_to_virt(flash_banks[bank]); + for (sect = 0; sect < info->sector_count; sect++) { + info->start[sect] = base; + /* protect each sector by default */ + info->protect[sect] = 1; + base += sect_size; + } + total_size += info->size; + } + + /* NVM controller iobase */ + nvm_regs_p = ioremap(PIC32_NVM_BASE, sizeof(*nvm_regs_p)); + + /* disable flash write/erase operations */ + writel(NVM_WREN, &nvm_regs_p->ctrl.clr); + +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[0]); +#endif + +#ifdef CONFIG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + return total_size; +} diff --git a/include/flash.h b/include/flash.h index f53ace7..c9aacd5 100644 --- a/include/flash.h +++ b/include/flash.h @@ -400,6 +400,9 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ #define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/ +#define FLASH_MCHP100T 0x0060 /* MCHP internal (1M = 64K x 16) */ +#define FLASH_MCHP100B 0x0061 /* MCHP internal (1M = 64K x 16) */ + #define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ #define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ @@ -486,7 +489,7 @@ extern flash_info_t *flash_get_info(ulong base); #define FLASH_MAN_SHARP 0x00500000 #define FLASH_MAN_ATM 0x00600000 #define FLASH_MAN_CFI 0x01000000 - +#define FLASH_MAN_MCHP 0x02000000 /* Microchip Technology */ #define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ #define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */ -- 1.8.3.1

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[U-Boot] [PATCH] sunxi: chip: enable composite video out
by Maxime Ripard 16 Mar '16

16 Mar '16

From: Alex Kaplan <kaplan2539(a)gmail.com> The CHIP has a composite video output in the mini-Jack connector, alongside with the 2 audio channels. Enable this output in U-Boot. Signed-off-by: Alex Kaplan <kaplan2539(a)gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard(a)free-electrons.com> --- configs/CHIP_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index 3135d1c88e79..4f99d1efdf9e 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y # CONFIG_MMC is not set CONFIG_USB0_VBUS_PIN="PB10" +CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip" CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" -- 2.7.1

2 1

[U-Boot] [PATCH] sunxi: fix DCDC2 output in CHIP_defconfig
by Maxime Ripard 16 Mar '16

16 Mar '16

From: Boris Brezillon <boris.brezillon(a)free-electrons.com> Unlike the datasheet recommendation, the R8 SoC requires a 1.4V supply for its CPU when operating at 1Ghz. Rely on the default value specified in the Kconfig entry. Signed-off-by: Boris Brezillon <boris.brezillon(a)free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard(a)free-electrons.com> --- configs/CHIP_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index 78b2c511bfa2..3135d1c88e79 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -9,7 +9,6 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2" # CONFIG_CMD_IMLS is not set CONFIG_CMD_GPIO=y -CONFIG_AXP_DCDC2_VOLT=1300 CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_USB_MUSB_GADGET=y -- 2.7.1

3 3

[U-Boot] [PATCH] sunxi: video: Configure only LVDS pins instead of all LCD pins when LVDS interface selected
by Lawrence Yu 16 Mar '16

16 Mar '16

The behavior before this patch would attempt to configure the mux setting for pins 0 to 27 on PORTD to all be setting 3 for LVDS. The LVDS interface actually only uses pins 18 to 27 and not pins 0 to 27 as in the parallel LCD interface. This patch restricts the configuration to only the relevant pins 18 to 27 on PORTD. This was tested on a sun8i A33 tablet with an LVDS screen. MMC1 has the capability to use pins 2 to 7 on PORTD and the mux on those pins was being inadvertently set to setting 3 for MMC functionality which this patch corrects. Signed-off-by: Lawrence Yu <lyu(a)micile.com> --- drivers/video/sunxi_display.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 9fee66a..3674ae1 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -767,7 +767,11 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode, (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; int bp, clk_delay, clk_div, clk_double, pin, total, val; +#ifdef CONFIG_VIDEO_LCD_IF_LVDS + for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) { +#else for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) { +#endif #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0); #endif -- 2.5.3

2 1

Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2
by Michael Haas 16 Mar '16

16 Mar '16

On 03/15/2016 07:09 PM, Karsten Merker wrote: > On Tue, Mar 15, 2016 at 06:41:39AM +0100, Michael Haas wrote: > >> This change is required to get GBIT Ethernet to work >> reliably on my board. Without CONFIG_GMAC_TX_DELAY=4, the connection >> suffers severe packet loss and SSH becomes unusable. >> >> --- 192.168.1.1 ping statistics --- >> 100 packets transmitted, 100 received, 0% packet loss, time 19842ms >> rtt min/avg/max/mdev = 0.260/0.334/0.527/0.038 ms >> >> I have also tried CONFIG_GMAC_TX_DELAY=3, which still >> yielded 11-13% packet loss. > Hello, > > unfortunately this change doesn't solve the gigabit issues > on my LIME2 - it even seems to make them worse on my board. > > > Could you perhaps try netbooting a kernel with your LIME2? > I would be interested in knowing whether that works on your > board (with CONFIG_GMAC_TX_DELAY=0/4). > > Hello Karsten, I just tried netbooting the debian installer: it didn't work, just as you said. Even worse: I noticed I had not installed my patched u-boot at all when I ran the ping test above! With my patch, the kernel would not download at all. So the patch is wrong and I'm sorry for having wasted everyone's time here. I won't give up yet, however. The fact still stands that at some point, I was able to use GBit Ethernet without any issues in Linux, possibly after a warm reboot. For (my) future reference, I used these commands: -- setenv bootargs console=ttyS0,115200 rootwait panic=10 setenv autoload no dhcp setenv serverip 192.168.1.170 tftpboot ${scriptaddr} /debian-installer/armhf/tftpboot.scr source ${scriptaddr} -- I'll be playing around with the value a bit more to find the "best" value for netbooting from a cold state, then try to get it to work within Linux itself. Perhaps there are also some clock adjusts to be done from within the DTS. Sorry again! Michael

2 2

[U-Boot] [PATCH v8 9/9] mips: ath79: add AP143 reference board
by Wills Wang 16 Mar '16

16 Mar '16

This patch add board-level code and base DT for AP143. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v8: - Move board/ath79/ap143 into board/qca/ap143 - Move SYS_VENDOR into board-level for ap143 Changes in v7: - Use KSEG1 address for debug port in ap143 Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/dts/Makefile | 1 + arch/mips/dts/ap143.dts | 43 +++++++++++++++++++++ arch/mips/dts/qca953x.dtsi | 84 ++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 5 +++ board/qca/ap143/Kconfig | 12 ++++++ board/qca/ap143/MAINTAINERS | 6 +++ board/qca/ap143/Makefile | 5 +++ board/qca/ap143/ap143.c | 66 ++++++++++++++++++++++++++++++++ configs/ap143_defconfig | 45 ++++++++++++++++++++++ include/configs/ap143.h | 91 ++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 358 insertions(+) create mode 100644 arch/mips/dts/ap143.dts create mode 100644 arch/mips/dts/qca953x.dtsi create mode 100644 board/qca/ap143/Kconfig create mode 100644 board/qca/ap143/MAINTAINERS create mode 100644 board/qca/ap143/Makefile create mode 100644 board/qca/ap143/ap143.c create mode 100644 configs/ap143_defconfig create mode 100644 include/configs/ap143.h diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 30e5c68..bd87ead 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -3,6 +3,7 @@ # dtb-$(CONFIG_TARGET_AP121) += ap121.dtb +dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/ap143.dts b/arch/mips/dts/ap143.dts new file mode 100644 index 0000000..f53207e --- /dev/null +++ b/arch/mips/dts/ap143.dts @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "qca953x.dtsi" + +/ { + model = "AP143 Reference Board"; + compatible = "qca,ap143", "qca,qca953x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x9f000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/dts/qca953x.dtsi b/arch/mips/dts/qca953x.dtsi new file mode 100644 index 0000000..870010f --- /dev/null +++ b/arch/mips/dts/qca953x.dtsi @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include "skeleton.dtsi" + +/ { + compatible = "qca,qca953x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + pinctrl { + u-boot,dm-pre-reloc; + compatible = "qca,qca953x-pinctrl"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18040000 0x100>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@18020000 { + compatible = "ns16550"; + reg = <0x18020000 0x20>; + reg-shift = <2>; + clock-frequency = <25000000>; + interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index c3012f8..f45403b 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -29,8 +29,13 @@ config TARGET_AP121 bool "AP121 Reference Board" select SOC_AR933X +config TARGET_AP143 + bool "AP143 Reference Board" + select SOC_QCA953X + endchoice source "board/qca/ap121/Kconfig" +source "board/qca/ap143/Kconfig" endmenu diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig new file mode 100644 index 0000000..4cdac0d --- /dev/null +++ b/board/qca/ap143/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AP143 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap143" + +config SYS_CONFIG_NAME + default "ap143" + +endif diff --git a/board/qca/ap143/MAINTAINERS b/board/qca/ap143/MAINTAINERS new file mode 100644 index 0000000..11cb14f --- /dev/null +++ b/board/qca/ap143/MAINTAINERS @@ -0,0 +1,6 @@ +AP143 BOARD +M: Wills Wang <wills.wang(a)live.com> +S: Maintained +F: board/qca/ap143/ +F: include/configs/ap143.h +F: configs/ap143_defconfig diff --git a/board/qca/ap143/Makefile b/board/qca/ap143/Makefile new file mode 100644 index 0000000..00f7837 --- /dev/null +++ b/board/qca/ap143/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap143.o diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c new file mode 100644 index 0000000..1572472 --- /dev/null +++ b/board/qca/ap143/ap143.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <debug_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* + * GPIO9 as input, GPIO10 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val |= QCA953X_GPIO(9); + val &= ~QCA953X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable GPIO10 as UART0_SOUT + */ + val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2); + val &= ~QCA953X_GPIO_MUX_MASK(16); + val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16; + writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2); + + /* + * Enable GPIO9 as UART0_SIN + */ + val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0); + val &= ~QCA953X_GPIO_MUX_MASK(8); + val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8; + writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0); + + /* + * Enable GPIO10 output + */ + val = readl(regs + AR71XX_GPIO_REG_OUT); + val |= QCA953X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OUT); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + ddr_init(); + return 0; +} diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig new file mode 100644 index 0000000..aa071be --- /dev/null +++ b/configs/ap143_defconfig @@ -0,0 +1,45 @@ +CONFIG_MIPS=y +CONFIG_SYS_MALLOC_F_LEN=0x800 +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ARCH_ATH79=y +CONFIG_TARGET_AP143=y +CONFIG_DEFAULT_DEVICE_TREE="ap143" +CONFIG_SYS_PROMPT="ap143 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_QCA953X_PINCTRL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xb8020000 +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_SYS_NS16550=y +CONFIG_ATH79_SPI=y diff --git a/include/configs/ap143.h b/include/configs/ap143.h new file mode 100644 index 0000000..6940551 --- /dev/null +++ b/include/configs/ap143.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0x9f000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 325 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 0x8000 +#define CONFIG_SYS_ICACHE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 25000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock2 " \ + "rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f300000" +#define CONFIG_LZMA +#define CONFIG_OF_LIBFDT + +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ + "256k(u-boot),64k(u-boot-env)," \ + "2752k(rootfs),896k(uImage)," \ + "64k(NVRAM),64k(ART)" + +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 + +/* + * Command + */ +#define CONFIG_CMD_MTDPARTS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#endif /* __CONFIG_H */ -- 1.9.1

1 0

[U-Boot] [PATCH v8 8/9] mips: ath79: add AP121 reference board
by Wills Wang 16 Mar '16

16 Mar '16

This patch add board-level code and base DT for AP121. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v8: - Move board/ath79/ap121 into board/qca/ap121 - Move SYS_VENDOR into board-level for ap121 Changes in v7: - Use KSEG1 address for debug port in ap121 Changes in v6: - Convert SZ_XXX into hex in ap121.h - Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h - Add board_early_init_f for DDR and pin initialization - Select UART and SPI in ap121_defconfig Changes in v5: - Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk - Remove useless README file - Remove useless checkboard function Changes in v4: None Changes in v3: - Add support for device tree Changes in v2: - Add a reference board implemention arch/mips/dts/Makefile | 1 + arch/mips/dts/ap121.dts | 43 ++++++++++++++++++++++ arch/mips/dts/ar933x.dtsi | 82 +++++++++++++++++++++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 11 ++++++ board/qca/ap121/Kconfig | 12 ++++++ board/qca/ap121/MAINTAINERS | 6 +++ board/qca/ap121/Makefile | 5 +++ board/qca/ap121/ap121.c | 50 +++++++++++++++++++++++++ configs/ap121_defconfig | 46 +++++++++++++++++++++++ include/configs/ap121.h | 87 ++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 343 insertions(+) create mode 100644 arch/mips/dts/ap121.dts create mode 100644 arch/mips/dts/ar933x.dtsi create mode 100644 board/qca/ap121/Kconfig create mode 100644 board/qca/ap121/MAINTAINERS create mode 100644 board/qca/ap121/Makefile create mode 100644 board/qca/ap121/ap121.c create mode 100644 configs/ap121_defconfig create mode 100644 include/configs/ap121.h diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index b513918..30e5c68 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -2,6 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts new file mode 100644 index 0000000..e31f601 --- /dev/null +++ b/arch/mips/dts/ap121.dts @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ar933x.dtsi" + +/ { + model = "AP121 Reference Board"; + compatible = "qca,ap121", "qca,ar933x"; + + aliases { + spi0 = &spi0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&xtal { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x9f000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi new file mode 100644 index 0000000..11f60a2 --- /dev/null +++ b/arch/mips/dts/ar933x.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include "skeleton.dtsi" + +/ { + compatible = "qca,ar933x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + pinctrl { + u-boot,dm-pre-reloc; + compatible = "qca,ar933x-pinctrl"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x18040000 0x100>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x20>; + interrupts = <128 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + interrupts = <129 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index e35f1b5..c3012f8 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -22,4 +22,15 @@ config SOC_QCA953X help This supports QCA/Atheros qca953x family SOCs. +choice + prompt "Board select" + +config TARGET_AP121 + bool "AP121 Reference Board" + select SOC_AR933X + +endchoice + +source "board/qca/ap121/Kconfig" + endmenu diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig new file mode 100644 index 0000000..f7e768a --- /dev/null +++ b/board/qca/ap121/Kconfig @@ -0,0 +1,12 @@ +if TARGET_AP121 + +config SYS_VENDOR + default "qca" + +config SYS_BOARD + default "ap121" + +config SYS_CONFIG_NAME + default "ap121" + +endif diff --git a/board/qca/ap121/MAINTAINERS b/board/qca/ap121/MAINTAINERS new file mode 100644 index 0000000..8b02988 --- /dev/null +++ b/board/qca/ap121/MAINTAINERS @@ -0,0 +1,6 @@ +AP121 BOARD +M: Wills Wang <wills.wang(a)live.com> +S: Maintained +F: board/qca/ap121/ +F: include/configs/ap121.h +F: configs/ap121_defconfig diff --git a/board/qca/ap121/Makefile b/board/qca/ap121/Makefile new file mode 100644 index 0000000..ced5432 --- /dev/null +++ b/board/qca/ap121/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = ap121.o diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c new file mode 100644 index 0000000..d6c60fe --- /dev/null +++ b/board/qca/ap121/ap121.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <debug_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + void __iomem *regs; + u32 val; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* + * GPIO9 as input, GPIO10 as output + */ + val = readl(regs + AR71XX_GPIO_REG_OE); + val &= ~AR933X_GPIO(9); + val |= AR933X_GPIO(10); + writel(val, regs + AR71XX_GPIO_REG_OE); + + /* + * Enable UART, GPIO9 as UART_SI, GPIO10 as UART_SO + */ + val = readl(regs + AR71XX_GPIO_REG_FUNC); + val |= AR933X_GPIO_FUNC_UART_EN | AR933X_GPIO_FUNC_RES_TRUE; + writel(val, regs + AR71XX_GPIO_REG_FUNC); +} +#endif + +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + ddr_init(); + return 0; +} diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig new file mode 100644 index 0000000..6ba1e29 --- /dev/null +++ b/configs/ap121_defconfig @@ -0,0 +1,46 @@ +CONFIG_MIPS=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_ARCH_ATH79=y +CONFIG_TARGET_AP121=y +CONFIG_DEFAULT_DEVICE_TREE="ap121" +CONFIG_SYS_PROMPT="ap121 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_AR933X_PINCTRL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_AR933X=y +CONFIG_DEBUG_UART_BASE=0xb8020000 +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_AR933X_UART=y +CONFIG_ATH79_SPI=y diff --git a/include/configs/ap121.h b/include/configs/ap121.h new file mode 100644 index 0000000..b06969b --- /dev/null +++ b/include/configs/ap121.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0x9f000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 200 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 0x8000 +#define CONFIG_SYS_ICACHE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock2 " \ + "rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND "sf probe;" \ + "mtdparts default;" \ + "bootm 0x9f300000" +#define CONFIG_LZMA +#define CONFIG_OF_LIBFDT + +#define MTDIDS_DEFAULT "nor0=spi-flash.0" +#define MTDPARTS_DEFAULT "mtdparts=spi-flash.0:" \ + "256k(u-boot),64k(u-boot-env)," \ + "2752k(rootfs),896k(uImage)," \ + "64k(NVRAM),64k(ART)" + +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 + +/* + * Command + */ +#define CONFIG_CMD_MTDPARTS + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#endif /* __CONFIG_H */ -- 1.9.1

1 0

[U-Boot] [PATCH v8 7/9] drivers: spi: add spi support for QCA/Atheros ath79 SOCs
by Wills Wang 16 Mar '16

16 Mar '16

This patch add a compatible spi driver for ath79 series SOC. Reviewed-by: Thomas Chou <thomas(a)wytron.com.tw> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck(a)gmail.com> Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v8: - Remove ath79_spi_write/read - Use pinctrl for spi - Add Kconfig dependence for spi option - Use dev_get_parent Changes in v7: - Define spi_cs_activate/spi_cs_deactivate - Rename MHZ to ATH79_SPI_MHZ - Use clrsetbits_32 Changes in v6: - Add rrw_delay in ath79_spi_priv for more accurate timing - Remove ath79_spi_delay - Calculate delay in ath79_spi_set_speed Changes in v5: - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation Changes in v4: - Use get_bus_freq instead of hardcode in SPI driver Changes in v3: - Convert spi driver to driver model Changes in v2: - Add a compatible spi driver doc/device-tree-bindings/spi/spi-ath79.txt | 19 +++ drivers/spi/Kconfig | 9 ++ drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 240 +++++++++++++++++++++++++++++ 4 files changed, 269 insertions(+) create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/spi/ath79_spi.c diff --git a/doc/device-tree-bindings/spi/spi-ath79.txt b/doc/device-tree-bindings/spi/spi-ath79.txt new file mode 100644 index 0000000..3fd9d67 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-ath79.txt @@ -0,0 +1,19 @@ +Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller + +Required properties: +- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback. +- reg: Base address and size of the controllers memory area +- #address-cells: <1>, as required by generic SPI binding. +- #size-cells: <0>, also as required by generic SPI binding. + +Child nodes as per the generic SPI binding. + +Example: + + spi@1f000000 { + compatible = "qca,ar9132-spi", "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2cdb110..c6662b3 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -23,6 +23,15 @@ config ALTERA_SPI IP core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATH79_SPI + bool "Atheros SPI driver" + depends on ARCH_ATH79 + help + Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used + to access SPI NOR flash and other SPI peripherals. This driver + uses driver model and requires a device tree binding to operate. + please refer to doc/device-tree-bindings/spi/spi-ath79.txt. + config CADENCE_QSPI bool "Cadence QSPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3eca745..7fb2926 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o +obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c new file mode 100644 index 0000000..0c1022d --- /dev/null +++ b/drivers/spi/ath79_spi.c @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spi.h> +#include <dm.h> +#include <div64.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <dm/pinctrl.h> +#include <mach/ar71xx_regs.h> + +/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */ +#define ATH79_SPI_CLK_DIV(x) (((x) >> 1) - 1) +#define ATH79_SPI_RRW_DELAY_FACTOR 12000 +#define ATH79_SPI_MHZ (1000 * 1000) + +struct ath79_spi_priv { + void __iomem *regs; + u32 rrw_delay; +}; + +static void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct ath79_spi_priv *priv = dev_get_priv(bus); + + writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS); + writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC); +} + +static void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev_get_parent(dev); + struct ath79_spi_priv *priv = dev_get_priv(bus); + + writel(AR71XX_SPI_IOC_CS_ALL, priv->regs + AR71XX_SPI_REG_IOC); + writel(0, priv->regs + AR71XX_SPI_REG_FS); +} + +static int ath79_spi_claim_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_release_bus(struct udevice *dev) +{ + return 0; +} + +static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct ath79_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev); + u8 *rx = din; + const u8 *tx = dout; + u8 curbyte, curbitlen, restbits; + u32 bytes = bitlen / 8; + u32 out, in; + u64 tick; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + restbits = (bitlen % 8); + if (restbits) + bytes++; + + out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave->cs)); + while (bytes > 0) { + bytes--; + curbyte = 0; + if (tx) + curbyte = *tx++; + + if (restbits && !bytes) { + curbitlen = restbits; + curbyte <<= 8 - restbits; + } else { + curbitlen = 8; + } + + for (curbyte <<= (8 - curbitlen); curbitlen; curbitlen--) { + if (curbyte & 0x80) + out |= AR71XX_SPI_IOC_DO; + else + out &= ~(AR71XX_SPI_IOC_DO); + + writel(out, priv->regs + AR71XX_SPI_REG_IOC); + + /* delay for low level */ + if (priv->rrw_delay) { + tick = get_ticks() + priv->rrw_delay; + while (get_ticks() < tick) + /*NOP*/; + } + + writel(out | AR71XX_SPI_IOC_CLK, + priv->regs + AR71XX_SPI_REG_IOC); + + /* delay for high level */ + if (priv->rrw_delay) { + tick = get_ticks() + priv->rrw_delay; + while (get_ticks() < tick) + /*NOP*/; + } + + curbyte <<= 1; + } + + if (!bytes) + writel(out, priv->regs + AR71XX_SPI_REG_IOC); + + in = readl(priv->regs + AR71XX_SPI_REG_RDS); + if (rx) { + if (restbits && !bytes) + *rx++ = (in << (8 - restbits)); + else + *rx++ = in; + } + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + return 0; +} + + +static int ath79_spi_set_speed(struct udevice *bus, uint speed) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + u32 val, div = 0; + u64 time; + + if (speed) + div = get_bus_freq(0) / speed; + + if (div > 63) + div = 63; + + if (div < 5) + div = 5; + + /* calculate delay */ + time = get_tbclk(); + do_div(time, speed / 2); + val = get_bus_freq(0) / ATH79_SPI_MHZ; + val = ATH79_SPI_RRW_DELAY_FACTOR / val; + if (time > val) + priv->rrw_delay = time - val + 1; + else + priv->rrw_delay = 0; + + writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS); + clrsetbits_be32(priv->regs + AR71XX_SPI_REG_CTRL, + AR71XX_SPI_CTRL_DIV_MASK, + ATH79_SPI_CLK_DIV(div)); + writel(0, priv->regs + AR71XX_SPI_REG_FS); + return 0; +} + +static int ath79_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static int ath79_spi_probe(struct udevice *bus) +{ + struct ath79_spi_priv *priv = dev_get_priv(bus); + struct udevice *pinctrl; + fdt_addr_t addr; + int ret; + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) + return ret; + ret = pinctrl_get_periph_id(pinctrl, bus); + if (ret < 0) + return ret; + ret = pinctrl_request(pinctrl, ret, 0); + if (ret < 0) + return ret; + + addr = dev_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = map_physmem(addr, + AR71XX_SPI_SIZE, + MAP_NOCACHE); + + /* Init SPI Hardware, disable remap, set clock */ + writel(AR71XX_SPI_FS_GPIO, priv->regs + AR71XX_SPI_REG_FS); + writel(AR71XX_SPI_CTRL_RD | ATH79_SPI_CLK_DIV(8), + priv->regs + AR71XX_SPI_REG_CTRL); + writel(0, priv->regs + AR71XX_SPI_REG_FS); + + return 0; +} + +static int ath79_cs_info(struct udevice *bus, uint cs, + struct spi_cs_info *info) +{ + /* Always allow activity on CS 0/1/2 */ + if (cs >= 3) + return -ENODEV; + + return 0; +} + +static const struct dm_spi_ops ath79_spi_ops = { + .claim_bus = ath79_spi_claim_bus, + .release_bus = ath79_spi_release_bus, + .xfer = ath79_spi_xfer, + .set_speed = ath79_spi_set_speed, + .set_mode = ath79_spi_set_mode, + .cs_info = ath79_cs_info, +}; + +static const struct udevice_id ath79_spi_ids[] = { + { .compatible = "qca,ar7100-spi" }, + {} +}; + +U_BOOT_DRIVER(ath79_spi) = { + .name = "ath79_spi", + .id = UCLASS_SPI, + .of_match = ath79_spi_ids, + .ops = &ath79_spi_ops, + .priv_auto_alloc_size = sizeof(struct ath79_spi_priv), + .probe = ath79_spi_probe, +}; -- 1.9.1

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Re: [U-Boot] [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared
by Wang Dongsheng 16 Mar '16

16 Mar '16

Hi Hongbo, On 03/16/2016 03:47 PM, Hongbo Zhang wrote: > Hi Dongsheng, > >> -----Original Message----- >> From: Chenhui Zhao >> Sent: Wednesday, March 16, 2016 3:05 PM >> To: Hongbo Zhang <hongbo.zhang(a)nxp.com> >> Cc: trini(a)konsulko.com; sbabic(a)denx.de; ijc(a)hellion.org.uk; >> hdegoede(a)redhat.com; twarren(a)nvidia.com; Huan Wang >> <alison.wang(a)nxp.com>; york sun <york.sun(a)nxp.com>; >> jan.kiszka(a)siemens.com; Frank Li <frank.li(a)nxp.com>; Peng Fan >> <peng.fan(a)nxp.com>; Zhengxiong Jin <jason.jin(a)nxp.com>; >> oss(a)buserror.net; u-boot(a)lists.denx.de; albert.u.boot(a)aribaud.net >> Subject: Re: [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack >> no longer is shared >> >> Add Hongbo. >> >> Thanks, >> Chenhui >> >> ________________________________________ >> From: Dongsheng Wang <dongsheng.wang(a)nxp.com> >> Sent: Monday, January 18, 2016 12:27 PM >> To: albert.u.boot(a)aribaud.net >> Cc: trini(a)konsulko.com; sbabic(a)denx.de; ijc(a)hellion.org.uk; >> hdegoede(a)redhat.com; twarren(a)nvidia.com; Huan Wang; york sun; >> jan.kiszka(a)siemens.com; Frank Li; Peng Fan; Zhengxiong Jin; Chenhui Zhao; >> oss(a)buserror.net; u-boot(a)lists.denx.de; Dongsheng Wang >> Subject: [PATCH 3/9] ARM: ARMv7: PSCI: move target PC in each CPU stack no >> longer is shared >> >> From: Wang Dongsheng <dongsheng.wang(a)nxp.com> >> >> All of cpu share the same targetPC space that is unsafe. So move target PC save >> space into CPU stack. >> >> Signed-off-by: Wang Dongsheng <dongsheng.wang(a)nxp.com> >> --- >> arch/arm/cpu/armv7/ls102xa/psci.S | 4 +-- >> arch/arm/cpu/armv7/mx7/psci.S | 4 +-- >> arch/arm/cpu/armv7/psci.S | 51 ++++++++++++++++++++++++++++---- >> --- >> arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 +-- >> arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 4 +-- >> arch/arm/cpu/armv7/virt-dt.c | 3 ++- >> arch/arm/include/asm/psci.h | 4 +++ >> arch/arm/mach-tegra/psci.S | 4 +-- >> 8 files changed, 53 insertions(+), 25 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S >> b/arch/arm/cpu/armv7/ls102xa/psci.S >> index 0b067d9..3a34064 100644 >> --- a/arch/arm/cpu/armv7/ls102xa/psci.S >> +++ b/arch/arm/cpu/armv7/ls102xa/psci.S >> @@ -36,9 +36,7 @@ psci_cpu_on: >> and r1, r1, #0xff >> >> mov r0, r1 >> - bl psci_get_cpu_stack_top >> - str r2, [r0] >> - dsb >> + bl psci_save_target_pc >> >> @ Get DCFG base address >> movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) >> diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S >> index 34c6ab3..cb39f27 100644 >> --- a/arch/arm/cpu/armv7/mx7/psci.S >> +++ b/arch/arm/cpu/armv7/mx7/psci.S >> @@ -30,9 +30,7 @@ psci_cpu_on: >> push {lr} >> >> mov r0, r1 >> - bl psci_get_cpu_stack_top >> - str r2, [r0] >> - dsb >> + bl psci_save_target_pc >> >> ldr r2, =psci_cpu_entry >> bl imx_cpu_on >> diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index >> 2425f6a..0e0f98e 100644 >> --- a/arch/arm/cpu/armv7/psci.S >> +++ b/arch/arm/cpu/armv7/psci.S >> @@ -20,6 +20,8 @@ >> #include <asm/macro.h> >> #include <asm/psci.h> >> >> +#define SAVE_SPACE_TARGET_PC_OFFSET 0x0 >> + >> .pushsection ._secure.text, "ax" >> >> .arch_extension sec >> @@ -196,27 +198,58 @@ ENDPROC(psci_cpu_off_common) >> >> @ expects CPU ID in r0 and returns stack top in r0 >> ENTRY(psci_get_cpu_stack_top) >> - mov r5, #0x400 @ 1kB of stack per CPU >> - mul r0, r0, r5 >> - >> + @ Align psci_text_end minumum page size. Even if page is greater than >> + @ 4K, we still can ensure that data is always safe access by the CPU. >> ldr r5, =psci_text_end @ end of monitor text >> - add r5, r5, #0x2000 @ Skip two pages >> - lsr r5, r5, #12 @ Align to start of page >> + @ Detect page border >> + lsl r4, r5, #20 > Why do you shift it 20 bits? I guess you wanted to shift 12 bits instead. Shift left 20bits will get the low of 12bits that is page border. if the 12 bits of value is 0, this means that we stand in the page border. And not need to do align page. >> + cmp r4, #0 >> + beq out_psci_stack_align >> + add r5, r5, #PSCI_STACK_ALIGN_SIZE >> + lsr r5, r5, #12 >> lsl r5, r5, #12 >> - sub r5, r5, #4 @ reserve 1 word for target PC >> - sub r0, r5, r0 @ here's our stack! >> + >> +out_psci_stack_align: >> + mov r4, #PSCI_PERCPU_STACK_SIZE >> + add r0, r0, #1 >> + mul r0, r0, r4 >> + add r0, r0, r5 >> >> bx lr >> ENDPROC(psci_get_cpu_stack_top) >> >> +@ Save space in percpu stack tail. >> +@ expects CPU ID in r0 and returns save space address in r0. >> +ENTRY(psci_get_cpu_save_space) > It is better to use term "reserve" here instead of "save" s/save/reserve/, thanks. >> + mov r10, lr >> + >> + bl psci_get_cpu_stack_top >> + sub r0, r0, #PSCI_PERCPU_STACK_SIZE > (r0 - PSCI_PERCPU_STACK_SIZE ) is stack top of next CPU's stack. > (r0 - PSCI_PERCPU_STACK_SIZE +1 ) is the stack tail you want, right? Yes, :) Regards, -Dongsheng

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[U-Boot] [PATCH 0/9] ARM: ARMv7: PSCI: add PSCI v1.0 support
by Dongsheng Wang 16 Mar '16

16 Mar '16

From: Wang Dongsheng <dongsheng.wang(a)nxp.com> Support PSCI v1.0 for u-boot. Wang Dongsheng (9): ARM: PSCI: Change function ID base value ARM: PSCI: Change PSCI related macro definition style ARM: ARMv7: PSCI: move target PC in each CPU stack no longer is shared ARM: ARMv7: PSCI: Factor out reusable psci_cpu_on_common ARM: ARMv7: PSCI: Pass contextID to target CPU ARM: ARMv7: PSCI: ls102xa: Verify CPU ID for CPU_ON ARM: ARMv7: PSCI: Add PSCI 1.0 version support ARM: ARMv7: PSCI: ls102xa: add psci functions implemention ARM: ARMv7: PSCI: ls102xa: put secure text section into OCRAM arch/arm/cpu/armv7/ls102xa/psci.S | 155 +++++++++++++++++++++++---- arch/arm/cpu/armv7/mx7/psci.S | 5 - arch/arm/cpu/armv7/nonsec_virt.S | 4 + arch/arm/cpu/armv7/psci.S | 162 ++++++++++++++++++++++++++--- arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 11 +- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 11 +- arch/arm/cpu/armv7/virt-dt.c | 48 ++++++--- arch/arm/include/asm/arch-ls102xa/config.h | 3 +- arch/arm/include/asm/psci.h | 62 ++++++++--- arch/arm/mach-tegra/psci.S | 11 +- board/freescale/ls1021aqds/Makefile | 1 + board/freescale/ls1021aqds/psci.S | 36 +++++++ board/freescale/ls1021atwr/Makefile | 1 + board/freescale/ls1021atwr/psci.S | 28 +++++ include/configs/ls1021aqds.h | 3 + include/configs/ls1021atwr.h | 2 + 16 files changed, 451 insertions(+), 92 deletions(-) create mode 100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S -- 2.1.0.27.g96db324

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