March 2016 - U-Boot

[U-Boot] [PATCH] armv8: lsch3: Enable WUO config for RNI-20 node
by Prabhakar Kushwaha 22 Mar '16

22 Mar '16

Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 8 ++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++ arch/arm/lib/ccn504.S | 21 +++++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 41e1704..9c69ed1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -18,6 +18,14 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ #ifdef CONFIG_FSL_LSCH3 + + /* Set Wuo bit for RN-I 20 */ +#if defined(CONFIG_LS2085A) || defined (CONFIG_LS2080A) + ldr x0, =CCI_AUX_CONTROL_BASE(20) + ldr x1, =0x00000010 + bl ccn504_set_aux +#endif + /* Add fully-coherent masters to DVM domain */ ldr x0, =CCI_MN_BASE ldr x1, =CCI_MN_RNF_NODEID_LIST diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 49b113d..f5a8595 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -91,6 +91,8 @@ #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) +#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) + /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 #define TZPCR0SIZE_BASE (TZPC_BASE) diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S index 7570c7b..1e07876 100644 --- a/arch/arm/lib/ccn504.S +++ b/arch/arm/lib/ccn504.S @@ -59,3 +59,24 @@ ENTRY(ccn504_set_qos) ret ENDPROC(ccn504_set_qos) +/************************************************************************* + * + * void ccn504_set_aux(CCI_AUX_CONTROL_BASE, Value); + * + * Initialize AUX control settings + * + *************************************************************************/ +ENTRY(ccn504_set_aux) + /* + * x0: CCI_AUX_CONTROL_BASE + * x1: Value + */ + + ldr x9, [x0] + mov x10, x1 + orr x9, x9, x10 + str x9, [x0] + + ret +ENDPROC(ccn504_set_aux) + -- 1.9.1

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[U-Boot] Please pull u-boot-ppc4xx/master
by Stefan Roese 22 Mar '16

22 Mar '16

Hi Tom, even though its not ppc4xx, I took Dirk's mpc83xx patches via this git repository get upstream. I hope this is okay for you. So here we go: The following changes since commit 83d95b67d3731e39292d858924ade3be68c167af: Merge branch 'master' of git://git.denx.de/u-boot-socfpga (2016-03-20 18:09:34 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git for you to fetch changes up to a119357c43a4d4bd0e488a701255bcfea8f8bf6c: strider: use optimised bus timing for FPGA access (2016-03-21 09:20:37 +0100) ---------------------------------------------------------------- Dirk Eibach (2): strider: Add DP501 support for cpu model strider: Define pca593x widths Reinhard Pfau (1): strider: use optimised bus timing for FPGA access board/gdsys/common/dp501.c | 31 +++++++++++++++++++++++++++++++ board/gdsys/common/dp501.h | 1 + board/gdsys/common/osd.c | 22 +--------------------- board/gdsys/mpc8308/strider.c | 31 ++++++++++++++++++++++++++----- include/configs/strider.h | 16 ++++++++++------ 5 files changed, 69 insertions(+), 32 deletions(-)

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[U-Boot] [PATCH] arm: socfpga: migration of CONFIG_SPI_FLASH_BAR
by Bakhvalov, Denis (Nokia - PL/Wroclaw) 22 Mar '16

22 Mar '16

CONFIG_SPI_FLASH_BAR was deleted from socfpga_common.h and placed in socfpga_*_defconfig where it makes sense. Signed-off-by: Denis Bakhvalov <denis.bakhvalov(a)nokia.com> Reported-by: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + include/configs/socfpga_common.h | 2 -- 8 files changed, 7 insertions(+), 2 deletions(-) diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 7b60d95..505a68d 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 6a487f4..df19a95 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index cfcae5d..5e18844 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -18,6 +18,7 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y +CONFIG_SPI_FLASH_BAR=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index b6f6a65..8a76aa1 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -19,5 +19,6 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_SPI_FLASH_BAR=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index f45c3ed..36bb1e1 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -19,6 +19,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index e25d09b..0aaef76 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -22,6 +22,7 @@ CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y +CONFIG_SPI_FLASH_BAR=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index d499a14..83eada3 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -17,6 +17,7 @@ CONFIG_DM_MMC=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_BAR=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 56d32e6..2ad0287 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -93,7 +93,6 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH_BAR /* * The base address is configurable in QSys, each board must specify the * base address based on it's particular FPGA configuration. Please note @@ -219,7 +218,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH_BAR /* * Designware SPI support -- 2.7.0

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[U-Boot] Problem with attaching UBI partition
by Bakhvalov, Denis (Nokia - PL/Wroclaw) 22 Mar '16

22 Mar '16

Dear U-Boot support, I have problems while running following commands in U-Boot: U-Boot => sf probe 0 0 0 SF: Detected S25FL512S with page size 512, total: 67108864 U-Boot => mtdparts device nor0 <snor0>, # parts = 4 #: name size offset mask_flags 0: boot 0x00100000 0x00000000 0 1: bootenv 0x00080000 0x00100000 0 2: SomeInfo 0x01980000 0x00180000 0 3: ubifspart 0x02500000 0x01b00000 0 U-Boot => ubi part ubifspart mtd: Giving out device 1 to mtd=3 ubi0: attaching mtd1 UBI DBG gen (pid 1): sizeof(struct ubi_ainf_peb) 48 UBI DBG gen (pid 1): sizeof(struct ubi_wl_entry) 20 UBI DBG gen (pid 1): min_io_size 1 UBI DBG gen (pid 1): max_write_size 512 UBI DBG gen (pid 1): hdrs_min_io_size 1 UBI DBG gen (pid 1): ec_hdr_alsize 64 UBI DBG gen (pid 1): vid_hdr_alsize 64 UBI DBG gen (pid 1): vid_hdr_offset 64 UBI DBG gen (pid 1): vid_hdr_aloffset 64 UBI DBG gen (pid 1): vid_hdr_shift 0 UBI DBG gen (pid 1): leb_start 128 UBI DBG gen (pid 1): max_erroneous 16 UBI DBG gen (pid 1): process PEB 0 UBI DBG bld (pid 1): scan PEB 0 UBI DBG io (pid 1): read EC header from PEB 0 UBI DBG io (pid 1): read 64 bytes from PEB 0:0 ubi0 warning: ubi_io_read_ec_hdr: bad magic number at PEB 0: ff554249 instead of 55424923 Erase counter header dump: magic 0xff554249 version 35 ec 0 vid_hdr_offset 16777216 data_offset 1073741824 image_seq -2142856561 hdr_crc 0xe046ed erase counter header hexdump: UBI DBG bld (pid 1): bad magic number at PEB 0: ff554249 instead of 55424923 UBI DBG io (pid 1): read VID header from PEB 0 UBI DBG io (pid 1): read 64 bytes from PEB 0:64 UBI DBG bld (pid 1): no VID header found at PEB 0, only 0xFF bytes UBI DBG bld (pid 1): add to erase: PEB 0, EC -1 ... // this warning goes for all PEBs from 1 to 147 ubi0: scanning is finished UBI DBG gen (pid 1): max. sequence number: 0 ubi0 error: ubi_read_volume_table: the layout volume was not found ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22 UBI error: cannot attach mtd1 UBI error: cannot initialize UBI, error -22 UBI init error 22 UBI init error 22 For me it looks like this magic number is shifted one byte right, although I can't understand why. Here is how I create UBI partition in Linux env: Linux Env #> mtdinfo -a mtd5 Name: data Type: nor Eraseblock size: 262144 bytes, 256.0 KiB Amount of eraseblocks: 148 (38797312 bytes, 37.0 MiB) Minimum input/output unit size: 1 byte Sub-page size: 1 byte Character device major/minor: 90:10 Bad blocks are allowed: false Device is writable: true Linux Env #> ubiformat /dev/mtd5 ubiformat: mtd5 (nor), size 38797312 bytes (37.0 MiB), 148 eraseblocks of 262144 bytes (256.0 KiB), min. I/O size 1 bytes libscan: scanning eraseblock 147 -- 100 % complete ubiformat: 148 eraseblocks are supposedly empty ubiformat: formatting eraseblock 147 -- 100 % complete 797312 Linux Env #> ubiattach -m 5 /dev/ubi_ctrl UBI: attaching mtd5 to ubi0 UBI: scanning is finished UBI: attached mtd5 (name "part5", size 37 MiB) to ubi0 UBI: PEB size: 262144 bytes (256 KiB), LEB size: 262016 bytes UBI: min./max. I/O unit sizes: 1/256, sub-page size 1 UBI: VID header offset: 64 (aligned 64), data offset: 128 UBI: good PEBs: 148, bad PEBs: 0, corrupted PEBs: 0 UBI: user volume: 0, internal volumes: 1, max. volumes count: 128 UBI: max/mean erase counter: 2/1, WL threshold: 4096, image sequence number: 1371523162 UBI: available PEBs: 144, total reserved PEBs: 4, PEBs reserved for bad PEB handling: 0 UBI: background thread "ubi_bgt0d" started, PID 1003 Linux Env #> ubimkvol -N data -m /dev/ubi0 Linux Env #> mount -t ubifs ubi0:data /mnt Linux Env #> mount -t ubifs ubi0:data /mnt UBIFS: default file-system created UBIFS: background thread "ubifs_bgt0_0" started, PID 1010 UBIFS: mounted UBI device 0, volume 0, name "data" UBIFS: LEB size: 262016 bytes (255 KiB), min./max. I/O unit sizes: 8 bytes/256 bytes UBIFS: FS size: 35110144 bytes (33 MiB, 134 LEBs), journal size 2096129 bytes (1 MiB, 7 LEBs) UBIFS: reserved for root: 1658338 bytes (1619 KiB) UBIFS: media format: w4/r0 (latest is w4/r0), UUID 696FFD7B-1957-4ABD-9FDC-ED0EEB674D9D, small LPT model It's perfectly working from Linux env, however U-Boot don't want to attach UBI partition. Please help me identify the problem! Best regards, Denis Bakhvalov

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[U-Boot] [RFC] ARMv7: Build cache_v7.c with -O1 to avoid gcc6 breakage
by Hans de Goede 22 Mar '16

22 Mar '16

Hi All, Here is a workaround for a problem I've been debugging today, for details see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788 We're still investigating what the real problem is in the mean time I wanted to share this workaround in case others are hitting the same problem. Regards, Hans

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Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2
by Michael Haas 22 Mar '16

22 Mar '16

On 03/21/2016 04:47 PM, Karsten Merker wrote: >>>> Are any other sunxi boards impacted by the same problem that you know ? >>> No, I don't know of any other boards, but I have not looked very hard :) > At least the Olimex A20-SOM-EVB (which uses the same RTL8211CL > PHY) has the same issue and forcing master mode helps there as > well. With the above change added on top of v2016.01, I can > successfully boot via tftp on a gigabit link on both the Lime2 > and the A20-SOM-EVB, which was impossible before. Great news! > > Some quick iperf measurements on the A20-SOM-EVB with the patch > applied show network throughput comparable to what I get with > other A20-based systems. > > All my other A20-based boards - which don't have problems on > gigabit links - use an RTL8211E instead of the RTL8211CL. I had > been looking into the source of the gigabit problems on the > A20-SOM-EVB for a while already and talked with Olimex about > them. Olimex has also been trying to debug the issue and told me > that the problem doesn't seem to occur on all boards, and that > during their tests different RTL8211CL chips (i.e. same chip > model, but with different production date codes) behaved > differently. This would fit into the hypothesis that there might > be some kind of erratum in at least some series of the RTL8211CL. > > So, Olimex knows about these issues? :/ Perhaps you can CC your contact there once we have a final patch. By the way, I just searched the web for "rtl8211c master mode" and found this [0]: ---%-- // The EVK board with RTL8211C requires this sequence per information // Realtek. // 1. Register 0x1F, write 0005 -> Page 5 // 2. Register 0x0C, write 0000 // 3. Register 0x01, change bit [7] to 1 // 4. Register 0x1F, write 0000 -> Page 0 // However, please note that it is not recommended to use the RTL8211CL 125MHz clock output because // it is not stable when link at Slave mode. If you need the clock output, // please consider using RTL8211E instead. // 5. Force manual "master" mode in auto-negotiation. #if defined(CONFIG_DIGICOLOR_MAINBOARD_THUNDERBOLT_REV1) if (!RTL8211C_hack) { // Enable 125 Mhz clock output gmac_mdio_write(ei, phy_id, 0x1f, 5); gmac_mdio_write(ei, phy_id, 0x0c, 0); gmac_mdio_read (ei, phy_id, 0x01, &data); data |= 0x80; gmac_mdio_write(ei, phy_id, 0x01, data); gmac_mdio_write(ei, phy_id, 0x1f, 0); // Set Manual MASTER Mode gmac_mdio_read (ei, phy_id, 0x09, &data); data |= 0x1800; gmac_mdio_write(ei, phy_id, 0x09, data); // Restart Autonegotiation gmac_mdio_read (ei, phy_id, 0x00, &data); data |= 0x0200; gmac_mdio_write(ei, phy_id, 0x00, data); // All done now. RTL8211C_hack = 1; } #endif %--- I guess we are not the first to find this out the hard way. If the issue is related to an internal clock of the RTL8211C, is there perhaps an external clock we can use? [0] http://mydc-proj.googlecode.com/svn/trunk/linux/target/u-boot/2010.09-cnxt/…

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[U-Boot] U-boot on Raspberry pi B+ does not display on HDMI monitor
by zbvs 22 Mar '16

22 Mar '16

Hi, i'm trying to load u-boot on RPI B+ , by using tools that described in the below page http://elinux.org/RPi_U-Boot As indicated in the page, i used Stephen Warren's git. sequence of command that i put is : export CROSS_COMPILE=$HOME/rpi-tools/arm-bcm2708/arm-bcm2708hardfp-linux-gnueabi/bin/arm-bcm2708hardfp-linux-gnueabi- make distclean make rpi_config make u-boot.bin After this, i just copy u-boot.bin to SD-Card by using rufus in windows RPI doesn't shutdown after power on, but does not show anything on HDMI monitor what is the problem is my progress? -- View this message in context: http://u-boot.10912.n7.nabble.com/U-boot-on-Raspberry-pi-B-does-not-display… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] powerpc/mpc85xx: Alignment issue when adding code to start.S
by Mario Six 22 Mar '16

22 Mar '16

Hi, I've been implementing pre-relocation malloc for MPC58xx to enable CONFIG_DM on our P1022 board (controlcenterd). The patch so far looks like this: " diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 235a635..e6e1688 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -82,7 +82,6 @@ void setup_ifc(void) void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; - int i; #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif @@ -95,13 +94,6 @@ void cpu_init_early_f(void *fdt) /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); - /* - * Clear initial global data - * we don't use memset so we can share this code with NAND_SPL - */ - for (i = 0; i < sizeof(gd_t); i++) - ((char *)gd)[i] = 0; - #ifdef CONFIG_QEMU_E500 /* * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index d867e2a..faf2804 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1152,6 +1152,29 @@ _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ + +#ifdef CONFIG_SYS_MALLOC_F_LEN + /* Leave 16+ byte for back chain termination and NULL return address */ + subi r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf) + + /* End of RAM */ + lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l + + li r0,0 + +1: subi r4,r4,4 + stw r0,0(r4) + cmplw r4,r3 + bne 1b + + lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h + ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l + + addi r3,r3,16 /* Pre-relocation malloc area */ + stw r3,GD_MALLOC_BASE(r4) + subi r3,r3,16 +#endif li r0,0 stw r0,0(r3) /* Terminate Back Chain */ stw r0,+4(r3) /* NULL return address. */ -- 1.8.3 " While tweaking the code, I found out that the board sometimes crashed and sometimes did not crash. As it turns out, the code I added had to have a specific length to work (the version above does not work, for example; but some additional nops are enough to make it work). I suspected an alignment issue somewhere below the function and traced it to the exception handlers that are defined there. Specifically, the timer_interrupt exception, since the following patch fixes the issue: " diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index faf2804..d87c034 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1240,6 +1240,7 @@ ProgramCheck: */ STD_EXCEPTION(0x0800, FPUnavailable, UnknownException) STD_EXCEPTION(0x0900, SystemCall, UnknownException) + . = 0x0a00 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt) STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException) STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException) -- 1.8.3 " Next, I ran a bisect (since the patch worked on v2015.01 without problems) and identified the commit 96d2bb952bbf2e5a14f6ad668312cbce3cc4485a (powerpc/mpc85xx: Don't relocate exception vectors) as the cause. Indeed, this commit removes the explicit alignment of the exceptions. Possibly, some explicit alignment is needed after all? Best regards, Mario

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[U-Boot] Problems with D-cache invalidation in Freescale eSDHC driver
by mario.six＠gdsys.cc 22 Mar '16

22 Mar '16

Hello, I've been working on a QorIQ P1022 board (controlcenterd) to run the newest U-Boot on it, and I encountered some strange behavior. During boot, we get these error messages " ERROR: Cannot import environment: errno = 12 at common/env_common.c:221/env_import() *** Warning - import failed, using default environment ERROR: Environment import failed: errno = 12 at common/env_common.c:123/set_default_env() ## Can't malloc 9 bytes " After bisecting, I found out that the commit 4683b22 (mmc:fsl_esdhc invalidate dcache before read) apparently causes this. With the additional d-cache invalidations in place, malloc and free calls fail. Now, after some experimenting, I found out that deactivating the d-cache invalidation when reading the first sector is enough; that is, if one replaces the first invalidation " if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); " with " if (data->flags & MMC_DATA_READ && (cmd->cmdidx != MMC_CMD_READ_SINGLE_BLOCK || cmd->cmdarg != 0)) check_and_invalidate_dcache_range(cmd, data); " in fsl_esdhc.c, it seems to work, but I have no idea why that is the case. Any ideas would be greatly appreciated. Best regards, Mario

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[U-Boot] [RFC PATCH 0/1] net: phy: Force master mode for RTL8211C
by Michael Haas 22 Mar '16

22 Mar '16

This patch is an RFC based on recent discussions. It's only lightly tested. I have yet to verify that the registers are being set correctly. I'm sending it out now because I have to leave for today. Note that this patch requires Karsten Merkers '[PATCH] net: phy: Realtek RTL8211B/C PHY ID fix'. Series-Version: 2 Series-changes: 2 - Removed accidental inclusion of Karsten's patch in my first submission of this series. - Fix a typo in the code: 6 -> & Michael Michael Haas (1): net: phy: Force master mode for RTL8211C drivers/net/phy/realtek.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.7.2

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