March 2016 - U-Boot

[U-Boot] [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()
by Yuanzheng Li 22 Mar '16

22 Mar '16

The TBI_ANA register is configurated with the wrong value 0x4001, refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual. It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian, which should be cleared. But the normal functions of the auto-negotiation, e.g. Pause and Full Duplex, do not be set. There is no problem in the p2041rdb board, because the ppc is connected directly with the phy chip which support auto-negotiation by default in SGMII interface. But the link problem will occur when it is connected with a switch chip like BCM5389, the switch chip disable auto-negotiation by default, and the ppc also disable auto-negotiation, then there is no link between them. So use the vlue TBIANA_SETTINGS to enable the ppc's auto-negotiation. Signed-off-by: Yuanzheng Li <liyuanzheng01(a)163.com> Cc: York Sun <yorksun(a)freescale.com> --- drivers/net/fm/eth.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index eb8e936..78c0988 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -81,7 +81,7 @@ qsgmii_loop: tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON, TBICON_CLK_SELECT); tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA, - TBIANA_SGMII_ACK); + TBIANA_SETTINGS); tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_CR, TBICR_SETTINGS); #endif -- 1.7.8

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[U-Boot] [PATCH] arm64: Fix layerscape mmu setup
by Alexander Graf 22 Mar '16

22 Mar '16

With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun(a)nxp.com> CC: Alison Wang <alison.wang(a)nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Alexander Graf <agraf(a)suse.de> --- arch/arm/cpu/armv8/cache_v8.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index d1bd06b..1615542 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -320,7 +320,7 @@ static int count_required_pts(u64 addr, int level, u64 maxaddr) } /* Returns the estimated required size of all page tables */ -u64 get_page_table_size(void) +__weak u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); u64 size = 0; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 7404bd9..4b9e209 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -410,6 +410,11 @@ static inline void final_mmu_setup(void) */ } +u64 get_page_table_size(void) +{ + return 0x10000; +} + int arch_cpu_init(void) { icache_enable(); -- 1.8.5.6

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[U-Boot] [PATCH][v2] driver: net: fsl-mc: Return from DPAA_exit if boot_status !=0
by Prabhakar Kushwaha 22 Mar '16

22 Mar '16

Return value of get_mc_boot_status() in case of failure is not necessary to be -1. So update the error condition check. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Reported-by: Yao Yuan <yao.yuan(a)nxp.com> --- Changes for v2: Incorporated York's comments - Added comments drivers/net/fsl-mc/mc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 53c4966..f83bd0c 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1147,7 +1147,8 @@ int fsl_mc_ldpaa_exit(bd_t *bd) { int err = 0; - if (bd && get_mc_boot_status() == -1) + /* MC is not loaded intentionally, So return success. */ + if (bd && get_mc_boot_status() != 0) return 0; if (bd && !get_mc_boot_status() && get_dpl_apply_status() == -1) { -- 1.9.1

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[U-Boot] [PATCH v2 1/3] freescale: vid: Return i2c mux to default channel
by Wenbin Song 22 Mar '16

22 Mar '16

IR chip is on one of the channels on multiplexed I2C-bus. Reset to default channel after accessing. Signed-off-by: Wenbin Song <wenbin.song(a)nxp.com> --- Changes for v2: -Rework the commit message and the tag int the subject. --- board/freescale/common/vid.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 1bd65a8..a6a132a 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -454,6 +454,9 @@ int adjust_vdd(ulong vdd_override) exit: if (re_enable) enable_interrupts(); + + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + return ret; } @@ -469,7 +472,7 @@ static int print_vdd(void) ret = find_ir_chip_on_i2c(); if (ret < 0) { printf("VID: Could not find voltage regulator on I2C.\n"); - return -1; + goto exit; } else { i2caddress = ret; debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); @@ -481,11 +484,14 @@ static int print_vdd(void) vdd_last = read_voltage(i2caddress); if (vdd_last < 0) { printf("VID: Couldn't read sensor abort VID adjustment\n"); - return -1; + goto exit; } printf("VID: Core voltage is at %d mV\n", vdd_last); +exit: + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + + return ret < 0 ? -1 : 0; - return 0; } static int do_vdd_override(cmd_tbl_t *cmdtp, -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] ARM: tegra210: set PLLE_PTS bit when enabling PLLE
by Stephen Warren 22 Mar '16

22 Mar '16

From: Stephen Warren <swarren(a)nvidia.com> This bit needs to be set for system suspend/resume to work. This setting will be documented in an updated TRM at some time in the future. Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- arch/arm/mach-tegra/tegra210/clock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index df92bdce889e..f0052e7934a1 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1104,6 +1104,7 @@ static int tegra_pllref_enable(void) #define PLLE_MISC_IDDQ_SWCTL (1 << 14) #define PLLE_MISC_IDDQ_OVERRIDE_VALUE (1 << 13) #define PLLE_MISC_LOCK (1 << 11) +#define PLLE_PTS (1 << 8) #define PLLE_MISC_KCP(x) (((x) & 0x3) << 6) #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2) #define PLLE_MISC_KVCO (1 << 0) @@ -1157,6 +1158,7 @@ int tegra_plle_enable(void) writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE); value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC); + value |= PLLE_PTS; value &= ~PLLE_MISC_KCP(3); value &= ~PLLE_MISC_VREG_CTRL(3); value &= ~PLLE_MISC_KVCO; -- 2.7.4

1 0

[U-Boot] [PATCH] arm: ls102xa: Enable CONFIG_SYS_CONSOLE_IS_IN_ENV support
by Alison Wang 22 Mar '16

22 Mar '16

CONFIG_SYS_CONSOLE_IS_IN_ENV needs to be enabled, so we could set stdout environment variable to specify the vga for the console output when LCD/HDMI is connected to the boards. Signed-off-by: Alison Wang <alison.wang(a)nxp.com> --- include/configs/ls1021aqds.h | 1 + include/configs/ls1021atwr.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ff5ca22..2b06816 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -470,6 +470,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_FSL_DIU_CH7301 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 166061d..7dccb39 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -338,6 +338,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_FSL_DCU_SII9022A #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8/fsl-lsch2: fix sdhc clock frequency value
by Yangbo Lu 22 Mar '16

22 Mar '16

The eSDHC could select to use platform clock or peripheral clock to generate SD clock. The default selection is platform clock. So, fix the clock frequency value that's calculated for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 6f6a588..453a93d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -106,9 +106,13 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 #ifdef CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK rcw_tmp = in_be32(&gur->rcwsr[15]); rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT; sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp; +#else + sys_info->freq_sdhc = sys_info->freq_systembus; +#endif #endif #if defined(CONFIG_FSL_IFC) -- 2.1.0.27.g96db324

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[U-Boot] [PATCH 2/2][v2] armv8: ls2085a: Remove phy configuration from QDS and RDB
by Prabhakar Kushwaha 22 Mar '16

22 Mar '16

From: Prabhakar Kushwaha <prabhakar(a)freescale.com> As phy_connect and phy_config are being called from DPAA2 driver. Remove calling of mentioned function from board file. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Sending as it is board/freescale/ls2080aqds/eth.c | 25 ------------------- board/freescale/ls2080ardb/eth_ls2080rdb.c | 39 ------------------------------ 2 files changed, 64 deletions(-) diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 42ff743..33ad7dc 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -548,12 +548,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 2: /* Slot housing a SGMII riser card? */ @@ -562,12 +556,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT2; bus = mii_dev_for_muxval(EMI1_SLOT2); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 3: break; @@ -606,12 +594,6 @@ serdes2: dpmac_info[dpmac_id].board_mux = EMI1_SLOT4; bus = mii_dev_for_muxval(EMI1_SLOT4); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 5: break; @@ -679,13 +661,6 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - - phy_config(dpmac_info[dpmac_id].phydev); break; case 3: break; diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index db50e4e..58ea746 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -20,42 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; -int load_firmware_cortina(struct phy_device *phy_dev) -{ - if (phy_dev->drv->config) - return phy_dev->drv->config(phy_dev); - - return 0; -} - -void load_phy_firmware(void) -{ - int i; - u8 phy_addr; - struct phy_device *phy_dev; - struct mii_dev *dev; - phy_interface_t interface; - - /*Initialize and upload firmware for all the PHYs*/ - for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) { - interface = wriop_get_enet_if(i); - if (interface == PHY_INTERFACE_MODE_XGMII) { - dev = wriop_get_mdio(i); - phy_addr = wriop_get_phy_address(i); - phy_dev = phy_find_by_mask(dev, 1 << phy_addr, - interface); - if (!phy_dev) { - printf("No phydev for phyaddr %d\n", phy_addr); - continue; - } - - /*Flash firmware for All CS4340 PHYS */ - if (phy_dev->phy_id == PHY_UID_CS4340) - load_firmware_cortina(phy_dev); - } - } -} - int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) @@ -125,9 +89,6 @@ int board_eth_init(bd_t *bis) } } - /* Load CORTINA CS4340 PHY firmware */ - load_phy_firmware(); - cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ -- 1.9.1

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[U-Boot] [PATCH 1/2][v2] driver: net: ldpaa_eth: Add support of PHY framework
by Prabhakar Kushwaha 22 Mar '16

22 Mar '16

This patch integrate DPAA2 ethernet driver existing PHY framework. Call phy_connect and phy_config as per available DPMAC id defined in SerDes Protcol. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> --- Changes for v2: Incorporated Joe Hershberger's comments drivers/net/ldpaa_eth/ldpaa_eth.c | 121 +++++++++++++++++++++++++++----------- 1 file changed, 87 insertions(+), 34 deletions(-) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 7f96883..8a00bc3 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -14,15 +14,32 @@ #include <linux/compat.h> #include <fsl-mc/fsl_dpmac.h> +#include <fsl-mc/ldpaa_wriop.h> #include "ldpaa_eth.h" -#undef CONFIG_PHYLIB +#ifdef CONFIG_PHYLIB static int init_phy(struct eth_device *dev) { - /*TODO for external PHY */ + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv; + struct phy_device *phydev = NULL; + struct mii_dev *bus; - return 0; + bus = wriop_get_mdio(priv->dpmac_id); + if (bus == NULL) + return 0; + + phydev = phy_connect(bus, wriop_get_phy_address(priv->dpmac_id), + dev, wriop_get_enet_if(priv->dpmac_id)); + if (!phydev) { + printf("Failed to connect\n"); + return -1; + } + + priv->phydev = phydev; + + return phy_config(phydev); } +#endif #ifdef DEBUG static void ldpaa_eth_get_dpni_counter(void) @@ -380,7 +397,9 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) #ifdef DEBUG struct dpni_link_state link_state; #endif - int err; + int err = 0; + struct mii_dev *bus; + phy_interface_t enet_if; if (net_dev->state == ETH_STATE_ACTIVE) return 0; @@ -394,11 +413,48 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) printf("ERROR (DPL is deployed. No device available)\n"); return -ENODEV; } + /* DPMAC initialization */ err = ldpaa_dpmac_setup(priv); if (err < 0) goto err_dpmac_setup; +#ifdef CONFIG_PHYLIB + if (priv->phydev) + err = phy_startup(priv->phydev); + if (err) { + printf("%s: Could not initialize\n", + priv->phydev->dev->name); + goto err_dpamc_bind; + } +#else + priv->phydev = (struct phy_device *)malloc(sizeof(struct phy_device)); + memset(priv->phydev, 0, sizeof(struct phy_device)); + + priv->phydev->speed = SPEED_1000; + priv->phydev->link = 1; + priv->phydev->duplex = DUPLEX_FULL; +#endif + + bus = wriop_get_mdio(priv->dpmac_id); + enet_if = wriop_get_enet_if(priv->dpmac_id); + if ((bus == NULL) && + (enet_if == PHY_INTERFACE_MODE_XGMII)) { + priv->phydev = (struct phy_device *) + malloc(sizeof(struct phy_device)); + memset(priv->phydev, 0, sizeof(struct phy_device)); + + priv->phydev->speed = SPEED_10000; + priv->phydev->link = 1; + priv->phydev->duplex = DUPLEX_FULL; + } + + if (!priv->phydev->link) { + printf("%s: No link.\n", priv->phydev->dev->name); + err = -1; + goto err_dpamc_bind; + } + /* DPMAC binding DPNI */ err = ldpaa_dpmac_bind(priv); if (err) @@ -425,28 +481,24 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) return err; } -#ifdef CONFIG_PHYLIB - /* TODO Check this path */ - err = phy_startup(priv->phydev); - if (err) { - printf("%s: Could not initialize\n", priv->phydev->dev->name); - return err; - } -#else - priv->phydev->speed = SPEED_1000; - priv->phydev->link = 1; - priv->phydev->duplex = DUPLEX_FULL; -#endif - err = dpni_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); if (err < 0) { printf("dpni_enable() failed\n"); return err; } - dpmac_link_state.rate = SPEED_1000; - dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG; - dpmac_link_state.up = 1; + dpmac_link_state.rate = priv->phydev->speed; + + if (priv->phydev->autoneg == AUTONEG_DISABLE) + dpmac_link_state.options &= ~DPMAC_LINK_OPT_AUTONEG; + else + dpmac_link_state.options |= DPMAC_LINK_OPT_AUTONEG; + + if (priv->phydev->duplex == DUPLEX_HALF) + dpmac_link_state.options |= DPMAC_LINK_OPT_HALF_DUPLEX; + + dpmac_link_state.up = priv->phydev->link; + err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle, &dpmac_link_state); if (err < 0) { @@ -484,10 +536,7 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) goto err_qdid; } - if (!priv->phydev->link) - printf("%s: No link.\n", priv->phydev->dev->name); - - return priv->phydev->link ? 0 : -1; + return priv->phydev->link; err_qdid: err_rx_flow: @@ -495,9 +544,10 @@ err_rx_flow: err_dpni_bind: ldpaa_dpbp_free(); err_dpbp_setup: -err_dpamc_bind: dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); err_dpni_setup: +err_dpamc_bind: + dpmac_destroy(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle); err_dpmac_setup: return err; } @@ -506,6 +556,9 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) { struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; int err = 0; +#ifdef CONFIG_PHYLIB + struct mii_dev *bus = wriop_get_mdio(priv->dpmac_id); +#endif if ((net_dev->state == ETH_STATE_PASSIVE) || (net_dev->state == ETH_STATE_INIT)) @@ -531,7 +584,10 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) printf("dpni_disable() failed\n"); #ifdef CONFIG_PHYLIB - phy_shutdown(priv->phydev); + if (priv->phydev && bus != NULL) + phy_shutdown(priv->phydev); + else + free(priv->phydev); #endif ldpaa_dpbp_free(); @@ -914,15 +970,12 @@ static int ldpaa_eth_netdev_init(struct eth_device *net_dev, net_dev->halt = ldpaa_eth_stop; net_dev->send = ldpaa_eth_tx; net_dev->recv = ldpaa_eth_pull_dequeue_rx; -/* - TODO: PHY MDIO information - priv->bus = info->bus; - priv->phyaddr = info->phy_addr; - priv->enet_if = info->enet_if; -*/ - if (init_phy(net_dev)) - return 0; +#ifdef CONFIG_PHYLIB + err = init_phy(net_dev); + if (err < 0) + return err; +#endif err = eth_register(net_dev); if (err < 0) { -- 1.9.1

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[U-Boot] [PATCH] [v3] armv8: fsl-layerscape: Updating entries in Serdes Table
by Pratiyush Mohan Srivastava 22 Mar '16

22 Mar '16

The serdes protocol entries in Serdes table 1 for protocol 0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45 and 0x47 are updated to reflect the entries in current Reference Manual. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)nxp.com> Reported-by: Jose Rivera <german.rivera(a)nxp.com> --- Changes for v3 Rebased to latest master Branch arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c index ea3114c..eaa44a7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c @@ -14,7 +14,7 @@ struct serdes_config { static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ - {0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, {0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } }, {0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2, SGMII1 } }, @@ -31,9 +31,9 @@ static struct serdes_config serdes1_cfg_tbl[] = { {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } }, {0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } }, {0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } }, - {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A, - QSGMII_B} }, - {0x35, {QSGMII_C, QSGMII_D, QSGMII_A, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, + {0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B, + QSGMII_A} }, + {0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } }, {} }; static struct serdes_config serdes2_cfg_tbl[] = { @@ -56,10 +56,10 @@ static struct serdes_config serdes2_cfg_tbl[] = { {0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, {0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, {0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } }, - {0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, - SGMII16 } }, - {0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, + {0x45, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x47, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15, + SGMII16 } }, {0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, SATA2 } }, {0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1, -- 1.9.1

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