March 2016 - U-Boot

[U-Boot] [PATCH] arm: socfpga: Handle phy-mode OF property for GMACs
by Marek Vasut 21 Mar '16

21 Mar '16

Thus far, the socfpga init code had hard-coded the configuration of the ethernet PHY interface to RGMII in the ethernet registers in sysmgr space, so PHYs connected in another modes did not work. This patch fixes support for configurations where the ethernet PHYs are connected over MII/GMII/RMII interfaces by parsing the phy-mode OF property of the GMACs and configuring the ethernet registers in sysmgr space accordingly. Signed-off-by: Marek Vasut <marex(a)denx.de> Reported-by: Denis Bakhvalov <denis.bakhvalov(a)nokia.com> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- arch/arm/mach-socfpga/misc.c | 39 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ce3ff0a..5f988e3 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -77,7 +77,8 @@ void v7_outer_cache_disable(void) * DesignWare Ethernet initialization */ #ifdef CONFIG_ETH_DESIGNWARE -static void dwmac_deassert_reset(const unsigned int of_reset_id) +static void dwmac_deassert_reset(const unsigned int of_reset_id, + const u32 phymode) { u32 physhift, reset; @@ -98,16 +99,41 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id) /* configure to PHY interface select choosed */ setbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); + phymode << physhift); /* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0); } +static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg) +{ + if (!phymode) + return -EINVAL; + + if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; + return 0; + } + + if (!strcmp(phymode, "rgmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; + return 0; + } + + if (!strcmp(phymode, "rmii")) { + *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII; + return 0; + } + + return -EINVAL; +} + static int socfpga_eth_reset(void) { const void *fdt = gd->fdt_blob; struct fdtdec_phandle_args args; + const char *phy_mode; + u32 phy_modereg; int nodes[2]; /* Max. two GMACs */ int ret, count; int i, node; @@ -132,7 +158,14 @@ static int socfpga_eth_reset(void) continue; } - dwmac_deassert_reset(args.args[0]); + phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL); + ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg); + if (ret) { + debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i); + continue; + } + + dwmac_deassert_reset(args.args[0], phy_modereg); } return 0; -- 2.7.0

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[U-Boot] Which entry in drivers/net/phy/realtek.c matches my device?
by Michael Haas 21 Mar '16

21 Mar '16

Hello all, I'd like to add some device-specific hacks to realtek.c. I'm using the Olimex A20-OlinuXino-Lime2 which uses the RTL8211CL PHY. Which of the various phy_driver structs is responsible for that device? I presume it's keyed off the .uid, but I'm not sure how to find the ID of the specific PHY used on my device. Thanks! Michael

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[U-Boot] [PATCH v6 00/76] mtd: Add SPI-NOR core support
by Jagan Teki 21 Mar '16

21 Mar '16

Compared to previous patch series this series adds spi-nor core with spi-nor controller drivers are of "mtd uclass" This is whole series for all spi-nor related changes, and while series tested on spansion spi-nor chip. Know issue: - arch/x86/lib/mrccache.c uses dm_spi_flash_ops, this need to fix. Why this framework: Some of the SPI device drivers at drivers/spi not a real spi controllers, Unlike normal/generic SPI controllers they operates only with SPI-NOR flash devices. these were technically termed as SPI-NOR controllers, Ex: drivers/spi/fsl_qspi.c The problem with these were resides at drivers/spi is entire SPI layer becomes SPI-NOR flash oriented which is absolutely a wrong indication where SPI layer getting effected more with flash operations - So this SPI-NOR core will resolve this issue by separating all SPI-NOR flash operations from spi layer and creats a generic layer called SPI-NOR core which can be used to interact SPI-NOR to SPI driver interface layer and the SPI-NOR controller driver. The idea is taken from Linux spi-nor framework. Before SPI-NOR: ----------------------- cmd/sf.c ----------------------- spi_flash.c ----------------------- sf_probe.c ----------------------- spi-uclass ----------------------- spi drivers ----------------------- SPI NOR chip ----------------------- After SPI-NOR: ------------------------------ cmd/sf.c ------------------------------ spi-nor.c ------------------------------- m25p80.c spi nor drivers ------------------------------- spi-uclass SPI NOR chip ------------------------------- spi drivers ------------------------------- SPI NOR chip ------------------------------- SPI-NOR with MTD: ------------------------------ cmd/sf.c ------------------------------ MTD core ------------------------------ spi-nor.c ------------------------------- m25p80.c spi nor drivers ------------------------------- spi-uclass SPI NOR chip ------------------------------- spi drivers ------------------------------- SPI NOR chip ------------------------------- drivers/mtd/spi-nor/spi-nor.c: spi-nor core drivers/mtd/spi-nor/m25p80.c: mtd uclass driver which is an interface layer b/w spi-nor core drivers/spi drivers/mtd/spi-nor/fsl_qspi.c: spi-nor controller driver(mtd uclass) Changes for v6: - Fixed git bisectable issues, with buildman. - Fixed spi-nor compilation issues - newly designed changes. Changes for v5: - newly designed changes Testing: $ git clone git://git.denx.de/u-boot-spi.git $ cd u-boot-spi $ git checkout -b spi-nor origin/spi-nor Jagan Teki (76): mtd: Add m25p80 driver mtd: Add Kconfig entry for MTD_M25P80 mtd: Add SPI-NOR core support doc: device-tree-bindings: jedec,spi-nor mtd: spi-nor: Add Kconfig entry for MTD_SPI_NOR mtd: spi-nor: Add kconfig for MTD_SPI_NOR_USE_4K_SECTORS mtd: spi-nor: Add MTD support mtd: spi-nor: Add spi_nor support in m25p80 mtd: spi-nor: Add dm spi-nor probing mtd: spi-nor: Add spi_flash_probe for mtd-dm-spi-nor mtd: spi-nor: Add spi_flash_free for mtd-dm-spi-nor mtd: spi-nor: m25p80: Add spi_nor support for non-dm sf: Rename erase_size to erasesize sf: Use erasesize instead of sector_size sf: Use uint64_t for flash->size spi_flash: Use mtd_info operation for SPI-NOR spi_flash: Use spi_flash_t instead of struct spi_flash mtd: spi-nor: Move spi_read_then_write to spi layer spi: Rename spi_read_then_write to spi_write_then_read mtd: spi-nor: Rename SPI_FLASH_BAR to SPI_NOR_BAR mtd: spi-nor: Add Kconfig entry for SPI_NOR_BAR mtd: spi-nor: Copy spl files from drivers/mtd/spi mtd: spi-nor: spl: Follow ascending order of include headers mtd: spi-nor: fsl_espi_spl: Use mtd_info mtd: spi-nor: spi_spl_load: Use mtd_info mtd: spi-nor: Add flash vendor Kconfig entries arm: zynq: Kconfig: Select MTD uclass arm: zynq: Kconfig: Drop DM_SPI_FLASH defconfigs: zynq_microzed: Drop CONFIG_SPI_FLASH defconfig: zynq_microzed: Enable CONFIG_MTD_M25P80 defconfig: zynq_microzed: Enable CONFIG_MTD_SPI_NOR spl: Add CONFIG_SPL_SPI_NOR_SUPPORT configs: zynq: Use CONFIG_SPL_SPI_NOR_SUPPORT configs: zynq: Use CONFIG_SPL_MTD_SUPPORT mtd: spi-nor: Copy sf_dataflash mtd: dataflash: Remove unneeded spi data mtd: dataflash: Move flash id detection into jedec_probe mtd: dataflash: Fix add_dataflash return logic mtd: dataflash: Add UCLASS_MTD support mtd: dataflash: Use spi_write_then_read mtd: dataflash: Drop sf_internal.h mtd: dataflash: Minor cleanups mtd: Rename sf_dataflash.c to mtd_dataflash.c mtd: spi-nor: Add Kconfig entry for mtd_dataflash mtd: dataflash: Add MTD_DATAFLASH_WRITE_VERIFY mtd: spi-nor: Add kconfig MTD_DATAFLASH_WRITE_VERIFY configs: ls1021aqds: Drop DM_SPI_FLASH and DATAFLASH defconfig: ls1021aqds_qspi: Enable SPI-NOR defconfig: ls1021aqds_qspi: Enable CONFIG_MTD_DATAFLASH mtd: spi-nor: Copy sandbox mtd: spi-nor: sandbox: Use spi-nor header mtd: spi-nor: Add SPI_NOR_SANBOX sandbox: kconfig: Drop DM_SPI_FLASH sandbox: kconfig: Select MTD uclass defconfigs: sandbox: Enable SPI-NOR mtd: sandbox: Use CONFIG_MTD_SPI_NOR defconfigs: sandbox: Enable SPI_NOR_SANDBOX spi_flash: Use spi_flash_t mtd: spi-nor: Add CONFIG_SPI_NOR_MISC config: Enable SPI-NOR framework spi-nor: Use CONFIG_MTD_SPI_NOR configs: Use CONFIG_MTD_SPI_NOR configs: Use CONFIG_SPI_NOR_BAR configs: spi-nor: Add new flash vendor configs configs: Use CONFIG_SPI_NOR_MISC spi: Drop mode_rx spi: Drop SPI_RX_FAST configs: Enable MTD uclass in missing configs configs: Drop CONFIG_SPI_FLASH_MTD uclass: Replace UCLASS_SPI_FLASH with UCLASS_MTD uclass: Drop UCLASS_SPI_FLASH configs: Use CONFIG_SPL_SPI_NOR_SUPPORT configs: Enable CONFIG_SPL_MTD_SUPPORT sf: Drop entire spi-flash framework MAINTAINERS: Add myself as SPI NOR maintainer configs: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS MAINTAINERS | 11 +- Makefile | 2 +- arch/Kconfig | 4 +- arch/arm/Kconfig | 10 +- arch/arm/mach-rockchip/Kconfig | 2 +- arch/arm/mach-rockchip/rk3288-board-spl.c | 2 +- arch/arm/mach-tegra/Kconfig | 2 +- arch/x86/lib/mrccache.c | 3 +- board/Arcturus/ucp1020/cmd_arc.c | 2 +- board/Synology/common/cmd_syno.c | 2 +- board/buffalo/lsxl/lsxl.c | 2 +- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 2 +- board/davinci/da8xxevm/da850evm.c | 4 +- board/davinci/ea20/ea20.c | 2 +- board/renesas/sh7752evb/sh7752evb.c | 4 +- board/renesas/sh7753evb/sh7753evb.c | 4 +- board/renesas/sh7757lcr/sh7757lcr.c | 6 +- board/siemens/taurus/taurus.c | 2 +- cmd/sf.c | 38 +- common/env_sf.c | 6 +- common/splash_source.c | 4 +- configs/B4420QDS_NAND_defconfig | 5 +- configs/B4420QDS_SPIFLASH_defconfig | 5 +- configs/B4420QDS_defconfig | 5 +- configs/B4860QDS_NAND_defconfig | 5 +- configs/B4860QDS_SECURE_BOOT_defconfig | 5 +- configs/B4860QDS_SPIFLASH_defconfig | 5 +- configs/B4860QDS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/B4860QDS_defconfig | 5 +- configs/BSC9131RDB_NAND_SYSCLK100_defconfig | 5 +- configs/BSC9131RDB_NAND_defconfig | 5 +- configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig | 5 +- configs/BSC9131RDB_SPIFLASH_defconfig | 5 +- configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig | 5 +- configs/BSC9132QDS_NAND_DDRCLK100_defconfig | 5 +- configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig | 5 +- configs/BSC9132QDS_NAND_DDRCLK133_defconfig | 5 +- configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig | 5 +- configs/BSC9132QDS_NOR_DDRCLK100_defconfig | 5 +- configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig | 5 +- configs/BSC9132QDS_NOR_DDRCLK133_defconfig | 5 +- .../BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig | 5 +- configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig | 5 +- .../BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig | 5 +- configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig | 5 +- .../BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig | 5 +- configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig | 5 +- .../BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig | 5 +- configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig | 5 +- configs/C29XPCIE_NAND_defconfig | 7 +- configs/C29XPCIE_NOR_SECBOOT_defconfig | 7 +- configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 7 +- configs/C29XPCIE_SPIFLASH_defconfig | 7 +- configs/C29XPCIE_defconfig | 7 +- configs/M52277EVB_defconfig | 5 +- configs/M52277EVB_stmicro_defconfig | 5 +- configs/M54418TWR_defconfig | 5 +- configs/M54418TWR_nand_mii_defconfig | 5 +- configs/M54418TWR_nand_rmii_defconfig | 5 +- configs/M54418TWR_nand_rmii_lowfreq_defconfig | 5 +- configs/M54418TWR_serial_mii_defconfig | 5 +- configs/M54418TWR_serial_rmii_defconfig | 5 +- configs/M54451EVB_defconfig | 5 +- configs/M54451EVB_stmicro_defconfig | 5 +- configs/M54455EVB_a66_defconfig | 5 +- configs/M54455EVB_defconfig | 5 +- configs/M54455EVB_i66_defconfig | 5 +- configs/M54455EVB_intel_defconfig | 5 +- configs/M54455EVB_stm33_defconfig | 5 +- configs/MPC8536DS_36BIT_defconfig | 5 +- configs/MPC8536DS_SDCARD_defconfig | 5 +- configs/MPC8536DS_SPIFLASH_defconfig | 5 +- configs/MPC8536DS_defconfig | 5 +- configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 5 +- configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 5 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 5 +- .../P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 5 +- configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_NAND_defconfig | 5 +- configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_NOR_defconfig | 5 +- configs/P1010RDB-PA_SDCARD_defconfig | 5 +- configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 5 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 5 +- configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 5 +- configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 5 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 5 +- .../P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 5 +- configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_NAND_defconfig | 5 +- configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_NOR_defconfig | 5 +- configs/P1010RDB-PB_SDCARD_defconfig | 5 +- configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 5 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 5 +- configs/P1020RDB-PC_36BIT_NAND_defconfig | 5 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 5 +- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 5 +- configs/P1020RDB-PC_36BIT_defconfig | 5 +- configs/P1020RDB-PC_NAND_defconfig | 5 +- configs/P1020RDB-PC_SDCARD_defconfig | 5 +- configs/P1020RDB-PC_SPIFLASH_defconfig | 5 +- configs/P1020RDB-PC_defconfig | 5 +- configs/P1020RDB-PD_NAND_defconfig | 5 +- configs/P1020RDB-PD_SDCARD_defconfig | 5 +- configs/P1020RDB-PD_SPIFLASH_defconfig | 5 +- configs/P1020RDB-PD_defconfig | 5 +- configs/P1021RDB-PC_36BIT_NAND_defconfig | 5 +- configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 5 +- configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 5 +- configs/P1021RDB-PC_36BIT_defconfig | 5 +- configs/P1021RDB-PC_NAND_defconfig | 5 +- configs/P1021RDB-PC_SDCARD_defconfig | 5 +- configs/P1021RDB-PC_SPIFLASH_defconfig | 5 +- configs/P1021RDB-PC_defconfig | 5 +- configs/P1022DS_36BIT_NAND_defconfig | 5 +- configs/P1022DS_36BIT_SDCARD_defconfig | 5 +- configs/P1022DS_36BIT_SPIFLASH_defconfig | 5 +- configs/P1022DS_36BIT_defconfig | 5 +- configs/P1022DS_NAND_defconfig | 5 +- configs/P1022DS_SDCARD_defconfig | 5 +- configs/P1022DS_SPIFLASH_defconfig | 5 +- configs/P1022DS_defconfig | 5 +- configs/P1024RDB_36BIT_defconfig | 5 +- configs/P1024RDB_NAND_defconfig | 5 +- configs/P1024RDB_SDCARD_defconfig | 5 +- configs/P1024RDB_SPIFLASH_defconfig | 5 +- configs/P1024RDB_defconfig | 5 +- configs/P1025RDB_36BIT_defconfig | 5 +- configs/P1025RDB_NAND_defconfig | 5 +- configs/P1025RDB_SDCARD_defconfig | 5 +- configs/P1025RDB_SPIFLASH_defconfig | 5 +- configs/P1025RDB_defconfig | 5 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 5 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 5 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 5 +- configs/P2020RDB-PC_36BIT_defconfig | 5 +- configs/P2020RDB-PC_NAND_defconfig | 5 +- configs/P2020RDB-PC_SDCARD_defconfig | 5 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 5 +- configs/P2020RDB-PC_defconfig | 5 +- configs/P2041RDB_NAND_defconfig | 5 +- configs/P2041RDB_SDCARD_defconfig | 5 +- configs/P2041RDB_SECURE_BOOT_defconfig | 5 +- configs/P2041RDB_SPIFLASH_defconfig | 5 +- configs/P2041RDB_SRIO_PCIE_BOOT_defconfig | 5 +- configs/P2041RDB_defconfig | 5 +- configs/P3041DS_NAND_SECURE_BOOT_defconfig | 5 +- configs/P3041DS_NAND_defconfig | 5 +- configs/P3041DS_SDCARD_defconfig | 5 +- configs/P3041DS_SECURE_BOOT_defconfig | 5 +- configs/P3041DS_SPIFLASH_defconfig | 5 +- configs/P3041DS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/P3041DS_defconfig | 5 +- configs/P4080DS_SDCARD_defconfig | 5 +- configs/P4080DS_SECURE_BOOT_defconfig | 5 +- configs/P4080DS_SPIFLASH_defconfig | 5 +- configs/P4080DS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/P4080DS_defconfig | 5 +- configs/P5020DS_NAND_SECURE_BOOT_defconfig | 5 +- configs/P5020DS_NAND_defconfig | 5 +- configs/P5020DS_SDCARD_defconfig | 5 +- configs/P5020DS_SECURE_BOOT_defconfig | 5 +- configs/P5020DS_SPIFLASH_defconfig | 5 +- configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/P5020DS_defconfig | 5 +- configs/P5040DS_NAND_SECURE_BOOT_defconfig | 5 +- configs/P5040DS_NAND_defconfig | 5 +- configs/P5040DS_SDCARD_defconfig | 5 +- configs/P5040DS_SECURE_BOOT_defconfig | 5 +- configs/P5040DS_SPIFLASH_defconfig | 5 +- configs/P5040DS_defconfig | 5 +- configs/T1023RDB_NAND_defconfig | 5 +- configs/T1023RDB_SDCARD_defconfig | 5 +- configs/T1023RDB_SECURE_BOOT_defconfig | 5 +- configs/T1023RDB_SPIFLASH_defconfig | 5 +- configs/T1023RDB_defconfig | 5 +- configs/T1024QDS_DDR4_SECURE_BOOT_defconfig | 9 +- configs/T1024QDS_DDR4_defconfig | 9 +- configs/T1024QDS_NAND_defconfig | 9 +- configs/T1024QDS_SDCARD_defconfig | 9 +- configs/T1024QDS_SECURE_BOOT_defconfig | 9 +- configs/T1024QDS_SPIFLASH_defconfig | 9 +- configs/T1024QDS_defconfig | 9 +- configs/T1024RDB_NAND_defconfig | 5 +- configs/T1024RDB_SDCARD_defconfig | 5 +- configs/T1024RDB_SECURE_BOOT_defconfig | 5 +- configs/T1024RDB_SPIFLASH_defconfig | 5 +- configs/T1024RDB_defconfig | 5 +- configs/T1040D4RDB_NAND_defconfig | 5 +- configs/T1040D4RDB_SDCARD_defconfig | 5 +- configs/T1040D4RDB_SECURE_BOOT_defconfig | 5 +- configs/T1040D4RDB_SPIFLASH_defconfig | 5 +- configs/T1040D4RDB_defconfig | 5 +- configs/T1040QDS_DDR4_defconfig | 9 +- configs/T1040QDS_SECURE_BOOT_defconfig | 9 +- configs/T1040QDS_defconfig | 9 +- configs/T1040RDB_NAND_defconfig | 5 +- configs/T1040RDB_SDCARD_defconfig | 5 +- configs/T1040RDB_SECURE_BOOT_defconfig | 5 +- configs/T1040RDB_SPIFLASH_defconfig | 5 +- configs/T1040RDB_defconfig | 5 +- configs/T1042D4RDB_NAND_defconfig | 5 +- configs/T1042D4RDB_SDCARD_defconfig | 5 +- configs/T1042D4RDB_SECURE_BOOT_defconfig | 5 +- configs/T1042D4RDB_SPIFLASH_defconfig | 5 +- configs/T1042D4RDB_defconfig | 5 +- configs/T1042RDB_PI_NAND_defconfig | 5 +- configs/T1042RDB_PI_SDCARD_defconfig | 5 +- configs/T1042RDB_PI_SPIFLASH_defconfig | 5 +- configs/T1042RDB_PI_defconfig | 5 +- configs/T1042RDB_SECURE_BOOT_defconfig | 5 +- configs/T1042RDB_defconfig | 5 +- configs/T2080QDS_NAND_defconfig | 9 +- configs/T2080QDS_SDCARD_defconfig | 9 +- configs/T2080QDS_SECURE_BOOT_defconfig | 9 +- configs/T2080QDS_SPIFLASH_defconfig | 9 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 9 +- configs/T2080QDS_defconfig | 9 +- configs/T2080RDB_NAND_defconfig | 5 +- configs/T2080RDB_SDCARD_defconfig | 5 +- configs/T2080RDB_SECURE_BOOT_defconfig | 5 +- configs/T2080RDB_SPIFLASH_defconfig | 5 +- configs/T2080RDB_SRIO_PCIE_BOOT_defconfig | 5 +- configs/T2080RDB_defconfig | 5 +- configs/T2081QDS_NAND_defconfig | 9 +- configs/T2081QDS_SDCARD_defconfig | 9 +- configs/T2081QDS_SPIFLASH_defconfig | 9 +- configs/T2081QDS_SRIO_PCIE_BOOT_defconfig | 9 +- configs/T2081QDS_defconfig | 9 +- configs/T4160QDS_NAND_defconfig | 5 +- configs/T4160QDS_SDCARD_defconfig | 5 +- configs/T4160QDS_SECURE_BOOT_defconfig | 5 +- configs/T4160QDS_defconfig | 5 +- configs/T4160RDB_defconfig | 5 +- configs/T4240QDS_NAND_defconfig | 5 +- configs/T4240QDS_SDCARD_defconfig | 5 +- configs/T4240QDS_SECURE_BOOT_defconfig | 5 +- configs/T4240QDS_SRIO_PCIE_BOOT_defconfig | 5 +- configs/T4240QDS_defconfig | 5 +- configs/T4240RDB_SDCARD_defconfig | 5 +- configs/T4240RDB_defconfig | 5 +- configs/UCP1020_SPIFLASH_defconfig | 9 +- configs/UCP1020_defconfig | 9 +- configs/alt_defconfig | 7 +- configs/am335x_boneblack_defconfig | 5 +- configs/am335x_boneblack_vboot_defconfig | 5 +- configs/am335x_evm_defconfig | 5 +- configs/am335x_evm_nor_defconfig | 5 +- configs/am335x_evm_norboot_defconfig | 5 +- configs/am335x_evm_spiboot_defconfig | 5 +- configs/am335x_evm_usbspl_defconfig | 5 +- configs/am335x_gp_evm_defconfig | 5 +- configs/am437x_gp_evm_defconfig | 5 +- configs/am437x_sk_evm_defconfig | 9 +- configs/am43xx_evm_defconfig | 7 +- configs/am43xx_evm_ethboot_defconfig | 5 +- configs/am43xx_evm_qspiboot_defconfig | 5 +- configs/am43xx_evm_usbhost_boot_defconfig | 5 +- configs/am57xx_evm_defconfig | 5 +- configs/aristainetos2_defconfig | 5 +- configs/aristainetos2b_defconfig | 5 +- configs/aristainetos_defconfig | 5 +- configs/at91sam9n12ek_mmc_defconfig | 5 +- configs/at91sam9n12ek_nandflash_defconfig | 5 +- configs/at91sam9n12ek_spiflash_defconfig | 5 +- configs/at91sam9x5ek_dataflash_defconfig | 5 +- configs/at91sam9x5ek_mmc_defconfig | 5 +- configs/at91sam9x5ek_nandflash_defconfig | 5 +- configs/at91sam9x5ek_spiflash_defconfig | 5 +- configs/atngw100_defconfig | 5 +- configs/atngw100mkii_defconfig | 5 +- configs/axm_defconfig | 5 +- configs/bayleybay_defconfig | 9 +- configs/beaver_defconfig | 5 +- configs/bf518f-ezbrd_defconfig | 7 +- configs/bf525-ucr2_defconfig | 5 +- configs/bf526-ezbrd_defconfig | 5 +- configs/bf527-ad7160-eval_defconfig | 5 +- configs/bf527-ezkit-v2_defconfig | 5 +- configs/bf527-ezkit_defconfig | 5 +- configs/bf527-sdp_defconfig | 16 +- configs/bf537-minotaur_defconfig | 5 +- configs/bf537-pnav_defconfig | 5 +- configs/bf537-srv1_defconfig | 5 +- configs/bf537-stamp_defconfig | 16 +- configs/bf548-ezkit_defconfig | 5 +- configs/bf561-acvilon_defconfig | 5 +- configs/bf609-ezkit_defconfig | 16 +- configs/bg0900_defconfig | 7 +- configs/birdland_bav335a_defconfig | 5 +- configs/birdland_bav335b_defconfig | 5 +- configs/blackstamp_defconfig | 5 +- configs/blackvme_defconfig | 5 +- configs/br4_defconfig | 5 +- configs/cardhu_defconfig | 5 +- configs/chromebook_link_defconfig | 9 +- configs/chromebox_panther_defconfig | 9 +- configs/clearfog_defconfig | 3 +- configs/cm_fx6_defconfig | 17 +- .../controlcenterd_36BIT_SDCARD_DEVELOP_defconfig | 5 +- configs/controlcenterd_36BIT_SDCARD_defconfig | 5 +- configs/coreboot-x86_defconfig | 9 +- configs/crownbay_defconfig | 11 +- configs/d2net_v2_defconfig | 5 +- configs/da850_am18xxevm_defconfig | 7 +- configs/da850evm_defconfig | 7 +- configs/da850evm_direct_nor_defconfig | 7 +- configs/dalmore_defconfig | 5 +- configs/db-88f6820-gp_defconfig | 7 +- configs/db-mv784mp-gp_defconfig | 7 +- configs/dra72_evm_defconfig | 9 +- configs/dra74_evm_defconfig | 9 +- configs/dra7xx_evm_defconfig | 7 +- configs/dra7xx_evm_qspiboot_defconfig | 5 +- configs/dra7xx_evm_uart3_defconfig | 5 +- configs/draco_defconfig | 5 +- configs/dreamplug_defconfig | 5 +- configs/ds414_defconfig | 7 +- configs/e2220-1170_defconfig | 5 +- configs/ea20_defconfig | 5 +- configs/ethernut5_defconfig | 5 +- configs/galileo_defconfig | 9 +- configs/gose_defconfig | 7 +- configs/gplugd_defconfig | 7 +- configs/inetspace_v2_defconfig | 5 +- configs/ip04_defconfig | 7 +- configs/jetson-tk1_defconfig | 5 +- configs/k2e_evm_defconfig | 5 +- configs/k2g_evm_defconfig | 5 +- configs/k2hk_evm_defconfig | 5 +- configs/k2l_evm_defconfig | 5 +- configs/km_kirkwood_128m16_defconfig | 5 +- configs/km_kirkwood_defconfig | 5 +- configs/km_kirkwood_pci_defconfig | 5 +- configs/kmcoge4_defconfig | 7 +- configs/kmcoge5un_defconfig | 5 +- configs/kmlion1_defconfig | 7 +- configs/kmnusa_defconfig | 5 +- configs/kmsugp1_defconfig | 5 +- configs/kmsuv31_defconfig | 5 +- configs/koelsch_defconfig | 7 +- configs/lager_defconfig | 7 +- configs/ls1021aqds_qspi_defconfig | 7 +- configs/ls1021atwr_qspi_defconfig | 8 +- configs/ls1021atwr_sdcard_qspi_defconfig | 7 +- configs/ls1043aqds_defconfig | 3 +- configs/ls1043aqds_lpuart_defconfig | 3 +- configs/ls1043aqds_nand_defconfig | 3 +- configs/ls1043aqds_nor_ddr3_defconfig | 3 +- configs/ls1043aqds_qspi_defconfig | 3 +- configs/ls1043aqds_sdcard_ifc_defconfig | 3 +- configs/ls1043aqds_sdcard_qspi_defconfig | 3 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 3 +- configs/ls1043ardb_defconfig | 3 +- configs/ls1043ardb_nand_defconfig | 3 +- configs/ls1043ardb_sdcard_defconfig | 3 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2085aqds_defconfig | 2 +- configs/ls2085ardb_defconfig | 2 +- configs/lschlv2_defconfig | 5 +- configs/lsxhl_defconfig | 5 +- configs/m28evk_defconfig | 5 +- configs/marsboard_defconfig | 5 +- configs/maxbcm_defconfig | 11 +- configs/mgcoge3un_defconfig | 5 +- configs/minnowmax_defconfig | 11 +- configs/mx28evk_auart_console_defconfig | 5 +- configs/mx28evk_defconfig | 5 +- configs/mx28evk_nand_defconfig | 5 +- configs/mx28evk_spi_defconfig | 5 +- configs/mx6dlsabreauto_defconfig | 5 +- configs/mx6dlsabresd_defconfig | 5 +- configs/mx6qpsabreauto_defconfig | 5 +- configs/mx6qsabreauto_defconfig | 5 +- configs/mx6qsabrelite_defconfig | 5 +- configs/mx6qsabresd_defconfig | 5 +- configs/mx6sabresd_spl_defconfig | 5 +- configs/mx6slevk_defconfig | 5 +- configs/mx6slevk_spinor_defconfig | 5 +- configs/mx6slevk_spl_defconfig | 5 +- configs/mx6sxsabreauto_defconfig | 7 +- configs/mx6sxsabresd_defconfig | 5 +- configs/mx6sxsabresd_spl_defconfig | 3 +- configs/net2big_v2_defconfig | 5 +- configs/netspace_lite_v2_defconfig | 5 +- configs/netspace_max_v2_defconfig | 5 +- configs/netspace_mini_v2_defconfig | 5 +- configs/netspace_v2_defconfig | 5 +- configs/nitrogen6dl2g_defconfig | 5 +- configs/nitrogen6dl_defconfig | 5 +- configs/nitrogen6q2g_defconfig | 5 +- configs/nitrogen6q_defconfig | 5 +- configs/nitrogen6s1g_defconfig | 5 +- configs/nitrogen6s_defconfig | 5 +- configs/nyan-big_defconfig | 5 +- configs/omapl138_lcdk_defconfig | 7 +- configs/ot1200_defconfig | 11 +- configs/ot1200_spl_defconfig | 11 +- configs/p2371-0000_defconfig | 5 +- configs/p2371-2180_defconfig | 5 +- configs/p2571_defconfig | 5 +- configs/pcm051_rev1_defconfig | 5 +- configs/pcm051_rev3_defconfig | 5 +- configs/peach-pi_defconfig | 7 +- configs/peach-pit_defconfig | 7 +- configs/porter_defconfig | 7 +- configs/portl2_defconfig | 5 +- configs/pr1_defconfig | 5 +- configs/pxm2_defconfig | 5 +- configs/qemu-x86_defconfig | 9 +- configs/rastaban_defconfig | 5 +- configs/riotboard_defconfig | 5 +- configs/rut_defconfig | 5 +- configs/sama5d2_xplained_mmc_defconfig | 3 +- configs/sama5d2_xplained_spiflash_defconfig | 3 +- configs/sama5d3xek_mmc_defconfig | 5 +- configs/sama5d3xek_nandflash_defconfig | 5 +- configs/sama5d3xek_spiflash_defconfig | 5 +- configs/sama5d4_xplained_mmc_defconfig | 5 +- configs/sama5d4_xplained_nandflash_defconfig | 5 +- configs/sama5d4_xplained_spiflash_defconfig | 5 +- configs/sama5d4ek_mmc_defconfig | 5 +- configs/sama5d4ek_nandflash_defconfig | 5 +- configs/sama5d4ek_spiflash_defconfig | 5 +- configs/sandbox_defconfig | 19 +- configs/sh7752evb_defconfig | 7 +- configs/sh7753evb_defconfig | 7 +- configs/sh7757lcr_defconfig | 5 +- configs/silk_defconfig | 7 +- configs/smdk5250_defconfig | 7 +- configs/smdk5420_defconfig | 7 +- configs/snow_defconfig | 7 +- configs/socfpga_arria5_defconfig | 9 +- configs/socfpga_cyclone5_defconfig | 9 +- configs/socfpga_sockit_defconfig | 9 +- configs/socfpga_socrates_defconfig | 7 +- configs/socfpga_sr1500_defconfig | 5 +- configs/spring_defconfig | 7 +- configs/stout_defconfig | 7 +- configs/stv0991_defconfig | 4 +- configs/taurus_defconfig | 5 +- configs/tec-ng_defconfig | 5 +- configs/theadorable_debug_defconfig | 7 +- configs/theadorable_defconfig | 7 +- configs/thuban_defconfig | 5 +- configs/tqma6q_mba6_mmc_defconfig | 5 +- configs/tqma6q_mba6_spi_defconfig | 5 +- configs/tqma6s_mba6_mmc_defconfig | 5 +- configs/tqma6s_mba6_spi_defconfig | 5 +- configs/trimslice_defconfig | 5 +- configs/tseries_spi_defconfig | 5 +- configs/venice2_defconfig | 5 +- configs/vf610twr_defconfig | 3 +- configs/vf610twr_nand_defconfig | 3 +- configs/zynq_microzed_defconfig | 9 +- configs/zynq_zc702_defconfig | 11 +- configs/zynq_zc706_defconfig | 11 +- configs/zynq_zc770_xm010_defconfig | 13 +- configs/zynq_zc770_xm013_defconfig | 5 +- configs/zynq_zed_defconfig | 11 +- configs/zynq_zybo_defconfig | 5 +- doc/SPI/README.ti_qspi_dra_test | 2 +- doc/device-tree-bindings/mtd/jedec,spi-nor.txt | 78 ++ doc/mtd/spi-nor.txt | 81 ++ drivers/Makefile | 2 +- drivers/dfu/dfu_sf.c | 12 +- drivers/mtd/Kconfig | 2 +- drivers/mtd/spi-nor/Kconfig | 125 +++ drivers/mtd/spi-nor/Makefile | 20 + drivers/mtd/{spi => spi-nor}/fsl_espi_spl.c | 6 +- drivers/mtd/spi-nor/m25p80.c | 332 ++++++ .../sf_dataflash.c => spi-nor/mtd_dataflash.c} | 429 ++++--- drivers/mtd/{spi => spi-nor}/sandbox.c | 51 +- drivers/mtd/spi-nor/spi-nor-ids.c | 283 +++++ drivers/mtd/spi-nor/spi-nor-probe.c | 52 + drivers/mtd/spi-nor/spi-nor.c | 1141 +++++++++++++++++++ drivers/mtd/{spi => spi-nor}/spi_spl_load.c | 7 +- drivers/mtd/spi/Kconfig | 131 --- drivers/mtd/spi/Makefile | 18 - drivers/mtd/spi/sf-uclass.c | 103 -- drivers/mtd/spi/sf.c | 58 - drivers/mtd/spi/sf_internal.h | 243 ---- drivers/mtd/spi/sf_mtd.c | 104 -- drivers/mtd/spi/sf_params.c | 146 --- drivers/mtd/spi/sf_probe.c | 181 --- drivers/mtd/spi/spi_flash.c | 1185 -------------------- drivers/net/fm/fm.c | 2 +- drivers/net/phy/cortina.c | 2 +- drivers/spi/fsl_qspi.c | 18 +- drivers/spi/ich.c | 6 +- drivers/spi/spi-uclass.c | 35 +- drivers/spi/spi.c | 24 + drivers/spi/ti_qspi.c | 6 +- examples/standalone/Makefile | 2 +- include/configs/MPC8536DS.h | 2 +- include/configs/P1010RDB.h | 3 +- include/configs/P1022DS.h | 3 +- include/configs/T102xQDS.h | 5 +- include/configs/T102xRDB.h | 5 +- include/configs/T104xRDB.h | 5 +- include/configs/T208xQDS.h | 7 +- include/configs/T208xRDB.h | 7 +- include/configs/UCP1020.h | 4 +- include/configs/am335x_evm.h | 3 +- include/configs/am43xx_evm.h | 2 +- include/configs/aristainetos-common.h | 1 - include/configs/at91sam9n12ek.h | 3 +- include/configs/at91sam9x5ek.h | 3 +- include/configs/bav335x.h | 3 +- include/configs/bfin_adi_common.h | 2 +- include/configs/cgtqmx6eval.h | 10 +- include/configs/chromebook_jerry.h | 5 +- include/configs/clearfog.h | 5 +- include/configs/cm_fx6.h | 3 +- include/configs/cm_t43.h | 9 +- include/configs/da850evm.h | 6 +- include/configs/db-88f6820-gp.h | 3 +- include/configs/db-mv784mp-gp.h | 3 +- include/configs/dra7xx_evm.h | 5 +- include/configs/dreamplug.h | 2 +- include/configs/ds414.h | 3 +- include/configs/exynos5-common.h | 2 +- include/configs/gw_ventana.h | 13 +- include/configs/km/kmp204x-common.h | 2 +- include/configs/ls1021aqds.h | 2 - include/configs/ls1021atwr.h | 1 - include/configs/ls1043a_common.h | 8 +- include/configs/ls1043aqds.h | 2 +- include/configs/ls2080aqds.h | 3 +- include/configs/ls2080ardb.h | 5 +- include/configs/lsxl.h | 2 +- include/configs/maxbcm.h | 3 +- include/configs/mx6ul_14x14_evk.h | 7 +- include/configs/mx7dsabresd.h | 7 +- include/configs/omapl138_lcdk.h | 3 +- include/configs/ot1200.h | 3 +- include/configs/p1_p2_rdb_pc.h | 5 +- include/configs/pcm051.h | 3 +- include/configs/pcm052.h | 3 +- include/configs/rk3036_common.h | 4 +- include/configs/rk3288_common.h | 2 +- include/configs/sama5d2_xplained.h | 5 +- include/configs/sama5d3xek.h | 3 +- include/configs/sama5d4_xplained.h | 3 +- include/configs/sama5d4ek.h | 3 +- include/configs/siemens-am33x-common.h | 3 +- include/configs/socfpga_common.h | 8 +- include/configs/taurus.h | 3 +- include/configs/tegra-common-usb-gadget.h | 2 +- include/configs/theadorable.h | 3 +- include/configs/ti_armv7_keystone2.h | 3 +- include/configs/tseries.h | 3 +- include/configs/zynq-common.h | 6 +- include/dm/uclass-id.h | 1 - include/linux/err.h | 5 + include/linux/mtd/spi-nor.h | 253 +++++ include/spi.h | 33 +- include/spi_flash.h | 233 +--- 566 files changed, 4437 insertions(+), 3863 deletions(-) create mode 100644 doc/device-tree-bindings/mtd/jedec,spi-nor.txt create mode 100644 doc/mtd/spi-nor.txt create mode 100644 drivers/mtd/spi-nor/Kconfig create mode 100644 drivers/mtd/spi-nor/Makefile rename drivers/mtd/{spi => spi-nor}/fsl_espi_spl.c (97%) create mode 100644 drivers/mtd/spi-nor/m25p80.c rename drivers/mtd/{spi/sf_dataflash.c => spi-nor/mtd_dataflash.c} (61%) rename drivers/mtd/{spi => spi-nor}/sandbox.c (95%) create mode 100644 drivers/mtd/spi-nor/spi-nor-ids.c create mode 100644 drivers/mtd/spi-nor/spi-nor-probe.c create mode 100644 drivers/mtd/spi-nor/spi-nor.c rename drivers/mtd/{spi => spi-nor}/spi_spl_load.c (94%) delete mode 100644 drivers/mtd/spi/Kconfig delete mode 100644 drivers/mtd/spi/Makefile delete mode 100644 drivers/mtd/spi/sf-uclass.c delete mode 100644 drivers/mtd/spi/sf.c delete mode 100644 drivers/mtd/spi/sf_internal.h delete mode 100644 drivers/mtd/spi/sf_mtd.c delete mode 100644 drivers/mtd/spi/sf_params.c delete mode 100644 drivers/mtd/spi/sf_probe.c delete mode 100644 drivers/mtd/spi/spi_flash.c create mode 100644 include/linux/mtd/spi-nor.h -- 1.9.1

9 46

[U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax
by Saket Sinha 21 Mar '16

21 Mar '16

This series adds ACPI table support on Minnowmax. Saket Sinha (2): x86: Add ACPI table support to Minnowmax x86: Add DSDT table for supporting ACPI on Minnowmax board/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++ board/intel/minnowmax/acpi/cpu.asl | 65 +++++++ board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++ board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++ board/intel/minnowmax/acpi/mainboard.asl | 13 ++ board/intel/minnowmax/acpi/platform.asl | 62 ++++++ board/intel/minnowmax/acpi/sleepstates.asl | 14 ++ board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++ board/intel/minnowmax/dsdt.asl | 46 +++++ 10 files changed, 884 insertions(+) create mode 100644 board/intel/minnowmax/acpi.c create mode 100644 board/intel/minnowmax/acpi/cpu.asl create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/acpi/platform.asl create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl create mode 100644 board/intel/minnowmax/acpi/southcluster.asl create mode 100644 board/intel/minnowmax/dsdt.asl -- 2.1.4

3 7

[U-Boot] [PATCH 14/18 v2] sf: add 4byte address opcodes
by Cyrille Pitchen 21 Mar '16

21 Mar '16

This patch provides an alternative to support memory >16MiB (>128Mib). Indeed using the Base Address Register changes the internal state of the SPI flash memory. However some early boot loaders expect to access the first memory bank of the SPI flash. Then when another bank has been selected, those boot loader will fail to read the right data. Using 4byte address opcodes doesn't change the internal state of the SPI flash memory but sill allows to access data above 16MiB. Signed-off-by: Cyrille Pitchen <cyrille.pitchen(a)atmel.com> --- ChangeLog: v1 -> v2: - add missing entry for PAGE PROGRAM op code drivers/mtd/spi/Kconfig | 18 ++++++++- drivers/mtd/spi/sf_internal.h | 17 +++++++- drivers/mtd/spi/spi_flash.c | 94 +++++++++++++++++++++++++++++++++++++------ include/spi_flash.h | 2 + 4 files changed, 115 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 3f7433cbc214..999c3176adee 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -34,14 +34,30 @@ config SPI_FLASH If unsure, say N +config SPI_FLASH_ABOVE_16MB + bool "Support of >16MB memories" + depends on SPI_FLASH + default n + +choice + prompt "Select >16MB method" + depends on SPI_FLASH_ABOVE_16MB + config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" - depends on SPI_FLASH help Enable the SPI flash Bank/Extended address register support. Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_4B_OPCODES + bool "4-byte address op codes support" + help + Replace regular 3-byte address op codes by thier 4-byte address + version when the size of the memory if greater than 16MB. + +endchoice + if SPI_FLASH config SPI_FLASH_ATMEL diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 86a0276f8518..a98c011218ce 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -62,8 +62,8 @@ enum spi_nor_option_flags { SNOR_F_USE_FSR = BIT(2), }; -#define SPI_FLASH_3B_ADDR_LEN 3 -#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) +#define SPI_FLASH_4B_ADDR_LEN 4 +#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_4B_ADDR_LEN) #define SPI_FLASH_16MB_BOUN 0x1000000 /* CFI Manufacture ID's */ @@ -79,6 +79,9 @@ enum spi_nor_option_flags { #define CMD_ERASE_32K 0x52 #define CMD_ERASE_CHIP 0xc7 #define CMD_ERASE_64K 0xd8 +#define CMD_ERASE_4K_4B 0x21 +#define CMD_ERASE_32K_4B 0x5c +#define CMD_ERASE_64K_4B 0xdc /* Write commands */ #define CMD_WRITE_STATUS 0x01 @@ -86,6 +89,10 @@ enum spi_nor_option_flags { #define CMD_WRITE_DISABLE 0x04 #define CMD_WRITE_ENABLE 0x06 #define CMD_QUAD_PAGE_PROGRAM 0x32 +#define CMD_QUAD_PAGE_PROGRAM_MXIC 0x38 +#define CMD_PAGE_PROGRAM_4B 0x12 +#define CMD_QUAD_PAGE_PROGRAM_4B 0x34 +#define CMD_QUAD_PAGE_PROGRAM_MXIC_4B 0x3e /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -94,6 +101,12 @@ enum spi_nor_option_flags { #define CMD_READ_DUAL_IO_FAST 0xbb #define CMD_READ_QUAD_OUTPUT_FAST 0x6b #define CMD_READ_QUAD_IO_FAST 0xeb +#define CMD_READ_ARRAY_SLOW_4B 0x13 +#define CMD_READ_ARRAY_FAST_4B 0x0c +#define CMD_READ_DUAL_OUTPUT_FAST_4B 0x3c +#define CMD_READ_DUAL_IO_FAST_4B 0xbc +#define CMD_READ_QUAD_OUTPUT_FAST_4B 0x6c +#define CMD_READ_QUAD_IO_FAST_4B 0xec #define CMD_READ_ID 0x9f #define CMD_READ_STATUS 0x05 #define CMD_READ_STATUS1 0x35 diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 01a073d81eb9..8c327961302c 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -22,12 +22,15 @@ DECLARE_GLOBAL_DATA_PTR; -static void spi_flash_addr(u32 addr, u8 *cmd) +static void spi_flash_addr(const struct spi_flash *flash, u32 addr, u8 *cmd) { + u8 shift = flash->addr_width * 8; + /* cmd[0] is actual command */ - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr >> 0; + cmd[1] = addr >> (shift - 8); + cmd[2] = addr >> (shift - 16); + cmd[3] = addr >> (shift - 24); + cmd[4] = addr >> (shift - 32); } static int read_sr(struct spi_flash *flash, u8 *rs) @@ -154,6 +157,63 @@ bar_end: } #endif +#ifdef CONFIG_SPI_FLASH_4B_OPCODES +struct address_entry { + u8 src_opcode; + u8 dst_opcode; +}; + +static u8 spi_flash_convert_opcode(u8 opcode, + const struct address_entry *entries, + size_t num_entries) +{ + int b, e; + + b = 0; + e = num_entries - 1; + while (b <= e) { + int m = (b + e) >> 1; + const struct address_entry *entry = &entries[m]; + + if (opcode == entry->src_opcode) + return entry->dst_opcode; + + if (opcode < entry->src_opcode) + e = m - 1; + else + b = m + 1; + } + + /* No convertion found */ + return opcode; +} + +static u8 spi_flash_3to4_opcode(u8 opcode) +{ + /* MUST be sorted by 3byte opcode */ +#define ENTRY_3TO4(_opcode) { _opcode, _opcode##_4B } + static const struct address_entry spi_flash_3to4_table[] = { + ENTRY_3TO4(CMD_PAGE_PROGRAM), /* 0x02 */ + ENTRY_3TO4(CMD_READ_ARRAY_SLOW), /* 0x03 */ + ENTRY_3TO4(CMD_READ_ARRAY_FAST), /* 0x0b */ + ENTRY_3TO4(CMD_ERASE_4K), /* 0x20 */ + ENTRY_3TO4(CMD_QUAD_PAGE_PROGRAM), /* 0x32 */ + ENTRY_3TO4(CMD_QUAD_PAGE_PROGRAM_MXIC), /* 0x38 */ + ENTRY_3TO4(CMD_READ_DUAL_OUTPUT_FAST), /* 0x3b */ + ENTRY_3TO4(CMD_ERASE_32K), /* 0x52 */ + ENTRY_3TO4(CMD_READ_QUAD_OUTPUT_FAST), /* 0x6b */ + ENTRY_3TO4(CMD_READ_DUAL_IO_FAST), /* 0xbb */ + ENTRY_3TO4(CMD_ERASE_64K), /* 0xd8 */ + ENTRY_3TO4(CMD_READ_QUAD_IO_FAST), /* 0xeb */ + }; +#undef ENTRY_3TO4 + + return spi_flash_convert_opcode(opcode, + spi_flash_3to4_table, + ARRAY_SIZE(spi_flash_3to4_table)); +} +#endif /* CONFIG_SPI_FLASH_4B_OPCODES */ + #ifdef CONFIG_SF_DUAL_FLASH static void spi_flash_dual(struct spi_flash *flash, u32 *addr) { @@ -353,10 +413,11 @@ static int spi_flash_erase_impl(struct spi_flash *flash, u32 offset) { struct spi_slave *spi = flash->spi; u8 cmd[SPI_FLASH_CMD_LEN]; + size_t cmdsz = 1 + flash->addr_width; cmd[0] = flash->erase_cmd; - spi_flash_addr(offset, cmd); - return spi_flash_cmd_write(spi, cmd, sizeof(cmd), NULL, 0); + spi_flash_addr(flash, offset, cmd); + return spi_flash_cmd_write(spi, cmd, cmdsz, NULL, 0); } int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) @@ -461,10 +522,10 @@ static int spi_flash_write_impl(struct spi_flash *flash, u32 offset, { struct spi_slave *spi = flash->spi; u8 cmd[SPI_FLASH_CMD_LEN]; - size_t cmdsz = sizeof(cmd); + size_t cmdsz = 1 + flash->addr_width; cmd[0] = flash->write_cmd; - spi_flash_addr(offset, cmd); + spi_flash_addr(flash, offset, cmd); #ifdef CONFIG_SPI_FLASH_SST if (flash->flags & SNOR_F_SST_WR_2ND) cmdsz = 1; @@ -567,7 +628,7 @@ static int spi_flash_read_impl(struct spi_flash *flash, u32 offset, size_t cmdsz; int ret; - cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; + cmdsz = 1 + flash->addr_width + flash->dummy_byte; cmd = calloc(1, cmdsz); if (!cmd) { debug("SF: Failed to allocate cmd\n"); @@ -575,7 +636,7 @@ static int spi_flash_read_impl(struct spi_flash *flash, u32 offset, } cmd[0] = flash->read_cmd; - spi_flash_addr(offset, cmd); + spi_flash_addr(flash, offset, cmd); ret = spi_flash_cmd_read(spi, cmd, cmdsz, buf, len); free(cmd); return ret; @@ -1255,15 +1316,22 @@ int spi_flash_scan(struct spi_flash *flash, u8 e_rd_cmd) puts("\n"); #endif -#ifndef CONFIG_SPI_FLASH_BAR + /* Set number of bytes for address and convert opcodes if needed */ + flash->addr_width = 3; if (((flash->dual_flash == SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN << 1))) { +#if defined(CONFIG_SPI_FLASH_4B_OPCODES) + flash->addr_width = 4; + flash->read_cmd = spi_flash_3to4_opcode(flash->read_cmd); + flash->write_cmd = spi_flash_3to4_opcode(flash->write_cmd); + flash->erase_cmd = spi_flash_3to4_opcode(flash->erase_cmd); +#elif !defined(CONFIG_SPI_FLASH_BAR) puts("SF: Warning - Only lower 16MiB accessible,"); - puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); - } + puts(" Full access #define CONFIG_SPI_FLASH_ABOVE_16MB\n"); #endif + } return ret; } diff --git a/include/spi_flash.h b/include/spi_flash.h index 945cc07ee8b2..5db06e5133f3 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -88,6 +88,7 @@ enum spi_flash_protocol { * @read_proto SPI protocol to be used by &read ops * @write_proto SPI protocol to be used by &write ops * @erase_proto SPI protocol to be used by &erase ops + * @addr_width Number of address bytes (typically 3 or 4) * @memory_map: Address of read-only SPI flash access * @flash_lock: lock a region of the SPI Flash * @flash_unlock: unlock a region of the SPI Flash @@ -117,6 +118,7 @@ struct spi_flash { u32 page_size; u32 sector_size; u32 erase_size; + u32 addr_width; #ifdef CONFIG_SPI_FLASH_BAR u8 bank_read_cmd; u8 bank_write_cmd; -- 1.8.2.2

1 0

[U-Boot] [PATCH 0/3] Update gdsys board support
by dirk.eibach＠gdsys.cc 21 Mar '16

21 Mar '16

From: Dirk Eibach <dirk.eibach(a)gdsys.cc> Dirk Eibach (2): strider: Add DP501 support for cpu model strider: Define pca593x widths Reinhard Pfau (1): strider: use optimised bus timing for FPGA access board/gdsys/common/dp501.c | 31 +++++++++++++++++++++++++++++++ board/gdsys/common/dp501.h | 1 + board/gdsys/common/osd.c | 22 +--------------------- board/gdsys/mpc8308/strider.c | 31 ++++++++++++++++++++++++++----- include/configs/strider.h | 16 ++++++++++------ 5 files changed, 69 insertions(+), 32 deletions(-) -- 2.1.3

2 4

[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 21 Mar '16

21 Mar '16

The following changes since commit e4fb863f6dec0002069d57422ebe3ce3af69a273: dm: blk: Add tests for block devices (2016-03-17 21:27:39 -0600) are available in the git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to 93d9fc26cb7b4fcbb849e79d21d16b114e4501a9: arm: socfpga: sr1500: Misc updates (SPI speed, env location) (2016-03-20 18:01:11 +0100) ---------------------------------------------------------------- Chin Liang See (1): arm: socfpga: Enabling U-Boot environment support in QSPI Marek Vasut (1): arm: socfpga: Fix SR1500 env position Stefan Roese (2): arm: socfpga: Allow boards to define a custom environment size arm: socfpga: sr1500: Misc updates (SPI speed, env location) arch/arm/dts/socfpga_cyclone5_sr1500.dts | 2 +- configs/socfpga_sr1500_defconfig | 2 ++ include/configs/socfpga_common.h | 8 ++++++++ include/configs/socfpga_sr1500.h | 25 +++++++++++++++---------- 4 files changed, 26 insertions(+), 11 deletions(-)

2 1

[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 21 Mar '16

21 Mar '16

The following changes since commit e4fb863f6dec0002069d57422ebe3ce3af69a273: dm: blk: Add tests for block devices (2016-03-17 21:27:39 -0600) are available in the git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to 1b108880e6433e398681785f51b2a2dca983cd1b: usb: xhci: Fix vendor command error if the request type is USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION. (2016-03-20 18:00:45 +0100) ---------------------------------------------------------------- Stefan Roese (4): usb: legacy_hub_port_reset(): Speedup hub reset handling usb: Remove 200 ms delay in usb_hub_port_connect_change() usb: Don't reset the USB hub a 2nd time usb: Change power-on / scanning timeout handling Ted Chen (1): usb: xhci: Fix vendor command error if the request type is USB_REQ_SET_ADDRESS or USB_REQ_SET_CONFIGURATION. common/usb.c | 13 +---- common/usb_hub.c | 329 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------- drivers/usb/host/xhci.c | 6 ++- include/usb.h | 4 ++ 4 files changed, 239 insertions(+), 113 deletions(-)

2 1

Re: [U-Boot] [PATCH] Add CONFIG_GMAC_TX_DELAY=4 for OlinuXino Lime2
by Michael Haas 20 Mar '16

20 Mar '16

Hello all, On 03/16/2016 09:36 PM, Karsten Merker wrote: > Michael, if you would like to try testing higher RX delay chain values > on the Lime2, I have attached a small patch that adds an appropriate > Kconfig option. Regards, Karsten I will be testing your patch along with Hans' patch. In fact, I have already compiled it - I'm just waiting for a new SD card reader to arrive tomorrow. Sorry for the delay. In the mean time, as I was trying to get the device to boot at all (not related to u-boot, just my broken sdcard setup), I did try my old SD card again to load the debian netinstaller. This should be the version with the TX_DELAY set to 4. Now I'm sitting in an ash shell and I can wget files from my desktop at around 100MB/s. ~ # wget http://192.168.1.170:8000/debian-8.3.0-i386-netinst.iso -O - | md5sum Connecting to 192.168.1.170:8000 (192.168.1.170:8000) - 100% |*******************************| 315M 0:00:00 ETA 37f329724a1c072cbe0ebda211fdeb88 - ~ # wget http://192.168.1.170:8000/debian-8.3.0-i386-netinst.iso -O - | md5sum Connecting to 192.168.1.170:8000 (192.168.1.170:8000) - 100% |*******************************| 315M 0:00:00 ETA 37f329724a1c072cbe0ebda211fdeb88 - ~ # date +%s; wget http://192.168.1.170:8000/debian-8.3.0-i386-netinst.iso -O /d ev/null; date +%s 1258 Connecting to 192.168.1.170:8000 (192.168.1.170:8000) null 100% |*******************************| 315M 0:00:00 ETA 1261 ~ # dmesg | grep -i link [ 1.504918] audit: initializing netlink subsys (disabled) [ 88.561822] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready [ 90.547368] sun7i-dwmac 1c50000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx [ 90.547424] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready ~ # cat /etc/lsb-release DISTRIB_ID=Debian DISTRIB_DESCRIPTION="Debian GNU/Linux installer" DISTRIB_RELEASE="9 (stretch) - installer build 20160316-00:13" X_INSTALLATION_MEDIUM=netboot ~ # uname -a Linux debian 4.4.0-1-armmp #1 SMP Debian 4.4.4-2 (2016-03-09) armv7l GNU/Linux It takes around three seconds (date +%s; time not set) to transfer the 315MB. The md5sum matches. Now, with the device sitting on my desk in a debian installer session and working gbit.. how do I proceed from here? I don't dare rebooting.. Best Michael

3 14

[U-Boot] [PATCH] arm: socfpga: sockit: Use more relaxed DRAM timings
by Marek Vasut 20 Mar '16

20 Mar '16

The currently present DRAM timings generated from GHRD 14.0 did not work on SoCkit rev. D because they were too tight. Load the DRAM timings from GHRD 13.0 which are more relaxed and work with SoCkit rev. D. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Chin Liang See <clsee(a)altera.com> --- board/terasic/sockit/qts/iocsr_config.h | 116 ++++++++++++++++---------------- board/terasic/sockit/qts/pll_config.h | 14 ++-- board/terasic/sockit/qts/sdram_config.h | 30 ++++----- 3 files changed, 80 insertions(+), 80 deletions(-) diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h index 83b1093..51b262b 100644 --- a/board/terasic/sockit/qts/iocsr_config.h +++ b/board/terasic/sockit/qts/iocsr_config.h @@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00001000, 0xA0000034, 0x0D000001, - 0x40680208, - 0x41034051, - 0x12481A00, - 0x802080D0, - 0x34051406, - 0x01A02490, - 0x080D0000, - 0x51406802, - 0x02490340, + 0xE0680B2C, + 0x20834038, + 0x11441A00, + 0x80B2C0D0, + 0x34038E06, + 0x01A00208, + 0x2C0D0000, + 0x38E0680B, + 0x00208340, 0xD000001A, - 0x0680A280, + 0x0680B2C0, 0x10040000, 0x00200000, 0x10040000, @@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00001000, 0xA0000034, 0x0D000001, - 0x40680208, - 0x49034051, - 0x12481A02, - 0x80A280D0, - 0x34030C06, + 0xE0680B2C, + 0x20834038, + 0x11441A00, + 0x80B2C0D0, + 0x34038E06, 0x01A00040, - 0x280D0002, - 0x5140680A, - 0x02490340, - 0xD012481A, - 0x0680A280, + 0x2C0D0002, + 0x38E0680B, + 0x00208340, + 0xD001041A, + 0x0680B2C0, 0x10040000, 0x00200000, 0x10040000, @@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x04864000, - 0x59647A01, - 0xD32CA3DE, - 0xF551451E, - 0x034CD348, + 0x18864000, + 0x49247A06, + 0xABCF23D7, + 0xF7DE791E, + 0x0356E388, 0x821A0000, 0x0000D000, - 0x05140680, - 0xD669A47A, - 0x1ED32CA3, - 0x48F55E79, - 0x00034C92, + 0x05960680, + 0xD749247A, + 0x1EABCF23, + 0x88F7DE79, + 0x000356E3, 0x00080200, 0x00001000, 0x00080200, @@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x14864000, - 0x59647A05, - 0x9228A3DE, - 0xF65E791E, - 0x034CD348, - 0x821A0186, + 0x18864000, + 0x49247A06, + 0xABCF23D7, + 0xF7DE791E, + 0x0356E388, + 0x821A01C7, 0x0000D000, 0x00000680, - 0xD669A47A, - 0x1E9228A3, - 0x48F65E79, - 0x00034CD3, + 0xD749247A, + 0x1EABCF23, + 0x88F7DE79, + 0x000356E3, 0x00080200, 0x00001000, 0x00080200, @@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x0C864000, - 0x79E47A03, - 0xB2AAA3D1, - 0xF551451E, - 0x035CD348, + 0x18864000, + 0x49247A06, + 0xABCF23D7, + 0xF7DE791E, + 0x0356E388, 0x821A0000, 0x0000D000, 0x00000680, - 0xD159647A, - 0x1ED32CA3, - 0x48F55145, - 0x00035CD3, + 0xD749247A, + 0x1EABCF23, + 0x88F7DE79, + 0x000356E3, 0x00080200, 0x00001000, 0x00080200, @@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F1690D, 0x1A041414, 0x00D00000, - 0x04864000, - 0x69A47A01, - 0x9228A3D6, - 0xF65E791E, - 0x034C9248, + 0x18864000, + 0x49247A06, + 0xABCF23D7, + 0xF7DE791E, + 0x0356E388, 0x821A0000, 0x0000D000, 0x00000680, - 0xDE59647A, - 0x1ED32CA3, - 0x48F55E79, - 0x00034CD3, + 0xD749247A, + 0x1EABCF23, + 0x88F7DE79, + 0x000356E3, 0x00080200, 0x00001000, 0x00080200, diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h index 0ecccbf..820b9ff 100644 --- a/board/terasic/sockit/qts/pll_config.h +++ b/board/terasic/sockit/qts/pll_config.h @@ -10,13 +10,13 @@ #define CONFIG_HPS_DBCTRL_STAYOSC1 1 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 @@ -61,7 +61,7 @@ #define CONFIG_HPS_CLK_OSC2_HZ 25000000 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 #define CONFIG_HPS_CLK_EMAC0_HZ 1953125 @@ -69,7 +69,7 @@ #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 370000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 #define CONFIG_HPS_CLK_SPIM_HZ 200000000 #define CONFIG_HPS_CLK_CAN0_HZ 12500000 #define CONFIG_HPS_CLK_CAN1_HZ 12500000 @@ -78,8 +78,8 @@ #define CONFIG_HPS_CLK_L4_SP_HZ 100000000 #define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h index 81c7d8e..769aa77 100644 --- a/board/terasic/sockit/qts/sdram_config.h +++ b/board/terasic/sockit/qts/sdram_config.h @@ -32,11 +32,11 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 @@ -46,7 +46,7 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 @@ -127,8 +127,8 @@ /* Sequencer defines configuration */ #define AFI_RATE_RATIO 1 -#define CALIB_LFIFO_OFFSET 8 -#define CALIB_VFIFO_OFFSET 6 +#define CALIB_LFIFO_OFFSET 12 +#define CALIB_VFIFO_OFFSET 10 #define ENABLE_SUPER_QUICK_CALIBRATION 0 #define IO_DELAY_PER_DCHAIN_TAP 25 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 @@ -147,7 +147,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32 @@ -171,16 +171,16 @@ const u32 ac_rom_init[] = { 0x20700000, 0x20780000, - 0x10080431, - 0x10080530, - 0x10090044, - 0x100a0008, + 0x10080471, + 0x10080570, + 0x10090006, + 0x100a0218, 0x100b0000, 0x10380400, - 0x10080449, - 0x100804c8, - 0x100a0024, - 0x10090010, + 0x10080469, + 0x100804e8, + 0x100a0006, + 0x10090218, 0x100b0000, 0x30780000, 0x38780000, -- 2.7.0

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