March 2016 - U-Boot

[U-Boot] [PATCH] test/py: Add support for loading image via tftp to specified location
by Michal Simek 04 Apr '16

04 Apr '16

For example this setting: env__net_tftp_readable_file = { "fn": "ep108/image.ub", "addr": "0x10000000", "size": 25846296, "crc32": "b726f9de", } Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- test/py/tests/test_net.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/test/py/tests/test_net.py b/test/py/tests/test_net.py index 07393eb1fdf8..4c578273aee3 100644 --- a/test/py/tests/test_net.py +++ b/test/py/tests/test_net.py @@ -135,7 +135,12 @@ def test_net_tftpboot(u_boot_console): if not f: pytest.skip('No TFTP readable file to read') - addr = u_boot_utils.find_ram_base(u_boot_console) + addr = f.get('addr', None) + if addr: + addr = int(addr,16) + else: + addr = u_boot_utils.find_ram_base(u_boot_console) + fn = f['fn'] output = u_boot_console.run_command('tftpboot %x %s' % (addr, fn)) expected_text = 'Bytes transferred = ' -- 1.9.1

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[U-Boot] [PATCH v3 0/1] Use LS2080A as the only SoC name
by York Sun 04 Apr '16

04 Apr '16

Not long ago, a change was made in U-Boot to switch the primary SoC from LS2085A to LS2080A. SoC name and board names were changed. It turns out the same board support both SoCs with a socket. It is possible to swtich SoC. In this case, using one unified image is more appropriate. If future SoC can be hosted on the same boards, they should be added. At this moment, the board name remains LS2080ARDB and LS2080AQDS. They don't match the labels on the boards. Should this become a concern, we can rename the boards in a separated patch. Tested on LS2085ARDB with both personalities. Changes in v3: Fix checking AIOP. Tested on LS2080ARDB. Changes in v2: Add checking for SVR before starting AIOP Drop RFC from subject York Sun (1): armv8: LS2080A: Consolidate LS2080A and LS2085A arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 ++++--- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 6 ++++- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 26 ++++++++++++++++++- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 4 +-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 ++----- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 +- .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ board/freescale/ls2080a/ddr.c | 27 +++++++++++--------- board/freescale/ls2080a/ls2080a.c | 2 +- board/freescale/ls2080aqds/MAINTAINERS | 2 -- board/freescale/ls2080aqds/ddr.c | 27 +++++++++++--------- board/freescale/ls2080aqds/ls2080aqds.c | 2 +- board/freescale/ls2080ardb/MAINTAINERS | 2 -- board/freescale/ls2080ardb/ddr.c | 27 +++++++++++--------- board/freescale/ls2080ardb/ls2080ardb.c | 2 +- configs/ls2085aqds_defconfig | 19 -------------- configs/ls2085aqds_nand_defconfig | 14 ---------- configs/ls2085ardb_defconfig | 19 -------------- configs/ls2085ardb_nand_defconfig | 14 ---------- drivers/net/fsl-mc/mc.c | 4 +++ drivers/net/ldpaa_eth/Makefile | 1 - include/configs/ls2080a_common.h | 7 +---- include/configs/ls2080a_emu.h | 7 ----- include/configs/ls2080a_simu.h | 7 ----- include/linux/usb/xhci-fsl.h | 2 +- 28 files changed, 100 insertions(+), 152 deletions(-) delete mode 100644 configs/ls2085aqds_defconfig delete mode 100644 configs/ls2085aqds_nand_defconfig delete mode 100644 configs/ls2085ardb_defconfig delete mode 100644 configs/ls2085ardb_nand_defconfig -- 1.7.9.5

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[U-Boot] [PATCH v3 5/9] Drop command-processing code when CONFIG_CMDLINE is disabled
by Simon Glass 04 Apr '16

04 Apr '16

Command parsing and processing code is not needed when the command line is disabled. Remove this code in that case. Signed-off-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Tom Rini <trini(a)konsulko.com> --- Changes in v3: - Drop the indentation on the #if...#else...#endif Changes in v2: - Move the board_run_command() prototype into this patch cmd/help.c | 4 ++++ common/cli.c | 17 ++++++++++++++++- common/command.c | 6 ++++++ include/command.h | 18 ++++++++++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/cmd/help.c b/cmd/help.c index 6ff494d..701ae7e 100644 --- a/cmd/help.c +++ b/cmd/help.c @@ -10,9 +10,13 @@ static int do_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +#ifdef CONFIG_CMDLINE cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd); const int len = ll_entry_count(cmd_tbl_t, cmd); return _do_help(start, len, cmdtp, flag, argc, argv); +#else + return 0; +#endif } U_BOOT_CMD( diff --git a/common/cli.c b/common/cli.c index 119d282..5e17da8 100644 --- a/common/cli.c +++ b/common/cli.c @@ -18,6 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_CMDLINE /* * Run a command using the selected parser. * @@ -68,6 +69,7 @@ int run_command_repeatable(const char *cmd, int flag) return 0; #endif } +#endif /* CONFIG_CMDLINE */ int run_command_list(const char *cmd, int len, int flag) { @@ -102,7 +104,11 @@ int run_command_list(const char *cmd, int len, int flag) * doing a malloc() which is actually required only in a case that * is pretty rare. */ +#ifdef CONFIG_CMDLINE rcode = cli_simple_run_command_list(buff, flag); +#else + rcode = board_run_command(buff); +#endif #endif if (need_buff) free(buff); @@ -166,7 +172,9 @@ bool cli_process_fdt(const char **cmdp) */ void cli_secure_boot_cmd(const char *cmd) { +#ifdef CONFIG_CMDLINE cmd_tbl_t *cmdtp; +#endif int rc; if (!cmd) { @@ -178,6 +186,7 @@ void cli_secure_boot_cmd(const char *cmd) disable_ctrlc(1); /* Find the command directly. */ +#ifdef CONFIG_CMDLINE cmdtp = find_cmd(cmd); if (!cmdtp) { printf("## Error: \"%s\" not defined\n", cmd); @@ -187,6 +196,10 @@ void cli_secure_boot_cmd(const char *cmd) /* Run the command, forcing no flags and faking argc and argv. */ rc = (cmdtp->cmd)(cmdtp, 0, 1, (char **)&cmd); +#else + rc = board_run_command(cmd); +#endif + /* Shouldn't ever return from boot command. */ printf("## Error: \"%s\" returned (code %d)\n", cmd, rc); @@ -205,8 +218,10 @@ void cli_loop(void) parse_file_outer(); /* This point is never reached */ for (;;); -#else +#elif defined(CONFIG_CMDINE) cli_simple_loop(); +#else + printf("## U-Boot command line is disabled. Please enable CONFIG_CMDLINE\n"); #endif /*CONFIG_SYS_HUSH_PARSER*/ } diff --git a/common/command.c b/common/command.c index 858e288..e5d9b9c 100644 --- a/common/command.c +++ b/common/command.c @@ -85,6 +85,7 @@ int _do_help(cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t *cmdtp, int flag, /* find command table entry for a command */ cmd_tbl_t *find_cmd_tbl(const char *cmd, cmd_tbl_t *table, int table_len) { +#ifdef CONFIG_CMDLINE cmd_tbl_t *cmdtp; cmd_tbl_t *cmdtp_temp = table; /* Init value */ const char *p; @@ -111,6 +112,7 @@ cmd_tbl_t *find_cmd_tbl(const char *cmd, cmd_tbl_t *table, int table_len) if (n_found == 1) { /* exactly one match */ return cmdtp_temp; } +#endif /* CONFIG_CMDLINE */ return NULL; /* not found or ambiguous command */ } @@ -162,6 +164,7 @@ int var_complete(int argc, char * const argv[], char last_char, int maxv, char * static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]) { +#ifdef CONFIG_CMDLINE cmd_tbl_t *cmdtp = ll_entry_start(cmd_tbl_t, cmd); const int count = ll_entry_count(cmd_tbl_t, cmd); const cmd_tbl_t *cmdend = cmdtp + count; @@ -231,6 +234,9 @@ static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv cmdv[n_found] = NULL; return n_found; +#else + return 0; +#endif } static int make_argv(char *s, int argvsz, char *argv[]) diff --git a/include/command.h b/include/command.h index 0524c0b..0d2b653 100644 --- a/include/command.h +++ b/include/command.h @@ -144,6 +144,24 @@ int cmd_process(int flag, int argc, char * const argv[], int *repeatable, unsigned long *ticks); void fixup_cmdtable(cmd_tbl_t *cmdtp, int size); + +/** + * board_run_command() - Fallback function to execute a command + * + * When no command line features are enabled in U-Boot, this function is + * called to execute a command. Typically the function can look at the + * command and perform a few very specific tasks, such as booting the + * system in a particular way. + * + * This function is only used when CONFIG_CMDLINE is not enabled. + * + * In normal situations this function should not return, since U-Boot will + * simply hang. + * + * @cmdline: Command line string to execute + * @return 0 if OK, 1 for error + */ +int board_run_command(const char *cmdline); #endif /* __ASSEMBLY__ */ /* -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH 2/6 v3] net: mvpp2.c: Add Marvell mvpp2 network driver for Armada 375
by Stefan Roese 04 Apr '16

04 Apr '16

This patch adds support for the mvpp2 ethernet controller which is integrated in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4), which has been stripped of the in U-Boot unused portions. Tested on the Marvell Armada 375 eval board db-88f6720. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> --- v3: - Use priv_auto_alloc for the priv struct of the parent MISC driver instead of allocating manually v2: - Removed check for PHYLIB - Used U-Boot defines instead of Linux ones where possible - Added PROT_PPP_SES and PROT_IPV6 to include/net.h - Introduced probe function for the MISC parent driver, which now handles all the "do-once" things drivers/net/Kconfig | 8 + drivers/net/Makefile | 1 + drivers/net/mvpp2.c | 4190 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/net.h | 2 + 4 files changed, 4201 insertions(+) create mode 100644 drivers/net/mvpp2.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 2a229b8..d9dda16 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -94,6 +94,14 @@ config ETH_DESIGNWARE 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to provide the PHY (physical media interface). +config MVPP2 + bool "Marvell Armada 375 network interface support" + depends on ARMADA_375 + select PHYLIB + help + This driver supports the network interface units in the + Marvell ARMADA 375 SoC. + config PCH_GBE bool "Intel Platform Controller Hub EG20T GMAC driver" depends on DM_ETH && DM_PCI diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 33a81ee..fbedd04 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o obj-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVNETA) += mvneta.o +obj-$(CONFIG_MVPP2) += mvpp2.o obj-$(CONFIG_NATSEMI) += natsemi.o obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c new file mode 100644 index 0000000..900a04c --- /dev/null +++ b/drivers/net/mvpp2.c @@ -0,0 +1,4190 @@ +/* + * Driver for Marvell PPv2 network controller for Armada 375 SoC. + * + * Copyright (C) 2014 Marvell + * + * Marcin Wojtas <mw(a)semihalf.com> + * + * U-Boot version: + * Copyright (C) 2016 Stefan Roese <sr(a)denx.de> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <common.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <net.h> +#include <netdev.h> +#include <config.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <phy.h> +#include <miiphy.h> +#include <watchdog.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <linux/compat.h> +#include <linux/mbus.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Some linux -> U-Boot compatibility stuff */ +#define netdev_err(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_warn(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_info(dev, fmt, args...) \ + printf(fmt, ##args) +#define netdev_dbg(dev, fmt, args...) \ + printf(fmt, ##args) + +#define ETH_ALEN 6 /* Octets in one ethernet addr */ + +#define __verify_pcpu_ptr(ptr) \ +do { \ + const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \ + (void)__vpp_verify; \ +} while (0) + +#define VERIFY_PERCPU_PTR(__p) \ +({ \ + __verify_pcpu_ptr(__p); \ + (typeof(*(__p)) __kernel __force *)(__p); \ +}) + +#define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); }) +#define smp_processor_id() 0 +#define num_present_cpus() 1 +#define for_each_present_cpu(cpu) \ + for ((cpu) = 0; (cpu) < 1; (cpu)++) + +#define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE) + +#define CONFIG_NR_CPUS 1 +#define ETH_HLEN ETHER_HDR_SIZE /* Total octets in header */ + +/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ +#define WRAP (2 + ETH_HLEN + 4 + 32) +#define MTU 1500 +#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) + +#define MVPP2_SMI_TIMEOUT 10000 + +/* RX Fifo Registers */ +#define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) +#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) +#define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 +#define MVPP2_RX_FIFO_INIT_REG 0x64 + +/* RX DMA Top Registers */ +#define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) +#define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) +#define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) +#define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) +#define MVPP2_POOL_BUF_SIZE_OFFSET 5 +#define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) +#define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff +#define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) +#define MVPP2_RXQ_POOL_SHORT_OFFS 20 +#define MVPP2_RXQ_POOL_SHORT_MASK 0x700000 +#define MVPP2_RXQ_POOL_LONG_OFFS 24 +#define MVPP2_RXQ_POOL_LONG_MASK 0x7000000 +#define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 +#define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 +#define MVPP2_RXQ_DISABLE_MASK BIT(31) + +/* Parser Registers */ +#define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 +#define MVPP2_PRS_PORT_LU_MAX 0xf +#define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) +#define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) +#define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) +#define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) +#define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) +#define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) +#define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) +#define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) +#define MVPP2_PRS_TCAM_IDX_REG 0x1100 +#define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) +#define MVPP2_PRS_TCAM_INV_MASK BIT(31) +#define MVPP2_PRS_SRAM_IDX_REG 0x1200 +#define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) +#define MVPP2_PRS_TCAM_CTRL_REG 0x1230 +#define MVPP2_PRS_TCAM_EN_MASK BIT(0) + +/* Classifier Registers */ +#define MVPP2_CLS_MODE_REG 0x1800 +#define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) +#define MVPP2_CLS_PORT_WAY_REG 0x1810 +#define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) +#define MVPP2_CLS_LKP_INDEX_REG 0x1814 +#define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 +#define MVPP2_CLS_LKP_TBL_REG 0x1818 +#define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff +#define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) +#define MVPP2_CLS_FLOW_INDEX_REG 0x1820 +#define MVPP2_CLS_FLOW_TBL0_REG 0x1824 +#define MVPP2_CLS_FLOW_TBL1_REG 0x1828 +#define MVPP2_CLS_FLOW_TBL2_REG 0x182c +#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) +#define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 +#define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 +#define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) +#define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 +#define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) + +/* Descriptor Manager Top Registers */ +#define MVPP2_RXQ_NUM_REG 0x2040 +#define MVPP2_RXQ_DESC_ADDR_REG 0x2044 +#define MVPP2_RXQ_DESC_SIZE_REG 0x2048 +#define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 +#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) +#define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 +#define MVPP2_RXQ_NUM_NEW_OFFSET 16 +#define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) +#define MVPP2_RXQ_OCCUPIED_MASK 0x3fff +#define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 +#define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 +#define MVPP2_RXQ_THRESH_REG 0x204c +#define MVPP2_OCCUPIED_THRESH_OFFSET 0 +#define MVPP2_OCCUPIED_THRESH_MASK 0x3fff +#define MVPP2_RXQ_INDEX_REG 0x2050 +#define MVPP2_TXQ_NUM_REG 0x2080 +#define MVPP2_TXQ_DESC_ADDR_REG 0x2084 +#define MVPP2_TXQ_DESC_SIZE_REG 0x2088 +#define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 +#define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 +#define MVPP2_TXQ_THRESH_REG 0x2094 +#define MVPP2_TRANSMITTED_THRESH_OFFSET 16 +#define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000 +#define MVPP2_TXQ_INDEX_REG 0x2098 +#define MVPP2_TXQ_PREF_BUF_REG 0x209c +#define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) +#define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) +#define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) +#define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) +#define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) +#define MVPP2_TXQ_PENDING_REG 0x20a0 +#define MVPP2_TXQ_PENDING_MASK 0x3fff +#define MVPP2_TXQ_INT_STATUS_REG 0x20a4 +#define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) +#define MVPP2_TRANSMITTED_COUNT_OFFSET 16 +#define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 +#define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 +#define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 +#define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 +#define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff +#define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 +#define MVPP2_TXQ_RSVD_CLR_OFFSET 16 +#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) +#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) +#define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 +#define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) +#define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff +#define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) + +/* MBUS bridge registers */ +#define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) +#define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) +#define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) +#define MVPP2_BASE_ADDR_ENABLE 0x4060 + +/* Interrupt Cause and Mask registers */ +#define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) +#define MVPP2_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq)) +#define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) +#define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) +#define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) +#define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) +#define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff +#define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 +#define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) +#define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) +#define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) +#define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) +#define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) +#define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) +#define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) +#define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc +#define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff +#define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 +#define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) +#define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 + +/* Buffer Manager registers */ +#define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) +#define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 +#define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) +#define MVPP2_BM_POOL_SIZE_MASK 0xfff0 +#define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) +#define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 +#define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) +#define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 +#define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) +#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) +#define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff +#define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) +#define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) +#define MVPP2_BM_START_MASK BIT(0) +#define MVPP2_BM_STOP_MASK BIT(1) +#define MVPP2_BM_STATE_MASK BIT(4) +#define MVPP2_BM_LOW_THRESH_OFFS 8 +#define MVPP2_BM_LOW_THRESH_MASK 0x7f00 +#define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ + MVPP2_BM_LOW_THRESH_OFFS) +#define MVPP2_BM_HIGH_THRESH_OFFS 16 +#define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 +#define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ + MVPP2_BM_HIGH_THRESH_OFFS) +#define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) +#define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) +#define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) +#define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) +#define MVPP2_BM_BPPE_FULL_MASK BIT(3) +#define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) +#define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) +#define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) +#define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) +#define MVPP2_BM_VIRT_ALLOC_REG 0x6440 +#define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) +#define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) +#define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) +#define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) +#define MVPP2_BM_VIRT_RLS_REG 0x64c0 +#define MVPP2_BM_MC_RLS_REG 0x64c4 +#define MVPP2_BM_MC_ID_MASK 0xfff +#define MVPP2_BM_FORCE_RELEASE_MASK BIT(12) + +/* TX Scheduler registers */ +#define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 +#define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 +#define MVPP2_TXP_SCHED_ENQ_MASK 0xff +#define MVPP2_TXP_SCHED_DISQ_OFFSET 8 +#define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 +#define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 +#define MVPP2_TXP_SCHED_MTU_REG 0x801c +#define MVPP2_TXP_MTU_MAX 0x7FFFF +#define MVPP2_TXP_SCHED_REFILL_REG 0x8020 +#define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff +#define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 +#define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) +#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 +#define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff +#define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) +#define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff +#define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 +#define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) +#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) +#define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff +#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) +#define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff + +/* TX general registers */ +#define MVPP2_TX_SNOOP_REG 0x8800 +#define MVPP2_TX_PORT_FLUSH_REG 0x8810 +#define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) + +/* LMS registers */ +#define MVPP2_SRC_ADDR_MIDDLE 0x24 +#define MVPP2_SRC_ADDR_HIGH 0x28 +#define MVPP2_PHY_AN_CFG0_REG 0x34 +#define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) +#define MVPP2_MIB_COUNTERS_BASE(port) (0x1000 + ((port) >> 1) * \ + 0x400 + (port) * 0x400) +#define MVPP2_MIB_LATE_COLLISION 0x7c +#define MVPP2_ISR_SUM_MASK_REG 0x220c +#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c +#define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 + +/* Per-port registers */ +#define MVPP2_GMAC_CTRL_0_REG 0x0 +#define MVPP2_GMAC_PORT_EN_MASK BIT(0) +#define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 +#define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc +#define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) +#define MVPP2_GMAC_CTRL_1_REG 0x4 +#define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) +#define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) +#define MVPP2_GMAC_PCS_LB_EN_BIT 6 +#define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) +#define MVPP2_GMAC_SA_LOW_OFFS 7 +#define MVPP2_GMAC_CTRL_2_REG 0x8 +#define MVPP2_GMAC_INBAND_AN_MASK BIT(0) +#define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) +#define MVPP2_GMAC_PORT_RGMII_MASK BIT(4) +#define MVPP2_GMAC_PORT_RESET_MASK BIT(6) +#define MVPP2_GMAC_AUTONEG_CONFIG 0xc +#define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) +#define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) +#define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) +#define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) +#define MVPP2_GMAC_AN_SPEED_EN BIT(7) +#define MVPP2_GMAC_FC_ADV_EN BIT(9) +#define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) +#define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) +#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c +#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 +#define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 +#define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ + MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) + +#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff + +/* Descriptor ring Macros */ +#define MVPP2_QUEUE_NEXT_DESC(q, index) \ + (((index) < (q)->last_desc) ? ((index) + 1) : 0) + +/* SMI: 0xc0054 -> offset 0x54 to lms_base */ +#define MVPP2_SMI 0x0054 +#define MVPP2_PHY_REG_MASK 0x1f +/* SMI register fields */ +#define MVPP2_SMI_DATA_OFFS 0 /* Data */ +#define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS) +#define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ +#define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ +#define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ +#define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS) +#define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */ +#define MVPP2_SMI_BUSY (1 << 28) /* Busy */ + +#define MVPP2_PHY_ADDR_MASK 0x1f +#define MVPP2_PHY_REG_MASK 0x1f + +/* Various constants */ + +/* Coalescing */ +#define MVPP2_TXDONE_COAL_PKTS_THRESH 15 +#define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL +#define MVPP2_RX_COAL_PKTS 32 +#define MVPP2_RX_COAL_USEC 100 + +/* The two bytes Marvell header. Either contains a special value used + * by Marvell switches when a specific hardware mode is enabled (not + * supported by this driver) or is filled automatically by zeroes on + * the RX side. Those two bytes being at the front of the Ethernet + * header, they allow to have the IP header aligned on a 4 bytes + * boundary automatically: the hardware skips those two bytes on its + * own. + */ +#define MVPP2_MH_SIZE 2 +#define MVPP2_ETH_TYPE_LEN 2 +#define MVPP2_PPPOE_HDR_SIZE 8 +#define MVPP2_VLAN_TAG_LEN 4 + +/* Lbtd 802.3 type */ +#define MVPP2_IP_LBDT_TYPE 0xfffa + +#define MVPP2_CPU_D_CACHE_LINE_SIZE 32 +#define MVPP2_TX_CSUM_MAX_SIZE 9800 + +/* Timeout constants */ +#define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 +#define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 + +#define MVPP2_TX_MTU_MAX 0x7ffff + +/* Maximum number of T-CONTs of PON port */ +#define MVPP2_MAX_TCONT 16 + +/* Maximum number of supported ports */ +#define MVPP2_MAX_PORTS 4 + +/* Maximum number of TXQs used by single port */ +#define MVPP2_MAX_TXQ 8 + +/* Maximum number of RXQs used by single port */ +#define MVPP2_MAX_RXQ 8 + +/* Default number of TXQs in use */ +#define MVPP2_DEFAULT_TXQ 1 + +/* Dfault number of RXQs in use */ +#define MVPP2_DEFAULT_RXQ 1 +#define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */ + +/* Total number of RXQs available to all ports */ +#define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS * MVPP2_MAX_RXQ) + +/* Max number of Rx descriptors */ +#define MVPP2_MAX_RXD 16 + +/* Max number of Tx descriptors */ +#define MVPP2_MAX_TXD 16 + +/* Amount of Tx descriptors that can be reserved at once by CPU */ +#define MVPP2_CPU_DESC_CHUNK 64 + +/* Max number of Tx descriptors in each aggregated queue */ +#define MVPP2_AGGR_TXQ_SIZE 256 + +/* Descriptor aligned size */ +#define MVPP2_DESC_ALIGNED_SIZE 32 + +/* Descriptor alignment mask */ +#define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) + +/* RX FIFO constants */ +#define MVPP2_RX_FIFO_PORT_DATA_SIZE 0x2000 +#define MVPP2_RX_FIFO_PORT_ATTR_SIZE 0x80 +#define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 + +/* RX buffer constants */ +#define MVPP2_SKB_SHINFO_SIZE \ + 0 + +#define MVPP2_RX_PKT_SIZE(mtu) \ + ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ + ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE) + +#define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) +#define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) +#define MVPP2_RX_MAX_PKT_SIZE(total_size) \ + ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) + +#define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) + +/* IPv6 max L3 address size */ +#define MVPP2_MAX_L3_ADDR_SIZE 16 + +/* Port flags */ +#define MVPP2_F_LOOPBACK BIT(0) + +/* Marvell tag types */ +enum mvpp2_tag_type { + MVPP2_TAG_TYPE_NONE = 0, + MVPP2_TAG_TYPE_MH = 1, + MVPP2_TAG_TYPE_DSA = 2, + MVPP2_TAG_TYPE_EDSA = 3, + MVPP2_TAG_TYPE_VLAN = 4, + MVPP2_TAG_TYPE_LAST = 5 +}; + +/* Parser constants */ +#define MVPP2_PRS_TCAM_SRAM_SIZE 256 +#define MVPP2_PRS_TCAM_WORDS 6 +#define MVPP2_PRS_SRAM_WORDS 4 +#define MVPP2_PRS_FLOW_ID_SIZE 64 +#define MVPP2_PRS_FLOW_ID_MASK 0x3f +#define MVPP2_PRS_TCAM_ENTRY_INVALID 1 +#define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5) +#define MVPP2_PRS_IPV4_HEAD 0x40 +#define MVPP2_PRS_IPV4_HEAD_MASK 0xf0 +#define MVPP2_PRS_IPV4_MC 0xe0 +#define MVPP2_PRS_IPV4_MC_MASK 0xf0 +#define MVPP2_PRS_IPV4_BC_MASK 0xff +#define MVPP2_PRS_IPV4_IHL 0x5 +#define MVPP2_PRS_IPV4_IHL_MASK 0xf +#define MVPP2_PRS_IPV6_MC 0xff +#define MVPP2_PRS_IPV6_MC_MASK 0xff +#define MVPP2_PRS_IPV6_HOP_MASK 0xff +#define MVPP2_PRS_TCAM_PROTO_MASK 0xff +#define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f +#define MVPP2_PRS_DBL_VLANS_MAX 100 + +/* Tcam structure: + * - lookup ID - 4 bits + * - port ID - 1 byte + * - additional information - 1 byte + * - header data - 8 bytes + * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0). + */ +#define MVPP2_PRS_AI_BITS 8 +#define MVPP2_PRS_PORT_MASK 0xff +#define MVPP2_PRS_LU_MASK 0xf +#define MVPP2_PRS_TCAM_DATA_BYTE(offs) \ + (((offs) - ((offs) % 2)) * 2 + ((offs) % 2)) +#define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \ + (((offs) * 2) - ((offs) % 2) + 2) +#define MVPP2_PRS_TCAM_AI_BYTE 16 +#define MVPP2_PRS_TCAM_PORT_BYTE 17 +#define MVPP2_PRS_TCAM_LU_BYTE 20 +#define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2) +#define MVPP2_PRS_TCAM_INV_WORD 5 +/* Tcam entries ID */ +#define MVPP2_PE_DROP_ALL 0 +#define MVPP2_PE_FIRST_FREE_TID 1 +#define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31) +#define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30) +#define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29) +#define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28) +#define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27) +#define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26) +#define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19) +#define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18) +#define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17) +#define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16) +#define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15) +#define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14) +#define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13) +#define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12) +#define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11) +#define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10) +#define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9) +#define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8) +#define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7) +#define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6) +#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5) +#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4) +#define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3) +#define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2) +#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1) + +/* Sram structure + * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0). + */ +#define MVPP2_PRS_SRAM_RI_OFFS 0 +#define MVPP2_PRS_SRAM_RI_WORD 0 +#define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32 +#define MVPP2_PRS_SRAM_RI_CTRL_WORD 1 +#define MVPP2_PRS_SRAM_RI_CTRL_BITS 32 +#define MVPP2_PRS_SRAM_SHIFT_OFFS 64 +#define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72 +#define MVPP2_PRS_SRAM_UDF_OFFS 73 +#define MVPP2_PRS_SRAM_UDF_BITS 8 +#define MVPP2_PRS_SRAM_UDF_MASK 0xff +#define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81 +#define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82 +#define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7 +#define MVPP2_PRS_SRAM_UDF_TYPE_L3 1 +#define MVPP2_PRS_SRAM_UDF_TYPE_L4 4 +#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85 +#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3 +#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1 +#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2 +#define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3 +#define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87 +#define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2 +#define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3 +#define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0 +#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2 +#define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3 +#define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89 +#define MVPP2_PRS_SRAM_AI_OFFS 90 +#define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98 +#define MVPP2_PRS_SRAM_AI_CTRL_BITS 8 +#define MVPP2_PRS_SRAM_AI_MASK 0xff +#define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106 +#define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf +#define MVPP2_PRS_SRAM_LU_DONE_BIT 110 +#define MVPP2_PRS_SRAM_LU_GEN_BIT 111 + +/* Sram result info bits assignment */ +#define MVPP2_PRS_RI_MAC_ME_MASK 0x1 +#define MVPP2_PRS_RI_DSA_MASK 0x2 +#define MVPP2_PRS_RI_VLAN_MASK 0xc +#define MVPP2_PRS_RI_VLAN_NONE ~(BIT(2) | BIT(3)) +#define MVPP2_PRS_RI_VLAN_SINGLE BIT(2) +#define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3) +#define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3)) +#define MVPP2_PRS_RI_CPU_CODE_MASK 0x70 +#define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4) +#define MVPP2_PRS_RI_L2_CAST_MASK 0x600 +#define MVPP2_PRS_RI_L2_UCAST ~(BIT(9) | BIT(10)) +#define MVPP2_PRS_RI_L2_MCAST BIT(9) +#define MVPP2_PRS_RI_L2_BCAST BIT(10) +#define MVPP2_PRS_RI_PPPOE_MASK 0x800 +#define MVPP2_PRS_RI_L3_PROTO_MASK 0x7000 +#define MVPP2_PRS_RI_L3_UN ~(BIT(12) | BIT(13) | BIT(14)) +#define MVPP2_PRS_RI_L3_IP4 BIT(12) +#define MVPP2_PRS_RI_L3_IP4_OPT BIT(13) +#define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13)) +#define MVPP2_PRS_RI_L3_IP6 BIT(14) +#define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14)) +#define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14)) +#define MVPP2_PRS_RI_L3_ADDR_MASK 0x18000 +#define MVPP2_PRS_RI_L3_UCAST ~(BIT(15) | BIT(16)) +#define MVPP2_PRS_RI_L3_MCAST BIT(15) +#define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16)) +#define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000 +#define MVPP2_PRS_RI_UDF3_MASK 0x300000 +#define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21) +#define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000 +#define MVPP2_PRS_RI_L4_TCP BIT(22) +#define MVPP2_PRS_RI_L4_UDP BIT(23) +#define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23)) +#define MVPP2_PRS_RI_UDF7_MASK 0x60000000 +#define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29) +#define MVPP2_PRS_RI_DROP_MASK 0x80000000 + +/* Sram additional info bits assignment */ +#define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0) +#define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0) +#define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1) +#define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2) +#define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3) +#define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4) +#define MVPP2_PRS_SINGLE_VLAN_AI 0 +#define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7) + +/* DSA/EDSA type */ +#define MVPP2_PRS_TAGGED true +#define MVPP2_PRS_UNTAGGED false +#define MVPP2_PRS_EDSA true +#define MVPP2_PRS_DSA false + +/* MAC entries, shadow udf */ +enum mvpp2_prs_udf { + MVPP2_PRS_UDF_MAC_DEF, + MVPP2_PRS_UDF_MAC_RANGE, + MVPP2_PRS_UDF_L2_DEF, + MVPP2_PRS_UDF_L2_DEF_COPY, + MVPP2_PRS_UDF_L2_USER, +}; + +/* Lookup ID */ +enum mvpp2_prs_lookup { + MVPP2_PRS_LU_MH, + MVPP2_PRS_LU_MAC, + MVPP2_PRS_LU_DSA, + MVPP2_PRS_LU_VLAN, + MVPP2_PRS_LU_L2, + MVPP2_PRS_LU_PPPOE, + MVPP2_PRS_LU_IP4, + MVPP2_PRS_LU_IP6, + MVPP2_PRS_LU_FLOWS, + MVPP2_PRS_LU_LAST, +}; + +/* L3 cast enum */ +enum mvpp2_prs_l3_cast { + MVPP2_PRS_L3_UNI_CAST, + MVPP2_PRS_L3_MULTI_CAST, + MVPP2_PRS_L3_BROAD_CAST +}; + +/* Classifier constants */ +#define MVPP2_CLS_FLOWS_TBL_SIZE 512 +#define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3 +#define MVPP2_CLS_LKP_TBL_SIZE 64 + +/* BM constants */ +#define MVPP2_BM_POOLS_NUM 1 +#define MVPP2_BM_LONG_BUF_NUM 16 +#define MVPP2_BM_SHORT_BUF_NUM 16 +#define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) +#define MVPP2_BM_POOL_PTR_ALIGN 128 +#define MVPP2_BM_SWF_LONG_POOL(port) 0 + +/* BM cookie (32 bits) definition */ +#define MVPP2_BM_COOKIE_POOL_OFFS 8 +#define MVPP2_BM_COOKIE_CPU_OFFS 24 + +/* BM short pool packet size + * These value assure that for SWF the total number + * of bytes allocated for each buffer will be 512 + */ +#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512) + +enum mvpp2_bm_type { + MVPP2_BM_FREE, + MVPP2_BM_SWF_LONG, + MVPP2_BM_SWF_SHORT +}; + +/* Definitions */ + +/* Shared Packet Processor resources */ +struct mvpp2 { + /* Shared registers' base addresses */ + void __iomem *base; + void __iomem *lms_base; + + /* List of pointers to port structures */ + struct mvpp2_port **port_list; + + /* Aggregated TXQs */ + struct mvpp2_tx_queue *aggr_txqs; + + /* BM pools */ + struct mvpp2_bm_pool *bm_pools; + + /* PRS shadow table */ + struct mvpp2_prs_shadow *prs_shadow; + /* PRS auxiliary table for double vlan entries control */ + bool *prs_double_vlans; + + /* Tclk value */ + u32 tclk; + + struct mii_dev *bus; +}; + +struct mvpp2_pcpu_stats { + u64 rx_packets; + u64 rx_bytes; + u64 tx_packets; + u64 tx_bytes; +}; + +struct mvpp2_port { + u8 id; + + int irq; + + struct mvpp2 *priv; + + /* Per-port registers' base address */ + void __iomem *base; + + struct mvpp2_rx_queue **rxqs; + struct mvpp2_tx_queue **txqs; + + int pkt_size; + + u32 pending_cause_rx; + + /* Per-CPU port control */ + struct mvpp2_port_pcpu __percpu *pcpu; + + /* Flags */ + unsigned long flags; + + u16 tx_ring_size; + u16 rx_ring_size; + struct mvpp2_pcpu_stats __percpu *stats; + + struct phy_device *phy_dev; + phy_interface_t phy_interface; + int phy_node; + int phyaddr; + int init; + unsigned int link; + unsigned int duplex; + unsigned int speed; + + struct mvpp2_bm_pool *pool_long; + struct mvpp2_bm_pool *pool_short; + + /* Index of first port's physical RXQ */ + u8 first_rxq; + + u8 dev_addr[ETH_ALEN]; +}; + +/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the + * layout of the transmit and reception DMA descriptors, and their + * layout is therefore defined by the hardware design + */ + +#define MVPP2_TXD_L3_OFF_SHIFT 0 +#define MVPP2_TXD_IP_HLEN_SHIFT 8 +#define MVPP2_TXD_L4_CSUM_FRAG BIT(13) +#define MVPP2_TXD_L4_CSUM_NOT BIT(14) +#define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) +#define MVPP2_TXD_PADDING_DISABLE BIT(23) +#define MVPP2_TXD_L4_UDP BIT(24) +#define MVPP2_TXD_L3_IP6 BIT(26) +#define MVPP2_TXD_L_DESC BIT(28) +#define MVPP2_TXD_F_DESC BIT(29) + +#define MVPP2_RXD_ERR_SUMMARY BIT(15) +#define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) +#define MVPP2_RXD_ERR_CRC 0x0 +#define MVPP2_RXD_ERR_OVERRUN BIT(13) +#define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) +#define MVPP2_RXD_BM_POOL_ID_OFFS 16 +#define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) +#define MVPP2_RXD_HWF_SYNC BIT(21) +#define MVPP2_RXD_L4_CSUM_OK BIT(22) +#define MVPP2_RXD_IP4_HEADER_ERR BIT(24) +#define MVPP2_RXD_L4_TCP BIT(25) +#define MVPP2_RXD_L4_UDP BIT(26) +#define MVPP2_RXD_L3_IP4 BIT(28) +#define MVPP2_RXD_L3_IP6 BIT(30) +#define MVPP2_RXD_BUF_HDR BIT(31) + +struct mvpp2_tx_desc { + u32 command; /* Options used by HW for packet transmitting.*/ + u8 packet_offset; /* the offset from the buffer beginning */ + u8 phys_txq; /* destination queue ID */ + u16 data_size; /* data size of transmitted packet in bytes */ + u32 buf_phys_addr; /* physical addr of transmitted buffer */ + u32 buf_cookie; /* cookie for access to TX buffer in tx path */ + u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ + u32 reserved2; /* reserved (for future use) */ +}; + +struct mvpp2_rx_desc { + u32 status; /* info about received packet */ + u16 reserved1; /* parser_info (for future use, PnC) */ + u16 data_size; /* size of received packet in bytes */ + u32 buf_phys_addr; /* physical address of the buffer */ + u32 buf_cookie; /* cookie for access to RX buffer in rx path */ + u16 reserved2; /* gem_port_id (for future use, PON) */ + u16 reserved3; /* csum_l4 (for future use, PnC) */ + u8 reserved4; /* bm_qset (for future use, BM) */ + u8 reserved5; + u16 reserved6; /* classify_info (for future use, PnC) */ + u32 reserved7; /* flow_id (for future use, PnC) */ + u32 reserved8; +}; + +/* Per-CPU Tx queue control */ +struct mvpp2_txq_pcpu { + int cpu; + + /* Number of Tx DMA descriptors in the descriptor ring */ + int size; + + /* Number of currently used Tx DMA descriptor in the + * descriptor ring + */ + int count; + + /* Number of Tx DMA descriptors reserved for each CPU */ + int reserved_num; + + /* Index of last TX DMA descriptor that was inserted */ + int txq_put_index; + + /* Index of the TX DMA descriptor to be cleaned up */ + int txq_get_index; +}; + +struct mvpp2_tx_queue { + /* Physical number of this Tx queue */ + u8 id; + + /* Logical number of this Tx queue */ + u8 log_id; + + /* Number of Tx DMA descriptors in the descriptor ring */ + int size; + + /* Number of currently used Tx DMA descriptor in the descriptor ring */ + int count; + + /* Per-CPU control of physical Tx queues */ + struct mvpp2_txq_pcpu __percpu *pcpu; + + u32 done_pkts_coal; + + /* Virtual address of thex Tx DMA descriptors array */ + struct mvpp2_tx_desc *descs; + + /* DMA address of the Tx DMA descriptors array */ + dma_addr_t descs_phys; + + /* Index of the last Tx DMA descriptor */ + int last_desc; + + /* Index of the next Tx DMA descriptor to process */ + int next_desc_to_proc; +}; + +struct mvpp2_rx_queue { + /* RX queue number, in the range 0-31 for physical RXQs */ + u8 id; + + /* Num of rx descriptors in the rx descriptor ring */ + int size; + + u32 pkts_coal; + u32 time_coal; + + /* Virtual address of the RX DMA descriptors array */ + struct mvpp2_rx_desc *descs; + + /* DMA address of the RX DMA descriptors array */ + dma_addr_t descs_phys; + + /* Index of the last RX DMA descriptor */ + int last_desc; + + /* Index of the next RX DMA descriptor to process */ + int next_desc_to_proc; + + /* ID of port to which physical RXQ is mapped */ + int port; + + /* Port's logic RXQ number to which physical RXQ is mapped */ + int logic_rxq; +}; + +union mvpp2_prs_tcam_entry { + u32 word[MVPP2_PRS_TCAM_WORDS]; + u8 byte[MVPP2_PRS_TCAM_WORDS * 4]; +}; + +union mvpp2_prs_sram_entry { + u32 word[MVPP2_PRS_SRAM_WORDS]; + u8 byte[MVPP2_PRS_SRAM_WORDS * 4]; +}; + +struct mvpp2_prs_entry { + u32 index; + union mvpp2_prs_tcam_entry tcam; + union mvpp2_prs_sram_entry sram; +}; + +struct mvpp2_prs_shadow { + bool valid; + bool finish; + + /* Lookup ID */ + int lu; + + /* User defined offset */ + int udf; + + /* Result info */ + u32 ri; + u32 ri_mask; +}; + +struct mvpp2_cls_flow_entry { + u32 index; + u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS]; +}; + +struct mvpp2_cls_lookup_entry { + u32 lkpid; + u32 way; + u32 data; +}; + +struct mvpp2_bm_pool { + /* Pool number in the range 0-7 */ + int id; + enum mvpp2_bm_type type; + + /* Buffer Pointers Pool External (BPPE) size */ + int size; + /* Number of buffers for this pool */ + int buf_num; + /* Pool buffer size */ + int buf_size; + /* Packet size */ + int pkt_size; + + /* BPPE virtual base address */ + u32 *virt_addr; + /* BPPE physical base address */ + dma_addr_t phys_addr; + + /* Ports using BM pool */ + u32 port_map; + + /* Occupied buffers indicator */ + int in_use_thresh; +}; + +struct mvpp2_buff_hdr { + u32 next_buff_phys_addr; + u32 next_buff_virt_addr; + u16 byte_count; + u16 info; + u8 reserved1; /* bm_qset (for future use, BM) */ +}; + +/* Buffer header info bits */ +#define MVPP2_B_HDR_INFO_MC_ID_MASK 0xfff +#define MVPP2_B_HDR_INFO_MC_ID(info) ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK) +#define MVPP2_B_HDR_INFO_LAST_OFFS 12 +#define MVPP2_B_HDR_INFO_LAST_MASK BIT(12) +#define MVPP2_B_HDR_INFO_IS_LAST(info) \ + ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS) + +/* Static declaractions */ + +/* Number of RXQs used by single port */ +static int rxq_number = MVPP2_DEFAULT_RXQ; +/* Number of TXQs used by single port */ +static int txq_number = MVPP2_DEFAULT_TXQ; + +#define MVPP2_DRIVER_NAME "mvpp2" +#define MVPP2_DRIVER_VERSION "1.0" + +/* + * U-Boot internal data, mostly uncached buffers for descriptors and data + */ +struct buffer_location { + struct mvpp2_tx_desc *aggr_tx_descs; + struct mvpp2_tx_desc *tx_descs; + struct mvpp2_rx_desc *rx_descs; + u32 *bm_pool[MVPP2_BM_POOLS_NUM]; + u32 *rx_buffer[MVPP2_BM_LONG_BUF_NUM]; + int first_rxq; +}; + +/* + * All 4 interfaces use the same global buffer, since only one interface + * can be enabled at once + */ +static struct buffer_location buffer_loc; + +/* + * Page table entries are set to 1MB, or multiples of 1MB + * (not < 1MB). driver uses less bd's so use 1MB bdspace. + */ +#define BD_SPACE (1 << 20) + +/* Utility/helper methods */ + +static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) +{ + writel(data, priv->base + offset); +} + +static u32 mvpp2_read(struct mvpp2 *priv, u32 offset) +{ + return readl(priv->base + offset); +} + +static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) +{ + txq_pcpu->txq_get_index++; + if (txq_pcpu->txq_get_index == txq_pcpu->size) + txq_pcpu->txq_get_index = 0; +} + +/* Get number of physical egress port */ +static inline int mvpp2_egress_port(struct mvpp2_port *port) +{ + return MVPP2_MAX_TCONT + port->id; +} + +/* Get number of physical TXQ */ +static inline int mvpp2_txq_phys(int port, int txq) +{ + return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; +} + +/* Parser configuration routines */ + +/* Update parser tcam and sram hw entries */ +static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) +{ + int i; + + if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) + return -EINVAL; + + /* Clear entry invalidation bit */ + pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; + + /* Write tcam index - indirect access */ + mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); + for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) + mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]); + + /* Write sram index - indirect access */ + mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); + for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) + mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]); + + return 0; +} + +/* Read tcam entry from hw */ +static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) +{ + int i; + + if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) + return -EINVAL; + + /* Write tcam index - indirect access */ + mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); + + pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, + MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD)); + if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) + return MVPP2_PRS_TCAM_ENTRY_INVALID; + + for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) + pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); + + /* Write sram index - indirect access */ + mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); + for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) + pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); + + return 0; +} + +/* Invalidate tcam hw entry */ +static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index) +{ + /* Write index - indirect access */ + mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); + mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD), + MVPP2_PRS_TCAM_INV_MASK); +} + +/* Enable shadow table entry and set its lookup ID */ +static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu) +{ + priv->prs_shadow[index].valid = true; + priv->prs_shadow[index].lu = lu; +} + +/* Update ri fields in shadow table entry */ +static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index, + unsigned int ri, unsigned int ri_mask) +{ + priv->prs_shadow[index].ri_mask = ri_mask; + priv->prs_shadow[index].ri = ri; +} + +/* Update lookup field in tcam sw entry */ +static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) +{ + int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE); + + pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu; + pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK; +} + +/* Update mask for single port in tcam sw entry */ +static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, + unsigned int port, bool add) +{ + int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); + + if (add) + pe->tcam.byte[enable_off] &= ~(1 << port); + else + pe->tcam.byte[enable_off] |= 1 << port; +} + +/* Update port map in tcam sw entry */ +static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, + unsigned int ports) +{ + unsigned char port_mask = MVPP2_PRS_PORT_MASK; + int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); + + pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0; + pe->tcam.byte[enable_off] &= ~port_mask; + pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK; +} + +/* Obtain port map from tcam sw entry */ +static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) +{ + int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE); + + return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK; +} + +/* Set byte of data and its enable bits in tcam sw entry */ +static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, + unsigned int offs, unsigned char byte, + unsigned char enable) +{ + pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte; + pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable; +} + +/* Get byte of data and its enable bits from tcam sw entry */ +static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, + unsigned int offs, unsigned char *byte, + unsigned char *enable) +{ + *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)]; + *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)]; +} + +/* Set ethertype in tcam sw entry */ +static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, + unsigned short ethertype) +{ + mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); + mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); +} + +/* Set bits in sram sw entry */ +static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, + int val) +{ + pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8)); +} + +/* Clear bits in sram sw entry */ +static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, + int val) +{ + pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8)); +} + +/* Update ri bits in sram sw entry */ +static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, + unsigned int bits, unsigned int mask) +{ + unsigned int i; + + for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) { + int ri_off = MVPP2_PRS_SRAM_RI_OFFS; + + if (!(mask & BIT(i))) + continue; + + if (bits & BIT(i)) + mvpp2_prs_sram_bits_set(pe, ri_off + i, 1); + else + mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1); + + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); + } +} + +/* Update ai bits in sram sw entry */ +static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, + unsigned int bits, unsigned int mask) +{ + unsigned int i; + int ai_off = MVPP2_PRS_SRAM_AI_OFFS; + + for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) { + + if (!(mask & BIT(i))) + continue; + + if (bits & BIT(i)) + mvpp2_prs_sram_bits_set(pe, ai_off + i, 1); + else + mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1); + + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); + } +} + +/* Read ai bits from sram sw entry */ +static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) +{ + u8 bits; + int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS); + int ai_en_off = ai_off + 1; + int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8; + + bits = (pe->sram.byte[ai_off] >> ai_shift) | + (pe->sram.byte[ai_en_off] << (8 - ai_shift)); + + return bits; +} + +/* In sram sw entry set lookup ID field of the tcam key to be used in the next + * lookup interation + */ +static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, + unsigned int lu) +{ + int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS; + + mvpp2_prs_sram_bits_clear(pe, sram_next_off, + MVPP2_PRS_SRAM_NEXT_LU_MASK); + mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); +} + +/* In the sram sw entry set sign and value of the next lookup offset + * and the offset value generated to the classifier + */ +static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, + unsigned int op) +{ + /* Set sign */ + if (shift < 0) { + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); + shift = 0 - shift; + } else { + mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); + } + + /* Set value */ + pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] = + (unsigned char)shift; + + /* Reset and set operation */ + mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, + MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK); + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); + + /* Set base offset as current */ + mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); +} + +/* In the sram sw entry set sign and value of the user defined offset + * generated to the classifier + */ +static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, + unsigned int type, int offset, + unsigned int op) +{ + /* Set sign */ + if (offset < 0) { + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); + offset = 0 - offset; + } else { + mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); + } + + /* Set value */ + mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, + MVPP2_PRS_SRAM_UDF_MASK); + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset); + pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + + MVPP2_PRS_SRAM_UDF_BITS)] &= + ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); + pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS + + MVPP2_PRS_SRAM_UDF_BITS)] |= + (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8))); + + /* Set offset type */ + mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, + MVPP2_PRS_SRAM_UDF_TYPE_MASK); + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); + + /* Set offset operation */ + mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, + MVPP2_PRS_SRAM_OP_SEL_UDF_MASK); + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op); + + pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + + MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &= + ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >> + (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); + + pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS + + MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |= + (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8))); + + /* Set base offset as current */ + mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); +} + +/* Find parser flow entry */ +static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow) +{ + struct mvpp2_prs_entry *pe; + int tid; + + pe = kzalloc(sizeof(*pe), GFP_KERNEL); + if (!pe) + return NULL; + mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); + + /* Go through the all entires with MVPP2_PRS_LU_FLOWS */ + for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) { + u8 bits; + + if (!priv->prs_shadow[tid].valid || + priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS) + continue; + + pe->index = tid; + mvpp2_prs_hw_read(priv, pe); + bits = mvpp2_prs_sram_ai_get(pe); + + /* Sram store classification lookup ID in AI bits [5:0] */ + if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow) + return pe; + } + kfree(pe); + + return NULL; +} + +/* Return first free tcam index, seeking from start to end */ +static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start, + unsigned char end) +{ + int tid; + + if (start > end) + swap(start, end); + + if (end >= MVPP2_PRS_TCAM_SRAM_SIZE) + end = MVPP2_PRS_TCAM_SRAM_SIZE - 1; + + for (tid = start; tid <= end; tid++) { + if (!priv->prs_shadow[tid].valid) + return tid; + } + + return -EINVAL; +} + +/* Enable/disable dropping all mac da's */ +static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add) +{ + struct mvpp2_prs_entry pe; + + if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) { + /* Entry exist - update port only */ + pe.index = MVPP2_PE_DROP_ALL; + mvpp2_prs_hw_read(priv, &pe); + } else { + /* Entry doesn't exist - create new */ + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); + pe.index = MVPP2_PE_DROP_ALL; + + /* Non-promiscuous mode for all ports - DROP unknown packets */ + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, + MVPP2_PRS_RI_DROP_MASK); + + mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); + + /* Update shadow table */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); + + /* Mask all ports */ + mvpp2_prs_tcam_port_map_set(&pe, 0); + } + + /* Update port mask */ + mvpp2_prs_tcam_port_set(&pe, port, add); + + mvpp2_prs_hw_write(priv, &pe); +} + +/* Set port to promiscuous mode */ +static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add) +{ + struct mvpp2_prs_entry pe; + + /* Promiscuous mode - Accept unknown packets */ + + if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) { + /* Entry exist - update port only */ + pe.index = MVPP2_PE_MAC_PROMISCUOUS; + mvpp2_prs_hw_read(priv, &pe); + } else { + /* Entry doesn't exist - create new */ + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); + pe.index = MVPP2_PE_MAC_PROMISCUOUS; + + /* Continue - set next lookup */ + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); + + /* Set result info bits */ + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST, + MVPP2_PRS_RI_L2_CAST_MASK); + + /* Shift to ethertype */ + mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, + MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); + + /* Mask all ports */ + mvpp2_prs_tcam_port_map_set(&pe, 0); + + /* Update shadow table */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); + } + + /* Update port mask */ + mvpp2_prs_tcam_port_set(&pe, port, add); + + mvpp2_prs_hw_write(priv, &pe); +} + +/* Accept multicast */ +static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index, + bool add) +{ + struct mvpp2_prs_entry pe; + unsigned char da_mc; + + /* Ethernet multicast address first byte is + * 0x01 for IPv4 and 0x33 for IPv6 + */ + da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33; + + if (priv->prs_shadow[index].valid) { + /* Entry exist - update port only */ + pe.index = index; + mvpp2_prs_hw_read(priv, &pe); + } else { + /* Entry doesn't exist - create new */ + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); + pe.index = index; + + /* Continue - set next lookup */ + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); + + /* Set result info bits */ + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST, + MVPP2_PRS_RI_L2_CAST_MASK); + + /* Update tcam entry data first byte */ + mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff); + + /* Shift to ethertype */ + mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, + MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); + + /* Mask all ports */ + mvpp2_prs_tcam_port_map_set(&pe, 0); + + /* Update shadow table */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); + } + + /* Update port mask */ + mvpp2_prs_tcam_port_set(&pe, port, add); + + mvpp2_prs_hw_write(priv, &pe); +} + +/* Parser per-port initialization */ +static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first, + int lu_max, int offset) +{ + u32 val; + + /* Set lookup ID */ + val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG); + val &= ~MVPP2_PRS_PORT_LU_MASK(port); + val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first); + mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val); + + /* Set maximum number of loops for packet received from port */ + val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port)); + val &= ~MVPP2_PRS_MAX_LOOP_MASK(port); + val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max); + mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val); + + /* Set initial offset for packet header extraction for the first + * searching loop + */ + val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port)); + val &= ~MVPP2_PRS_INIT_OFF_MASK(port); + val |= MVPP2_PRS_INIT_OFF_VAL(port, offset); + mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val); +} + +/* Default flow entries initialization for all ports */ +static void mvpp2_prs_def_flow_init(struct mvpp2 *priv) +{ + struct mvpp2_prs_entry pe; + int port; + + for (port = 0; port < MVPP2_MAX_PORTS; port++) { + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); + pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; + + /* Mask all ports */ + mvpp2_prs_tcam_port_map_set(&pe, 0); + + /* Set flow ID*/ + mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); + mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); + mvpp2_prs_hw_write(priv, &pe); + } +} + +/* Set default entry for Marvell Header field */ +static void mvpp2_prs_mh_init(struct mvpp2 *priv) +{ + struct mvpp2_prs_entry pe; + + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + + pe.index = MVPP2_PE_MH_DEFAULT; + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); + mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, + MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); + + /* Unmask all ports */ + mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); + mvpp2_prs_hw_write(priv, &pe); +} + +/* Set default entires (place holder) for promiscuous, non-promiscuous and + * multicast MAC addresses + */ +static void mvpp2_prs_mac_init(struct mvpp2 *priv) +{ + struct mvpp2_prs_entry pe; + + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + + /* Non-promiscuous mode for all ports - DROP unknown packets */ + pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); + + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, + MVPP2_PRS_RI_DROP_MASK); + mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); + + /* Unmask all ports */ + mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); + mvpp2_prs_hw_write(priv, &pe); + + /* place holders only - no ports */ + mvpp2_prs_mac_drop_all_set(priv, 0, false); + mvpp2_prs_mac_promisc_set(priv, 0, false); + mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false); + mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false); +} + +/* Match basic ethertypes */ +static int mvpp2_prs_etype_init(struct mvpp2 *priv) +{ + struct mvpp2_prs_entry pe; + int tid; + + /* Ethertype: PPPoE */ + tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, + MVPP2_PE_LAST_FREE_TID); + if (tid < 0) + return tid; + + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); + pe.index = tid; + + mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES); + + mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, + MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, + MVPP2_PRS_RI_PPPOE_MASK); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); + priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; + priv->prs_shadow[pe.index].finish = false; + mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, + MVPP2_PRS_RI_PPPOE_MASK); + mvpp2_prs_hw_write(priv, &pe); + + /* Ethertype: ARP */ + tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, + MVPP2_PE_LAST_FREE_TID); + if (tid < 0) + return tid; + + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); + pe.index = tid; + + mvpp2_prs_match_etype(&pe, 0, PROT_ARP); + + /* Generate flow in the next iteration*/ + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); + mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, + MVPP2_PRS_RI_L3_PROTO_MASK); + /* Set L3 offset */ + mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, + MVPP2_ETH_TYPE_LEN, + MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); + priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; + priv->prs_shadow[pe.index].finish = true; + mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, + MVPP2_PRS_RI_L3_PROTO_MASK); + mvpp2_prs_hw_write(priv, &pe); + + /* Ethertype: LBTD */ + tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, + MVPP2_PE_LAST_FREE_TID); + if (tid < 0) + return tid; + + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); + pe.index = tid; + + mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); + + /* Generate flow in the next iteration*/ + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); + mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | + MVPP2_PRS_RI_UDF3_RX_SPECIAL, + MVPP2_PRS_RI_CPU_CODE_MASK | + MVPP2_PRS_RI_UDF3_MASK); + /* Set L3 offset */ + mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, + MVPP2_ETH_TYPE_LEN, + MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); + priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; + priv->prs_shadow[pe.index].finish = true; + mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | + MVPP2_PRS_RI_UDF3_RX_SPECIAL, + MVPP2_PRS_RI_CPU_CODE_MASK | + MVPP2_PRS_RI_UDF3_MASK); + mvpp2_prs_hw_write(priv, &pe); + + /* Ethertype: IPv4 without options */ + tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, + MVPP2_PE_LAST_FREE_TID); + if (tid < 0) + return tid; + + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); + pe.index = tid; + + mvpp2_prs_match_etype(&pe, 0, PROT_IP); + mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, + MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL, + MVPP2_PRS_IPV4_HEAD_MASK | + MVPP2_PRS_IPV4_IHL_MASK); + + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, + MVPP2_PRS_RI_L3_PROTO_MASK); + /* Skip eth_type + 4 bytes of IP header */ + mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4, + MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); + /* Set L3 offset */ + mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, + MVPP2_ETH_TYPE_LEN, + MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); + priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; + priv->prs_shadow[pe.index].finish = false; + mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, + MVPP2_PRS_RI_L3_PROTO_MASK); + mvpp2_prs_hw_write(priv, &pe); + + /* Ethertype: IPv4 with options */ + tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, + MVPP2_PE_LAST_FREE_TID); + if (tid < 0) + return tid; + + pe.index = tid; + + /* Clear tcam data before updating */ + pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0; + pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0; + + mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, + MVPP2_PRS_IPV4_HEAD, + MVPP2_PRS_IPV4_HEAD_MASK); + + /* Clear ri before updating */ + pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0; + pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, + MVPP2_PRS_RI_L3_PROTO_MASK); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); + priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; + priv->prs_shadow[pe.index].finish = false; + mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT, + MVPP2_PRS_RI_L3_PROTO_MASK); + mvpp2_prs_hw_write(priv, &pe); + + /* Ethertype: IPv6 without options */ + tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, + MVPP2_PE_LAST_FREE_TID); + if (tid < 0) + return tid; + + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); + pe.index = tid; + + mvpp2_prs_match_etype(&pe, 0, PROT_IPV6); + + /* Skip DIP of IPV6 header */ + mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + + MVPP2_MAX_L3_ADDR_SIZE, + MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, + MVPP2_PRS_RI_L3_PROTO_MASK); + /* Set L3 offset */ + mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, + MVPP2_ETH_TYPE_LEN, + MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); + + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); + priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; + priv->prs_shadow[pe.index].finish = false; + mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, + MVPP2_PRS_RI_L3_PROTO_MASK); + mvpp2_prs_hw_write(priv, &pe); + + /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */ + memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); + mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); + pe.index = MVPP2_PE_ETH_TYPE_UN; + + /* Unmask all ports */ + mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); + + /* Generate flow in the next iteration*/ + mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); + mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); + mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, + MVPP2_PRS_RI_L3_PROTO_MASK); + /* Set L3 offset even it's unknown L3 */ + mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, + MVPP2_ETH_TYPE_LEN, + MVPP2_PRS_SRAM_OP_SEL_UDF_ADD); + + /* Update shadow table and hw entry */ + mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); + priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; + priv->prs_shadow[pe.index].finish = true; + mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, + MVPP2_PRS_RI_L3_PROTO_MASK); + mvpp2_prs_hw_write(priv, &pe); + + return 0; +} + +/* Parser default initialization */ +static int mvpp2_prs_default_init(struct udevice *dev, + struct mvpp2 *priv) +{ + int err, index, i; + + /* Enable tcam table */ + mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK); + + /* Clear all tcam and sram entries */ + for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) { + mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index); + for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++) + mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0); + + mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index); + for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++) + mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0); + } + + /* Invalidate all tcam entries */ + for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) + mvpp2_prs_hw_inv(priv, index); + + priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE, + sizeof(struct mvpp2_prs_shadow), + GFP_KERNEL); + if (!priv->prs_shadow) + return -ENOMEM; + + /* Always start from lookup = 0 */ + for (index = 0; index < MVPP2_MAX_PORTS; index++) + mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH, + MVPP2_PRS_PORT_LU_MAX, 0); + + mvpp2_prs_def_flow_init(priv); + + mvpp2_prs_mh_init(priv); + + mvpp2_prs_mac_init(priv); + + err = mvpp2_prs_etype_init(priv); + if (err) + return err; + + return 0; +} + +/* Compare MAC DA with tcam entry data */ +static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, + const u8 *da, unsigned char *mask) +{ + unsigned char tcam_byte, tcam_mask; + int index; + + for (index = 0; index < ETH_ALEN; index++) { + mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); + if (tcam_mask != mask[index]) + return false; + + if ((tcam_mask & tcam_byte) != (da[index] & mask[index])) + return false; + } + + return true; +} + +/* Find tcam entry with matched pair <MAC DA, port> */ +static struct mvpp2_prs_entry * +mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da, + unsigned char *mask, int udf_type) +{ + struct mvpp2_prs_entry *pe; + int tid; + + pe = kzalloc(sizeof(*pe), GFP_KERNEL); + if (!pe) + return NULL; + mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); + + /* Go through the all entires with MVPP2_PRS_LU_MAC */ + for (tid = MVPP2_PE_FIRST_FREE_TID; + tid <= MVPP2_PE_LAST_FREE_TID; tid++) { + unsigned int entry_pmap; + + if (!priv->prs_shadow[tid].valid || + (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) || + (priv->prs_shadow[tid].udf != udf_type)) + continue; + + pe->index = tid; + mvpp2_prs_hw_read(priv, pe); + entry_pmap = mvpp2_prs_tcam_port_map_get(pe); + + if (mvpp2_prs_mac_range_equals(pe, da, mask) && + entry_pmap == pmap) + return pe; + } + kfree(pe); + + return NULL; +} + +/* Update parser's mac da entry */ +static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port, + const u8 *da, bool add) +{ + struct mvpp2_prs_entry *pe; + unsigned int pmap, len, ri; + unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + int tid; + + /* Scan TCAM and see if entry with this <MAC DA, port> already exist */ + pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask, + MVPP2_PRS_UDF_MAC_DEF); + + /* No such entry */ + if (!pe) { + if (!add) + return 0; + + /* Create new TCAM entry */ + /* Find first range mac entry*/ + for (tid = MVPP2_PE_FIRST_FREE_TID; + tid <= MVPP2_PE_LAST_FREE_TID; tid++) + if (priv->prs_shadow[tid].valid && + (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) && + (priv->prs_shadow[tid].udf == + MVPP2_PRS_UDF_MAC_RANGE)) + break; + + /* Go through the all entries from first to last */ + tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID, + tid - 1); + if (tid < 0) + return tid; + + pe = kzalloc(sizeof(*pe), GFP_KERNEL); + if (!pe) + return -1; + mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC); + pe->index = tid; + + /* Mask all ports */ + mvpp2_prs_tcam_port_map_set(pe, 0); + } + + /* Update port mask */ + mvpp2_prs_tcam_port_set(pe, port, add); + + /* Invalidate the entry if no ports are left enabled */ + pmap = mvpp2_prs_tcam_port_map_get(pe); + if (pmap == 0) { + if (add) { + kfree(pe); + return -1; + } + mvpp2_prs_hw_inv(priv, pe->index); + priv->prs_shadow[pe->index].valid = false; + kfree(pe); + return 0; + } + + /* Continue - set next lookup */ + mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA); + + /* Set match on DA */ + len = ETH_ALEN; + while (len--) + mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff); + + /* Set result info bits */ + ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK; + + mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | + MVPP2_PRS_RI_MAC_ME_MASK); + mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK | + MVPP2_PRS_RI_MAC_ME_MASK); + + /* Shift to ethertype */ + mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN, + MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); + + /* Update shadow table and hw entry */ + priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF; + mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC); + mvpp2_prs_hw_write(priv, pe); + + kfree(pe); + + return 0; +} + +static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da) +{ + int err; + + /* Remove old parser entry */ + err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr, + false); + if (err) + return err; + + /* Add new parser entry */ + err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true); + if (err) + return err; + + /* Set addr in the device */ + memcpy(port->dev_addr, da, ETH_ALEN); + + return 0; +} + +/* Set prs flow for the port */ +static int mvpp2_prs_def_flow(struct mvpp2_port *port) +{ + struct mvpp2_prs_entry *pe; + int tid; + + pe = mvpp2_prs_flow_find(port->priv, port->id); + + /* Such entry not exist */ + if (!pe) { + /* Go through the all entires from last to first */ + tid = mvpp2_prs_tcam_first_free(port->priv, + MVPP2_PE_LAST_FREE_TID, + MVPP2_PE_FIRST_FREE_TID); + if (tid < 0) + return tid; + + pe = kzalloc(sizeof(*pe), GFP_KERNEL); + if (!pe) + return -ENOMEM; + + mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS); + pe->index = tid; + + /* Set flow ID*/ + mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK); + mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); + + /* Update shadow table */ + mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS); + } + + mvpp2_prs_tcam_port_map_set(pe, (1 << port->id)); + mvpp2_prs_hw_write(port->priv, pe); + kfree(pe); + + return 0; +} + +/* Classifier configuration routines */ + +/* Update classification flow table registers */ +static void mvpp2_cls_flow_write(struct mvpp2 *priv, + struct mvpp2_cls_flow_entry *fe) +{ + mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index); + mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]); + mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]); + mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]); +} + +/* Update classification lookup table register */ +static void mvpp2_cls_lookup_write(struct mvpp2 *priv, + struct mvpp2_cls_lookup_entry *le) +{ + u32 val; + + val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; + mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val); + mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data); +} + +/* Classifier default initialization */ +static void mvpp2_cls_init(struct mvpp2 *priv) +{ + struct mvpp2_cls_lookup_entry le; + struct mvpp2_cls_flow_entry fe; + int index; + + /* Enable classifier */ + mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK); + + /* Clear classifier flow table */ + memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS); + for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) { + fe.index = index; + mvpp2_cls_flow_write(priv, &fe); + } + + /* Clear classifier lookup table */ + le.data = 0; + for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) { + le.lkpid = index; + le.way = 0; + mvpp2_cls_lookup_write(priv, &le); + + le.way = 1; + mvpp2_cls_lookup_write(priv, &le); + } +} + +static void mvpp2_cls_port_config(struct mvpp2_port *port) +{ + struct mvpp2_cls_lookup_entry le; + u32 val; + + /* Set way for the port */ + val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG); + val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id); + mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val); + + /* Pick the entry to be accessed in lookup ID decoding table + * according to the way and lkpid. + */ + le.lkpid = port->id; + le.way = 0; + le.data = 0; + + /* Set initial CPU queue for receiving packets */ + le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK; + le.data |= port->first_rxq; + + /* Disable classification engines */ + le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK; + + /* Update lookup ID table entry */ + mvpp2_cls_lookup_write(port->priv, &le); +} + +/* Set CPU queue number for oversize packets */ +static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port) +{ + u32 val; + + mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id), + port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK); + + mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id), + (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS)); + + val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG); + val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id); + mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val); +} + +/* Buffer Manager configuration routines */ + +/* Create pool */ +static int mvpp2_bm_pool_create(struct udevice *dev, + struct mvpp2 *priv, + struct mvpp2_bm_pool *bm_pool, int size) +{ + u32 val; + + bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id]; + bm_pool->phys_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id]; + if (!bm_pool->virt_addr) + return -ENOMEM; + + if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVPP2_BM_POOL_PTR_ALIGN)) { + dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", + bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); + return -ENOMEM; + } + + mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), + bm_pool->phys_addr); + mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); + + val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); + val |= MVPP2_BM_START_MASK; + mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); + + bm_pool->type = MVPP2_BM_FREE; + bm_pool->size = size; + bm_pool->pkt_size = 0; + bm_pool->buf_num = 0; + + return 0; +} + +/* Set pool buffer size */ +static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, + struct mvpp2_bm_pool *bm_pool, + int buf_size) +{ + u32 val; + + bm_pool->buf_size = buf_size; + + val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); + mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); +} + +/* Free all buffers from the pool */ +static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv, + struct mvpp2_bm_pool *bm_pool) +{ + bm_pool->buf_num = 0; +} + +/* Cleanup pool */ +static int mvpp2_bm_pool_destroy(struct udevice *dev, + struct mvpp2 *priv, + struct mvpp2_bm_pool *bm_pool) +{ + u32 val; + + mvpp2_bm_bufs_free(dev, priv, bm_pool); + if (bm_pool->buf_num) { + dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id); + return 0; + } + + val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); + val |= MVPP2_BM_STOP_MASK; + mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); + + return 0; +} + +static int mvpp2_bm_pools_init(struct udevice *dev, + struct mvpp2 *priv) +{ + int i, err, size; + struct mvpp2_bm_pool *bm_pool; + + /* Create all pools with maximum size */ + size = MVPP2_BM_POOL_SIZE_MAX; + for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { + bm_pool = &priv->bm_pools[i]; + bm_pool->id = i; + err = mvpp2_bm_pool_create(dev, priv, bm_pool, size); + if (err) + goto err_unroll_pools; + mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); + } + return 0; + +err_unroll_pools: + dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); + for (i = i - 1; i >= 0; i--) + mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); + return err; +} + +static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv) +{ + int i, err; + + for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { + /* Mask BM all interrupts */ + mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); + /* Clear BM cause register */ + mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); + } + + /* Allocate and initialize BM pools */ + priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM, + sizeof(struct mvpp2_bm_pool), GFP_KERNEL); + if (!priv->bm_pools) + return -ENOMEM; + + err = mvpp2_bm_pools_init(dev, priv); + if (err < 0) + return err; + return 0; +} + +/* Attach long pool to rxq */ +static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, + int lrxq, int long_pool) +{ + u32 val; + int prxq; + + /* Get queue physical ID */ + prxq = port->rxqs[lrxq]->id; + + val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); + val &= ~MVPP2_RXQ_POOL_LONG_MASK; + val |= ((long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & + MVPP2_RXQ_POOL_LONG_MASK); + + mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); +} + +/* Set pool number in a BM cookie */ +static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool) +{ + u32 bm; + + bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS); + bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS); + + return bm; +} + +/* Get pool number from a BM cookie */ +static inline int mvpp2_bm_cookie_pool_get(u32 cookie) +{ + return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF; +} + +/* Release buffer to BM */ +static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, + u32 buf_phys_addr, u32 buf_virt_addr) +{ + mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_virt_addr); + mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_phys_addr); +} + +/* Refill BM pool */ +static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm, + u32 phys_addr, u32 cookie) +{ + int pool = mvpp2_bm_cookie_pool_get(bm); + + mvpp2_bm_pool_put(port, pool, phys_addr, cookie); +} + +/* Allocate buffers for the pool */ +static int mvpp2_bm_bufs_add(struct mvpp2_port *port, + struct mvpp2_bm_pool *bm_pool, int buf_num) +{ + int i; + u32 bm; + + if (buf_num < 0 || + (buf_num + bm_pool->buf_num > bm_pool->size)) { + netdev_err(port->dev, + "cannot allocate %d buffers for pool %d\n", + buf_num, bm_pool->id); + return 0; + } + + bm = mvpp2_bm_cookie_pool_set(0, bm_pool->id); + for (i = 0; i < buf_num; i++) { + mvpp2_pool_refill(port, bm, (u32)buffer_loc.rx_buffer[i], + (u32)buffer_loc.rx_buffer[i]); + } + + /* Update BM driver with number of buffers added to pool */ + bm_pool->buf_num += i; + bm_pool->in_use_thresh = bm_pool->buf_num / 4; + + return i; +} + +/* Notify the driver that BM pool is being used as specific type and return the + * pool pointer on success + */ +static struct mvpp2_bm_pool * +mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type, + int pkt_size) +{ + struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; + int num; + + if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) { + netdev_err(port->dev, "mixing pool types is forbidden\n"); + return NULL; + } + + if (new_pool->type == MVPP2_BM_FREE) + new_pool->type = type; + + /* Allocate buffers in case BM pool is used as long pool, but packet + * size doesn't match MTU or BM pool hasn't being used yet + */ + if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) || + (new_pool->pkt_size == 0)) { + int pkts_num; + + /* Set default buffer number or free all the buffers in case + * the pool is not empty + */ + pkts_num = new_pool->buf_num; + if (pkts_num == 0) + pkts_num = type == MVPP2_BM_SWF_LONG ? + MVPP2_BM_LONG_BUF_NUM : + MVPP2_BM_SHORT_BUF_NUM; + else + mvpp2_bm_bufs_free(NULL, + port->priv, new_pool); + + new_pool->pkt_size = pkt_size; + + /* Allocate buffers for this pool */ + num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); + if (num != pkts_num) { + dev_err(dev, "pool %d: %d of %d allocated\n", + new_pool->id, num, pkts_num); + return NULL; + } + } + + mvpp2_bm_pool_bufsize_set(port->priv, new_pool, + MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); + + return new_pool; +} + +/* Initialize pools for swf */ +static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) +{ + int rxq; + + if (!port->pool_long) { + port->pool_long = + mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id), + MVPP2_BM_SWF_LONG, + port->pkt_size); + if (!port->pool_long) + return -ENOMEM; + + port->pool_long->port_map |= (1 << port->id); + + for (rxq = 0; rxq < rxq_number; rxq++) + mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); + } + + return 0; +} + +/* Port configuration routines */ + +static void mvpp2_port_mii_set(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG); + + switch (port->phy_interface) { + case PHY_INTERFACE_MODE_SGMII: + val |= MVPP2_GMAC_INBAND_AN_MASK; + break; + case PHY_INTERFACE_MODE_RGMII: + val |= MVPP2_GMAC_PORT_RGMII_MASK; + default: + val &= ~MVPP2_GMAC_PCS_ENABLE_MASK; + } + + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); +} + +static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val |= MVPP2_GMAC_FC_ADV_EN; + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); +} + +static void mvpp2_port_enable(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + val |= MVPP2_GMAC_PORT_EN_MASK; + val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); +} + +static void mvpp2_port_disable(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + val &= ~(MVPP2_GMAC_PORT_EN_MASK); + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); +} + +/* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ +static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & + ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); +} + +/* Configure loopback port */ +static void mvpp2_port_loopback_set(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); + + if (port->speed == 1000) + val |= MVPP2_GMAC_GMII_LB_EN_MASK; + else + val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; + + if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) + val |= MVPP2_GMAC_PCS_LB_EN_MASK; + else + val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; + + writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); +} + +static void mvpp2_port_reset(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) & + ~MVPP2_GMAC_PORT_RESET_MASK; + writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); + + while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & + MVPP2_GMAC_PORT_RESET_MASK) + continue; +} + +/* Change maximum receive size of the port */ +static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) +{ + u32 val; + + val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); + val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; + val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << + MVPP2_GMAC_MAX_RX_SIZE_OFFS); + writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); +} + +/* Set defaults to the MVPP2 port */ +static void mvpp2_defaults_set(struct mvpp2_port *port) +{ + int tx_port_num, val, queue, ptxq, lrxq; + + /* Configure port to loopback if needed */ + if (port->flags & MVPP2_F_LOOPBACK) + mvpp2_port_loopback_set(port); + + /* Update TX FIFO MIN Threshold */ + val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; + /* Min. TX threshold must be less than minimal packet length */ + val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); + writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); + + /* Disable Legacy WRR, Disable EJP, Release from reset */ + tx_port_num = mvpp2_egress_port(port); + mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, + tx_port_num); + mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); + + /* Close bandwidth for all queues */ + for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) { + ptxq = mvpp2_txq_phys(port->id, queue); + mvpp2_write(port->priv, + MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0); + } + + /* Set refill period to 1 usec, refill tokens + * and bucket size to maximum + */ + mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8); + val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); + val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; + val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); + val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; + mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); + val = MVPP2_TXP_TOKEN_SIZE_MAX; + mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); + + /* Set MaximumLowLatencyPacketSize value to 256 */ + mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), + MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | + MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); + + /* Enable Rx cache snoop */ + for (lrxq = 0; lrxq < rxq_number; lrxq++) { + queue = port->rxqs[lrxq]->id; + val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); + val |= MVPP2_SNOOP_PKT_SIZE_MASK | + MVPP2_SNOOP_BUF_HDR_MASK; + mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); + } +} + +/* Enable/disable receiving packets */ +static void mvpp2_ingress_enable(struct mvpp2_port *port) +{ + u32 val; + int lrxq, queue; + + for (lrxq = 0; lrxq < rxq_number; lrxq++) { + queue = port->rxqs[lrxq]->id; + val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); + val &= ~MVPP2_RXQ_DISABLE_MASK; + mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); + } +} + +static void mvpp2_ingress_disable(struct mvpp2_port *port) +{ + u32 val; + int lrxq, queue; + + for (lrxq = 0; lrxq < rxq_number; lrxq++) { + queue = port->rxqs[lrxq]->id; + val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); + val |= MVPP2_RXQ_DISABLE_MASK; + mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); + } +} + +/* Enable transmit via physical egress queue + * - HW starts take descriptors from DRAM + */ +static void mvpp2_egress_enable(struct mvpp2_port *port) +{ + u32 qmap; + int queue; + int tx_port_num = mvpp2_egress_port(port); + + /* Enable all initialized TXs. */ + qmap = 0; + for (queue = 0; queue < txq_number; queue++) { + struct mvpp2_tx_queue *txq = port->txqs[queue]; + + if (txq->descs != NULL) + qmap |= (1 << queue); + } + + mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); + mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); +} + +/* Disable transmit via physical egress queue + * - HW doesn't take descriptors from DRAM + */ +static void mvpp2_egress_disable(struct mvpp2_port *port) +{ + u32 reg_data; + int delay; + int tx_port_num = mvpp2_egress_port(port); + + /* Issue stop command for active channels only */ + mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); + reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & + MVPP2_TXP_SCHED_ENQ_MASK; + if (reg_data != 0) + mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, + (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); + + /* Wait for all Tx activity to terminate. */ + delay = 0; + do { + if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { + netdev_warn(port->dev, + "Tx stop timed out, status=0x%08x\n", + reg_data); + break; + } + mdelay(1); + delay++; + + /* Check port TX Command register that all + * Tx queues are stopped + */ + reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); + } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); +} + +/* Rx descriptors helper methods */ + +/* Get number of Rx descriptors occupied by received packets */ +static inline int +mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) +{ + u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); + + return val & MVPP2_RXQ_OCCUPIED_MASK; +} + +/* Update Rx queue status with the number of occupied and available + * Rx descriptor slots. + */ +static inline void +mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, + int used_count, int free_count) +{ + /* Decrement the number of used descriptors and increment count + * increment the number of free descriptors. + */ + u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); + + mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); +} + +/* Get pointer to next RX descriptor to be processed by SW */ +static inline struct mvpp2_rx_desc * +mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) +{ + int rx_desc = rxq->next_desc_to_proc; + + rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); + prefetch(rxq->descs + rxq->next_desc_to_proc); + return rxq->descs + rx_desc; +} + +/* Set rx queue offset */ +static void mvpp2_rxq_offset_set(struct mvpp2_port *port, + int prxq, int offset) +{ + u32 val; + + /* Convert offset from bytes to units of 32 bytes */ + offset = offset >> 5; + + val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); + val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; + + /* Offset is in */ + val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & + MVPP2_RXQ_PACKET_OFFSET_MASK); + + mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); +} + +/* Obtain BM cookie information from descriptor */ +static u32 mvpp2_bm_cookie_build(struct mvpp2_rx_desc *rx_desc) +{ + int pool = (rx_desc->status & MVPP2_RXD_BM_POOL_ID_MASK) >> + MVPP2_RXD_BM_POOL_ID_OFFS; + int cpu = smp_processor_id(); + + return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) | + ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS); +} + +/* Tx descriptors helper methods */ + +/* Get number of Tx descriptors waiting to be transmitted by HW */ +static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port, + struct mvpp2_tx_queue *txq) +{ + u32 val; + + mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); + val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); + + return val & MVPP2_TXQ_PENDING_MASK; +} + +/* Get pointer to next Tx descriptor to be processed (send) by HW */ +static struct mvpp2_tx_desc * +mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) +{ + int tx_desc = txq->next_desc_to_proc; + + txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); + return txq->descs + tx_desc; +} + +/* Update HW with number of aggregated Tx descriptors to be sent */ +static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) +{ + /* aggregated access - relevant TXQ number is written in TX desc */ + mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending); +} + +/* Get number of sent descriptors and decrement counter. + * The number of sent descriptors is returned. + * Per-CPU access + */ +static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, + struct mvpp2_tx_queue *txq) +{ + u32 val; + + /* Reading status reg resets transmitted descriptor counter */ + val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id)); + + return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> + MVPP2_TRANSMITTED_COUNT_OFFSET; +} + +static void mvpp2_txq_sent_counter_clear(void *arg) +{ + struct mvpp2_port *port = arg; + int queue; + + for (queue = 0; queue < txq_number; queue++) { + int id = port->txqs[queue]->id; + + mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id)); + } +} + +/* Set max sizes for Tx queues */ +static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) +{ + u32 val, size, mtu; + int txq, tx_port_num; + + mtu = port->pkt_size * 8; + if (mtu > MVPP2_TXP_MTU_MAX) + mtu = MVPP2_TXP_MTU_MAX; + + /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ + mtu = 3 * mtu; + + /* Indirect access to registers */ + tx_port_num = mvpp2_egress_port(port); + mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); + + /* Set MTU */ + val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); + val &= ~MVPP2_TXP_MTU_MAX; + val |= mtu; + mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); + + /* TXP token size and all TXQs token size must be larger that MTU */ + val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); + size = val & MVPP2_TXP_TOKEN_SIZE_MAX; + if (size < mtu) { + size = mtu; + val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; + val |= size; + mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); + } + + for (txq = 0; txq < txq_number; txq++) { + val = mvpp2_read(port->priv, + MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); + size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; + + if (size < mtu) { + size = mtu; + val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; + val |= size; + mvpp2_write(port->priv, + MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), + val); + } + } +} + +/* Free Tx queue skbuffs */ +static void mvpp2_txq_bufs_free(struct mvpp2_port *port, + struct mvpp2_tx_queue *txq, + struct mvpp2_txq_pcpu *txq_pcpu, int num) +{ + int i; + + for (i = 0; i < num; i++) + mvpp2_txq_inc_get(txq_pcpu); +} + +static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, + u32 cause) +{ + int queue = fls(cause) - 1; + + return port->rxqs[queue]; +} + +static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, + u32 cause) +{ + int queue = fls(cause) - 1; + + return port->txqs[queue]; +} + +/* Rx/Tx queue initialization/cleanup methods */ + +/* Allocate and initialize descriptors for aggr TXQ */ +static int mvpp2_aggr_txq_init(struct udevice *dev, + struct mvpp2_tx_queue *aggr_txq, + int desc_num, int cpu, + struct mvpp2 *priv) +{ + /* Allocate memory for TX descriptors */ + aggr_txq->descs = buffer_loc.aggr_tx_descs; + aggr_txq->descs_phys = (dma_addr_t)buffer_loc.aggr_tx_descs; + if (!aggr_txq->descs) + return -ENOMEM; + + /* Make sure descriptor address is cache line size aligned */ + BUG_ON(aggr_txq->descs != + PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); + + aggr_txq->last_desc = aggr_txq->size - 1; + + /* Aggr TXQ no reset WA */ + aggr_txq->next_desc_to_proc = mvpp2_read(priv, + MVPP2_AGGR_TXQ_INDEX_REG(cpu)); + + /* Set Tx descriptors queue starting address */ + /* indirect access */ + mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), + aggr_txq->descs_phys); + mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num); + + return 0; +} + +/* Create a specified Rx queue */ +static int mvpp2_rxq_init(struct mvpp2_port *port, + struct mvpp2_rx_queue *rxq) + +{ + rxq->size = port->rx_ring_size; + + /* Allocate memory for RX descriptors */ + rxq->descs = buffer_loc.rx_descs; + rxq->descs_phys = (dma_addr_t)buffer_loc.rx_descs; + if (!rxq->descs) + return -ENOMEM; + + BUG_ON(rxq->descs != + PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); + + rxq->last_desc = rxq->size - 1; + + /* Zero occupied and non-occupied counters - direct access */ + mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); + + /* Set Rx descriptors queue starting address - indirect access */ + mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); + mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq->descs_phys); + mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); + mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0); + + /* Set Offset */ + mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); + + /* Add number of descriptors ready for receiving packets */ + mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); + + return 0; +} + +/* Push packets received by the RXQ to BM pool */ +static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, + struct mvpp2_rx_queue *rxq) +{ + int rx_received, i; + + rx_received = mvpp2_rxq_received(port, rxq->id); + if (!rx_received) + return; + + for (i = 0; i < rx_received; i++) { + struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); + u32 bm = mvpp2_bm_cookie_build(rx_desc); + + mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr, + rx_desc->buf_cookie); + } + mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); +} + +/* Cleanup Rx queue */ +static void mvpp2_rxq_deinit(struct mvpp2_port *port, + struct mvpp2_rx_queue *rxq) +{ + mvpp2_rxq_drop_pkts(port, rxq); + + rxq->descs = NULL; + rxq->last_desc = 0; + rxq->next_desc_to_proc = 0; + rxq->descs_phys = 0; + + /* Clear Rx descriptors queue starting address and size; + * free descriptor number + */ + mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); + mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); + mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0); + mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0); +} + +/* Create and initialize a Tx queue */ +static int mvpp2_txq_init(struct mvpp2_port *port, + struct mvpp2_tx_queue *txq) +{ + u32 val; + int cpu, desc, desc_per_txq, tx_port_num; + struct mvpp2_txq_pcpu *txq_pcpu; + + txq->size = port->tx_ring_size; + + /* Allocate memory for Tx descriptors */ + txq->descs = buffer_loc.tx_descs; + txq->descs_phys = (dma_addr_t)buffer_loc.tx_descs; + if (!txq->descs) + return -ENOMEM; + + /* Make sure descriptor address is cache line size aligned */ + BUG_ON(txq->descs != + PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE)); + + txq->last_desc = txq->size - 1; + + /* Set Tx descriptors queue starting address - indirect access */ + mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); + mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_phys); + mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size & + MVPP2_TXQ_DESC_SIZE_MASK); + mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0); + mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG, + txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); + val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG); + val &= ~MVPP2_TXQ_PENDING_MASK; + mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val); + + /* Calculate base address in prefetch buffer. We reserve 16 descriptors + * for each existing TXQ. + * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT + * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS + */ + desc_per_txq = 16; + desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + + (txq->log_id * desc_per_txq); + + mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, + MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | + MVPP2_PREF_BUF_THRESH(desc_per_txq/2)); + + /* WRR / EJP configuration - indirect access */ + tx_port_num = mvpp2_egress_port(port); + mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); + + val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); + val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; + val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); + val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; + mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); + + val = MVPP2_TXQ_TOKEN_SIZE_MAX; + mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), + val); + + for_each_present_cpu(cpu) { + txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); + txq_pcpu->size = txq->size; + } + + return 0; +} + +/* Free allocated TXQ resources */ +static void mvpp2_txq_deinit(struct mvpp2_port *port, + struct mvpp2_tx_queue *txq) +{ + txq->descs = NULL; + txq->last_desc = 0; + txq->next_desc_to_proc = 0; + txq->descs_phys = 0; + + /* Set minimum bandwidth for disabled TXQs */ + mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0); + + /* Set Tx descriptors queue starting address and size */ + mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); + mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0); + mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0); +} + +/* Cleanup Tx ports */ +static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) +{ + struct mvpp2_txq_pcpu *txq_pcpu; + int delay, pending, cpu; + u32 val; + + mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); + val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG); + val |= MVPP2_TXQ_DRAIN_EN_MASK; + mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); + + /* The napi queue has been stopped so wait for all packets + * to be transmitted. + */ + delay = 0; + do { + if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { + netdev_warn(port->dev, + "port %d: cleaning queue %d timed out\n", + port->id, txq->log_id); + break; + } + mdelay(1); + delay++; + + pending = mvpp2_txq_pend_desc_num_get(port, txq); + } while (pending); + + val &= ~MVPP2_TXQ_DRAIN_EN_MASK; + mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); + + for_each_present_cpu(cpu) { + txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); + + /* Release all packets */ + mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); + + /* Reset queue */ + txq_pcpu->count = 0; + txq_pcpu->txq_put_index = 0; + txq_pcpu->txq_get_index = 0; + } +} + +/* Cleanup all Tx queues */ +static void mvpp2_cleanup_txqs(struct mvpp2_port *port) +{ + struct mvpp2_tx_queue *txq; + int queue; + u32 val; + + val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); + + /* Reset Tx ports and delete Tx queues */ + val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); + mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); + + for (queue = 0; queue < txq_number; queue++) { + txq = port->txqs[queue]; + mvpp2_txq_clean(port, txq); + mvpp2_txq_deinit(port, txq); + } + + mvpp2_txq_sent_counter_clear(port); + + val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); + mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); +} + +/* Cleanup all Rx queues */ +static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) +{ + int queue; + + for (queue = 0; queue < rxq_number; queue++) + mvpp2_rxq_deinit(port, port->rxqs[queue]); +} + +/* Init all Rx queues for port */ +static int mvpp2_setup_rxqs(struct mvpp2_port *port) +{ + int queue, err; + + for (queue = 0; queue < rxq_number; queue++) { + err = mvpp2_rxq_init(port, port->rxqs[queue]); + if (err) + goto err_cleanup; + } + return 0; + +err_cleanup: + mvpp2_cleanup_rxqs(port); + return err; +} + +/* Init all tx queues for port */ +static int mvpp2_setup_txqs(struct mvpp2_port *port) +{ + struct mvpp2_tx_queue *txq; + int queue, err; + + for (queue = 0; queue < txq_number; queue++) { + txq = port->txqs[queue]; + err = mvpp2_txq_init(port, txq); + if (err) + goto err_cleanup; + } + + mvpp2_txq_sent_counter_clear(port); + return 0; + +err_cleanup: + mvpp2_cleanup_txqs(port); + return err; +} + +/* Adjust link */ +static void mvpp2_link_event(struct mvpp2_port *port) +{ + struct phy_device *phydev = port->phy_dev; + int status_change = 0; + u32 val; + + if (phydev->link) { + if ((port->speed != phydev->speed) || + (port->duplex != phydev->duplex)) { + u32 val; + + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | + MVPP2_GMAC_CONFIG_GMII_SPEED | + MVPP2_GMAC_CONFIG_FULL_DUPLEX | + MVPP2_GMAC_AN_SPEED_EN | + MVPP2_GMAC_AN_DUPLEX_EN); + + if (phydev->duplex) + val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; + + if (phydev->speed == SPEED_1000) + val |= MVPP2_GMAC_CONFIG_GMII_SPEED; + else if (phydev->speed == SPEED_100) + val |= MVPP2_GMAC_CONFIG_MII_SPEED; + + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + + port->duplex = phydev->duplex; + port->speed = phydev->speed; + } + } + + if (phydev->link != port->link) { + if (!phydev->link) { + port->duplex = -1; + port->speed = 0; + } + + port->link = phydev->link; + status_change = 1; + } + + if (status_change) { + if (phydev->link) { + val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); + val |= (MVPP2_GMAC_FORCE_LINK_PASS | + MVPP2_GMAC_FORCE_LINK_DOWN); + writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); + mvpp2_egress_enable(port); + mvpp2_ingress_enable(port); + } else { + mvpp2_ingress_disable(port); + mvpp2_egress_disable(port); + } + } +} + +/* Main RX/TX processing routines */ + +/* Display more error info */ +static void mvpp2_rx_error(struct mvpp2_port *port, + struct mvpp2_rx_desc *rx_desc) +{ + u32 status = rx_desc->status; + + switch (status & MVPP2_RXD_ERR_CODE_MASK) { + case MVPP2_RXD_ERR_CRC: + netdev_err(port->dev, "bad rx status %08x (crc error), size=%d\n", + status, rx_desc->data_size); + break; + case MVPP2_RXD_ERR_OVERRUN: + netdev_err(port->dev, "bad rx status %08x (overrun error), size=%d\n", + status, rx_desc->data_size); + break; + case MVPP2_RXD_ERR_RESOURCE: + netdev_err(port->dev, "bad rx status %08x (resource error), size=%d\n", + status, rx_desc->data_size); + break; + } +} + +/* Reuse skb if possible, or allocate a new skb and add it to BM pool */ +static int mvpp2_rx_refill(struct mvpp2_port *port, + struct mvpp2_bm_pool *bm_pool, + u32 bm, u32 phys_addr) +{ + mvpp2_pool_refill(port, bm, phys_addr, phys_addr); + return 0; +} + +/* Set hw internals when starting port */ +static void mvpp2_start_dev(struct mvpp2_port *port) +{ + mvpp2_gmac_max_rx_size_set(port); + mvpp2_txp_max_tx_size_set(port); + + mvpp2_port_enable(port); +} + +/* Set hw internals when stopping port */ +static void mvpp2_stop_dev(struct mvpp2_port *port) +{ + /* Stop new packets from arriving to RXQs */ + mvpp2_ingress_disable(port); + + mvpp2_egress_disable(port); + mvpp2_port_disable(port); +} + +static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port) +{ + struct phy_device *phy_dev; + + if (!port->init || port->link == 0) { + phy_dev = phy_connect(port->priv->bus, port->phyaddr, dev, + port->phy_interface); + port->phy_dev = phy_dev; + if (!phy_dev) { + netdev_err(port->dev, "cannot connect to phy\n"); + return -ENODEV; + } + phy_dev->supported &= PHY_GBIT_FEATURES; + phy_dev->advertising = phy_dev->supported; + + port->phy_dev = phy_dev; + port->link = 0; + port->duplex = 0; + port->speed = 0; + + phy_config(phy_dev); + phy_startup(phy_dev); + if (!phy_dev->link) { + printf("%s: No link\n", phy_dev->dev->name); + return -1; + } + + port->init = 1; + } else { + mvpp2_egress_enable(port); + mvpp2_ingress_enable(port); + } + + return 0; +} + +static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port) +{ + unsigned char mac_bcast[ETH_ALEN] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + int err; + + err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true); + if (err) { + netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); + return err; + } + err = mvpp2_prs_mac_da_accept(port->priv, port->id, + port->dev_addr, true); + if (err) { + netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n"); + return err; + } + err = mvpp2_prs_def_flow(port); + if (err) { + netdev_err(dev, "mvpp2_prs_def_flow failed\n"); + return err; + } + + /* Allocate the Rx/Tx queues */ + err = mvpp2_setup_rxqs(port); + if (err) { + netdev_err(port->dev, "cannot allocate Rx queues\n"); + return err; + } + + err = mvpp2_setup_txqs(port); + if (err) { + netdev_err(port->dev, "cannot allocate Tx queues\n"); + return err; + } + + err = mvpp2_phy_connect(dev, port); + if (err < 0) + return err; + + mvpp2_link_event(port); + + mvpp2_start_dev(port); + + return 0; +} + +/* No Device ops here in U-Boot */ + +/* Driver initialization */ + +static void mvpp2_port_power_up(struct mvpp2_port *port) +{ + mvpp2_port_mii_set(port); + mvpp2_port_periodic_xon_disable(port); + mvpp2_port_fc_adv_enable(port); + mvpp2_port_reset(port); +} + +/* Initialize port HW */ +static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port) +{ + struct mvpp2 *priv = port->priv; + struct mvpp2_txq_pcpu *txq_pcpu; + int queue, cpu, err; + + if (port->first_rxq + rxq_number > MVPP2_RXQ_TOTAL_NUM) + return -EINVAL; + + /* Disable port */ + mvpp2_egress_disable(port); + mvpp2_port_disable(port); + + port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs), + GFP_KERNEL); + if (!port->txqs) + return -ENOMEM; + + /* Associate physical Tx queues to this port and initialize. + * The mapping is predefined. + */ + for (queue = 0; queue < txq_number; queue++) { + int queue_phy_id = mvpp2_txq_phys(port->id, queue); + struct mvpp2_tx_queue *txq; + + txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); + if (!txq) + return -ENOMEM; + + txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu), + GFP_KERNEL); + if (!txq->pcpu) + return -ENOMEM; + + txq->id = queue_phy_id; + txq->log_id = queue; + txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; + for_each_present_cpu(cpu) { + txq_pcpu = per_cpu_ptr(txq->pcpu, cpu); + txq_pcpu->cpu = cpu; + } + + port->txqs[queue] = txq; + } + + port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs), + GFP_KERNEL); + if (!port->rxqs) + return -ENOMEM; + + /* Allocate and initialize Rx queue for this port */ + for (queue = 0; queue < rxq_number; queue++) { + struct mvpp2_rx_queue *rxq; + + /* Map physical Rx queue to port's logical Rx queue */ + rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); + if (!rxq) + return -ENOMEM; + /* Map this Rx queue to a physical queue */ + rxq->id = port->first_rxq + queue; + rxq->port = port->id; + rxq->logic_rxq = queue; + + port->rxqs[queue] = rxq; + } + + /* Configure Rx queue group interrupt for this port */ + mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(port->id), CONFIG_MV_ETH_RXQ); + + /* Create Rx descriptor rings */ + for (queue = 0; queue < rxq_number; queue++) { + struct mvpp2_rx_queue *rxq = port->rxqs[queue]; + + rxq->size = port->rx_ring_size; + rxq->pkts_coal = MVPP2_RX_COAL_PKTS; + rxq->time_coal = MVPP2_RX_COAL_USEC; + } + + mvpp2_ingress_disable(port); + + /* Port default configuration */ + mvpp2_defaults_set(port); + + /* Port's classifier configuration */ + mvpp2_cls_oversize_rxq_set(port); + mvpp2_cls_port_config(port); + + /* Provide an initial Rx packet size */ + port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN); + + /* Initialize pools for swf */ + err = mvpp2_swf_bm_pool_init(port); + if (err) + return err; + + return 0; +} + +/* Ports initialization */ +static int mvpp2_port_probe(struct udevice *dev, + struct mvpp2_port *port, + int port_node, + struct mvpp2 *priv, + int *next_first_rxq) +{ + int phy_node; + u32 id; + u32 phyaddr; + const char *phy_mode_str; + int phy_mode = -1; + int priv_common_regs_num = 2; + int err; + + phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy"); + if (phy_node < 0) { + dev_err(&pdev->dev, "missing phy\n"); + return -ENODEV; + } + + phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL); + if (phy_mode_str) + phy_mode = phy_get_interface_by_name(phy_mode_str); + if (phy_mode == -1) { + dev_err(&pdev->dev, "incorrect phy mode\n"); + return -EINVAL; + } + + id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1); + if (id == -1) { + dev_err(&pdev->dev, "missing port-id value\n"); + return -EINVAL; + } + + phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0); + + port->priv = priv; + port->id = id; + port->first_rxq = *next_first_rxq; + port->phy_node = phy_node; + port->phy_interface = phy_mode; + port->phyaddr = phyaddr; + + port->base = (void __iomem *)dev_get_addr_index(dev->parent, + priv_common_regs_num + + id); + if (IS_ERR(port->base)) + return PTR_ERR(port->base); + + port->tx_ring_size = MVPP2_MAX_TXD; + port->rx_ring_size = MVPP2_MAX_RXD; + + err = mvpp2_port_init(dev, port); + if (err < 0) { + dev_err(&pdev->dev, "failed to init port %d\n", id); + return err; + } + mvpp2_port_power_up(port); + + /* Increment the first Rx queue number to be used by the next port */ + *next_first_rxq += CONFIG_MV_ETH_RXQ; + priv->port_list[id] = port; + return 0; +} + +/* Initialize decoding windows */ +static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, + struct mvpp2 *priv) +{ + u32 win_enable; + int i; + + for (i = 0; i < 6; i++) { + mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); + mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); + + if (i < 4) + mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); + } + + win_enable = 0; + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + + mvpp2_write(priv, MVPP2_WIN_BASE(i), + (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | + dram->mbus_dram_target_id); + + mvpp2_write(priv, MVPP2_WIN_SIZE(i), + (cs->size - 1) & 0xffff0000); + + win_enable |= (1 << i); + } + + mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); +} + +/* Initialize Rx FIFO's */ +static void mvpp2_rx_fifo_init(struct mvpp2 *priv) +{ + int port; + + for (port = 0; port < MVPP2_MAX_PORTS; port++) { + mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), + MVPP2_RX_FIFO_PORT_DATA_SIZE); + mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), + MVPP2_RX_FIFO_PORT_ATTR_SIZE); + } + + mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, + MVPP2_RX_FIFO_PORT_MIN_PKT); + mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); +} + +/* Initialize network controller common part HW */ +static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) +{ + const struct mbus_dram_target_info *dram_target_info; + int err, i; + u32 val; + + /* Checks for hardware constraints (U-Boot uses only one rxq) */ + if ((rxq_number > MVPP2_MAX_RXQ) || (txq_number > MVPP2_MAX_TXQ)) { + dev_err(&pdev->dev, "invalid queue size parameter\n"); + return -EINVAL; + } + + /* MBUS windows configuration */ + dram_target_info = mvebu_mbus_dram_info(); + if (dram_target_info) + mvpp2_conf_mbus_windows(dram_target_info, priv); + + /* Disable HW PHY polling */ + val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); + val |= MVPP2_PHY_AN_STOP_SMI0_MASK; + writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); + + /* Allocate and initialize aggregated TXQs */ + priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(), + sizeof(struct mvpp2_tx_queue), + GFP_KERNEL); + if (!priv->aggr_txqs) + return -ENOMEM; + + for_each_present_cpu(i) { + priv->aggr_txqs[i].id = i; + priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; + err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i], + MVPP2_AGGR_TXQ_SIZE, i, priv); + if (err < 0) + return err; + } + + /* Rx Fifo Init */ + mvpp2_rx_fifo_init(priv); + + /* Reset Rx queue group interrupt configuration */ + for (i = 0; i < MVPP2_MAX_PORTS; i++) + mvpp2_write(priv, MVPP2_ISR_RXQ_GROUP_REG(i), + CONFIG_MV_ETH_RXQ); + + writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, + priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); + + /* Allow cache snoop when transmiting packets */ + mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); + + /* Buffer Manager initialization */ + err = mvpp2_bm_init(dev, priv); + if (err < 0) + return err; + + /* Parser default initialization */ + err = mvpp2_prs_default_init(dev, priv); + if (err < 0) + return err; + + /* Classifier default initialization */ + mvpp2_cls_init(priv); + + return 0; +} + +/* SMI / MDIO functions */ + +static int smi_wait_ready(struct mvpp2 *priv) +{ + u32 timeout = MVPP2_SMI_TIMEOUT; + u32 smi_reg; + + /* wait till the SMI is not busy */ + do { + /* read smi register */ + smi_reg = readl(priv->lms_base + MVPP2_SMI); + if (timeout-- == 0) { + printf("Error: SMI busy timeout\n"); + return -EFAULT; + } + } while (smi_reg & MVPP2_SMI_BUSY); + + return 0; +} + +/* + * mpp2_mdio_read - miiphy_read callback function. + * + * Returns 16bit phy register value, or 0xffff on error + */ +static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct mvpp2 *priv = bus->priv; + u32 smi_reg; + u32 timeout; + + /* check parameters */ + if (addr > MVPP2_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", addr); + return -EFAULT; + } + + if (reg > MVPP2_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg); + return -EFAULT; + } + + /* wait till the SMI is not busy */ + if (smi_wait_ready(priv) < 0) + return -EFAULT; + + /* fill the phy address and regiser offset and read opcode */ + smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS) + | (reg << MVPP2_SMI_REG_ADDR_OFFS) + | MVPP2_SMI_OPCODE_READ; + + /* write the smi register */ + writel(smi_reg, priv->lms_base + MVPP2_SMI); + + /* wait till read value is ready */ + timeout = MVPP2_SMI_TIMEOUT; + + do { + /* read smi register */ + smi_reg = readl(priv->lms_base + MVPP2_SMI); + if (timeout-- == 0) { + printf("Err: SMI read ready timeout\n"); + return -EFAULT; + } + } while (!(smi_reg & MVPP2_SMI_READ_VALID)); + + /* Wait for the data to update in the SMI register */ + for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++) + ; + + return readl(priv->lms_base + MVPP2_SMI) & MVPP2_SMI_DATA_MASK; +} + +/* + * mpp2_mdio_write - miiphy_write callback function. + * + * Returns 0 if write succeed, -EINVAL on bad parameters + * -ETIME on timeout + */ +static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) +{ + struct mvpp2 *priv = bus->priv; + u32 smi_reg; + + /* check parameters */ + if (addr > MVPP2_PHY_ADDR_MASK) { + printf("Error: Invalid PHY address %d\n", addr); + return -EFAULT; + } + + if (reg > MVPP2_PHY_REG_MASK) { + printf("Err: Invalid register offset %d\n", reg); + return -EFAULT; + } + + /* wait till the SMI is not busy */ + if (smi_wait_ready(priv) < 0) + return -EFAULT; + + /* fill the phy addr and reg offset and write opcode and data */ + smi_reg = value << MVPP2_SMI_DATA_OFFS; + smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS) + | (reg << MVPP2_SMI_REG_ADDR_OFFS); + smi_reg &= ~MVPP2_SMI_OPCODE_READ; + + /* write the smi register */ + writel(smi_reg, priv->lms_base + MVPP2_SMI); + + return 0; +} + +static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct mvpp2_port *port = dev_get_priv(dev); + struct mvpp2_rx_desc *rx_desc; + struct mvpp2_bm_pool *bm_pool; + dma_addr_t phys_addr; + u32 bm, rx_status; + int pool, rx_bytes, err; + int rx_received; + struct mvpp2_rx_queue *rxq; + u32 cause_rx_tx, cause_rx, cause_misc; + u8 *data; + + cause_rx_tx = mvpp2_read(port->priv, + MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); + cause_rx_tx &= ~MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; + cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; + if (!cause_rx_tx && !cause_misc) + return 0; + + cause_rx = cause_rx_tx & MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK; + + /* Process RX packets */ + cause_rx |= port->pending_cause_rx; + rxq = mvpp2_get_rx_queue(port, cause_rx); + + /* Get number of received packets and clamp the to-do */ + rx_received = mvpp2_rxq_received(port, rxq->id); + + /* Return if no packets are received */ + if (!rx_received) + return 0; + + rx_desc = mvpp2_rxq_next_desc_get(rxq); + rx_status = rx_desc->status; + rx_bytes = rx_desc->data_size - MVPP2_MH_SIZE; + phys_addr = rx_desc->buf_phys_addr; + + bm = mvpp2_bm_cookie_build(rx_desc); + pool = mvpp2_bm_cookie_pool_get(bm); + bm_pool = &port->priv->bm_pools[pool]; + + /* Check if buffer header is used */ + if (rx_status & MVPP2_RXD_BUF_HDR) + return 0; + + /* In case of an error, release the requested buffer pointer + * to the Buffer Manager. This request process is controlled + * by the hardware, and the information about the buffer is + * comprised by the RX descriptor. + */ + if (rx_status & MVPP2_RXD_ERR_SUMMARY) { + mvpp2_rx_error(port, rx_desc); + /* Return the buffer to the pool */ + mvpp2_pool_refill(port, bm, rx_desc->buf_phys_addr, + rx_desc->buf_cookie); + return 0; + } + + err = mvpp2_rx_refill(port, bm_pool, bm, phys_addr); + if (err) { + netdev_err(port->dev, "failed to refill BM pools\n"); + return 0; + } + + /* Update Rx queue management counters */ + mb(); + mvpp2_rxq_status_update(port, rxq->id, 1, 1); + + /* give packet to stack - skip on first n bytes */ + data = (u8 *)phys_addr + 2 + 32; + + if (rx_bytes <= 0) + return 0; + + /* + * No cache invalidation needed here, since the rx_buffer's are + * located in a uncached memory region + */ + *packetp = data; + + return rx_bytes; +} + +/* Drain Txq */ +static void mvpp2_txq_drain(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, + int enable) +{ + u32 val; + + mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); + val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG); + if (enable) + val |= MVPP2_TXQ_DRAIN_EN_MASK; + else + val &= ~MVPP2_TXQ_DRAIN_EN_MASK; + mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val); +} + +static int mvpp2_send(struct udevice *dev, void *packet, int length) +{ + struct mvpp2_port *port = dev_get_priv(dev); + struct mvpp2_tx_queue *txq, *aggr_txq; + struct mvpp2_tx_desc *tx_desc; + int tx_done; + int timeout; + + txq = port->txqs[0]; + aggr_txq = &port->priv->aggr_txqs[smp_processor_id()]; + + /* Get a descriptor for the first part of the packet */ + tx_desc = mvpp2_txq_next_desc_get(aggr_txq); + tx_desc->phys_txq = txq->id; + tx_desc->data_size = length; + tx_desc->packet_offset = (u32)packet & MVPP2_TX_DESC_ALIGN; + tx_desc->buf_phys_addr = (u32)packet & ~MVPP2_TX_DESC_ALIGN; + /* First and Last descriptor */ + tx_desc->command = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE + | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; + + /* Flush tx data */ + flush_dcache_range((u32)packet, (u32)packet + length); + + /* Enable transmit */ + mb(); + mvpp2_aggr_txq_pend_desc_add(port, 1); + + mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id); + + timeout = 0; + do { + if (timeout++ > 10000) { + printf("timeout: packet not sent from aggregated to phys TXQ\n"); + return 0; + } + tx_done = mvpp2_txq_pend_desc_num_get(port, txq); + } while (tx_done); + + /* Enable TXQ drain */ + mvpp2_txq_drain(port, txq, 1); + + timeout = 0; + do { + if (timeout++ > 10000) { + printf("timeout: packet not sent\n"); + return 0; + } + tx_done = mvpp2_txq_sent_desc_proc(port, txq); + } while (!tx_done); + + /* Disable TXQ drain */ + mvpp2_txq_drain(port, txq, 0); + + return 0; +} + +static int mvpp2_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct mvpp2_port *port = dev_get_priv(dev); + + /* Load current MAC address */ + memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN); + + /* Reconfigure parser accept the original MAC address */ + mvpp2_prs_update_mac_da(port, port->dev_addr); + + mvpp2_port_power_up(port); + + mvpp2_open(dev, port); + + return 0; +} + +static void mvpp2_stop(struct udevice *dev) +{ + struct mvpp2_port *port = dev_get_priv(dev); + + mvpp2_stop_dev(port); + mvpp2_cleanup_rxqs(port); + mvpp2_cleanup_txqs(port); +} + +static int mvpp2_probe(struct udevice *dev) +{ + struct mvpp2_port *port = dev_get_priv(dev); + struct mvpp2 *priv = dev_get_priv(dev->parent); + int err; + + /* Initialize network controller */ + err = mvpp2_init(dev, priv); + if (err < 0) { + dev_err(&pdev->dev, "failed to initialize controller\n"); + return err; + } + + return mvpp2_port_probe(dev, port, dev->of_offset, priv, + &buffer_loc.first_rxq); +} + +static const struct eth_ops mvpp2_ops = { + .start = mvpp2_start, + .send = mvpp2_send, + .recv = mvpp2_recv, + .stop = mvpp2_stop, +}; + +static struct driver mvpp2_driver = { + .name = "mvpp2", + .id = UCLASS_ETH, + .probe = mvpp2_probe, + .ops = &mvpp2_ops, + .priv_auto_alloc_size = sizeof(struct mvpp2_port), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +/* + * Use a MISC device to bind the n instances (child nodes) of the + * network base controller in UCLASS_ETH. + */ +static int mvpp2_base_probe(struct udevice *dev) +{ + struct mvpp2 *priv = dev_get_priv(dev); + struct mii_dev *bus; + void *bd_space; + u32 size = 0; + int i; + + /* + * U-Boot special buffer handling: + * + * Allocate buffer area for descs and rx_buffers. This is only + * done once for all interfaces. As only one interface can + * be active. Make this area DMA-safe by disabling the D-cache + */ + + /* Align buffer area for descs and rx_buffers to 1MiB */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF); + + buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space; + size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE; + + buffer_loc.tx_descs = (struct mvpp2_tx_desc *)((u32)bd_space + size); + size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE; + + buffer_loc.rx_descs = (struct mvpp2_rx_desc *)((u32)bd_space + size); + size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE; + + for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { + buffer_loc.bm_pool[i] = (u32 *)((u32)bd_space + size); + size += MVPP2_BM_POOL_SIZE_MAX * sizeof(u32); + } + + for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) { + buffer_loc.rx_buffer[i] = (u32 *)((u32)bd_space + size); + size += RX_BUFFER_SIZE; + } + + /* Save base addresses for later use */ + priv->base = (void *)dev_get_addr_index(dev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->lms_base = (void *)dev_get_addr_index(dev, 1); + if (IS_ERR(priv->lms_base)) + return PTR_ERR(priv->lms_base); + + /* Finally create and register the MDIO bus driver */ + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = mpp2_mdio_read; + bus->write = mpp2_mdio_write; + snprintf(bus->name, sizeof(bus->name), dev->name); + bus->priv = (void *)priv; + priv->bus = bus; + + return mdio_register(bus); +} + +static int mvpp2_base_bind(struct udevice *parent) +{ + const void *blob = gd->fdt_blob; + int node = parent->of_offset; + struct uclass_driver *drv; + struct udevice *dev; + struct eth_pdata *plat; + char *name; + int subnode; + u32 id; + + /* Lookup eth driver */ + drv = lists_uclass_lookup(UCLASS_ETH); + if (!drv) { + puts("Cannot find eth driver\n"); + return -ENOENT; + } + + fdt_for_each_subnode(blob, subnode, node) { + /* Skip disabled ports */ + if (!fdtdec_get_is_enabled(blob, subnode)) + continue; + + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + + id = fdtdec_get_int(blob, subnode, "port-id", -1); + + name = calloc(1, 16); + sprintf(name, "mvpp2-%d", id); + + /* Create child device UCLASS_ETH and bind it */ + device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev); + dev->of_offset = subnode; + } + + return 0; +} + +static const struct udevice_id mvpp2_ids[] = { + { .compatible = "marvell,armada-375-pp2" }, + { } +}; + +U_BOOT_DRIVER(mvpp2_base) = { + .name = "mvpp2_base", + .id = UCLASS_MISC, + .of_match = mvpp2_ids, + .bind = mvpp2_base_bind, + .probe = mvpp2_base_probe, + .priv_auto_alloc_size = sizeof(struct mvpp2), +}; diff --git a/include/net.h b/include/net.h index a739f45..31b7307 100644 --- a/include/net.h +++ b/include/net.h @@ -320,6 +320,8 @@ struct vlan_ethernet_hdr { #define PROT_ARP 0x0806 /* IP ARP protocol */ #define PROT_RARP 0x8035 /* IP ARP protocol */ #define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */ +#define PROT_IPV6 0x86dd /* IPv6 over bluebook */ +#define PROT_PPP_SES 0x8864 /* PPPoE session messages */ #define IPPROTO_ICMP 1 /* Internet Control Message Protocol */ #define IPPROTO_UDP 17 /* User Datagram Protocol */ -- 2.7.4

2 4

[U-Boot] [PATCH 1/6] spi: kirkwood_spi.c: Add compatible match ID for Armada 375
by Stefan Roese 04 Apr '16

04 Apr '16

This enables this driver for the Marvell Armada 375 SoC. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Jagan Teki <jteki(a)openedev.com> --- drivers/spi/kirkwood_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 7890796..80cdbd0 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -315,6 +315,7 @@ static const struct dm_spi_ops mvebu_spi_ops = { }; static const struct udevice_id mvebu_spi_ids[] = { + { .compatible = "marvell,armada-375-spi" }, { .compatible = "marvell,armada-380-spi" }, { .compatible = "marvell,armada-xp-spi" }, { } -- 2.7.3

3 15

[U-Boot] [PATCH 1/2] warp7: Pass the UART base definition
by Fabio Estevam 03 Apr '16

03 Apr '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> Since commit 5d69269deed0 ("mx7dsabresd: Define serial port locally") we need to specify the UART base address in each board config file, so do this to avoid a build error. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- include/configs/warp7.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 0798671..5ea5512 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -14,6 +14,8 @@ #define PHYS_SDRAM_SIZE SZ_512M +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + #define CONFIG_BOARD_EARLY_INIT_F /* MMC Config*/ -- 1.9.1

2 3

[U-Boot] [PATCH] mx6sabresd: Remove unneeded enable_lvds() function
by Fabio Estevam 03 Apr '16

03 Apr '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> enable_lvds() function only set bits IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT and IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT, but these bits were already set previously inside setup_display(). We can safely remove enable_lvds() then. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- board/freescale/mx6sabresd/mx6sabresd.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 727334a..2319354 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -365,22 +365,12 @@ static void do_enable_hdmi(struct display_info_t const *dev) imx_enable_hdmi_phy(); } -static void enable_lvds(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *) - IOMUXC_BASE_ADDR; - u32 reg = readl(&iomux->gpr[2]); - reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | - IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; - writel(reg, &iomux->gpr[2]); -} - struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB666, .detect = NULL, - .enable = enable_lvds, + .enable = NULL, .mode = { .name = "Hannstar-XGA", .refresh = 60, -- 1.9.1

2 1

[U-Boot] [PATCH] usb: gadget: Move CONFIG_USB_GADGET to Kconfig
by Semen Protsenko 03 Apr '16

03 Apr '16

From: Sam Protsenko <semen.protsenko(a)linaro.org> The description was borrowed from kernel. "tristate" type was changed to "bool" (I believe we don't support modules for u-boot yet, right?). CONFIG_USB_GADGET requires CONFIG_USB to be defined too, so add it along as well. Some platforms weren't ported though: include/configs/e2220-1170.h include/configs/sunxi-common.h include/configs/xilinx_zynqmp.h CONFIG_USB_GADGET remains in those files as there is no corresponding defconfig files for those and I don't want to break anything. Signed-off-by: Sam Protsenko <semen.protsenko(a)linaro.org> --- configs/am335x_baltos_defconfig | 2 ++ configs/am335x_boneblack_defconfig | 2 ++ configs/am335x_boneblack_vboot_defconfig | 2 ++ configs/am335x_evm_defconfig | 2 ++ configs/am335x_evm_nor_defconfig | 2 ++ configs/am335x_evm_norboot_defconfig | 2 ++ configs/am335x_evm_spiboot_defconfig | 2 ++ configs/am335x_evm_usbspl_defconfig | 2 ++ configs/am335x_gp_evm_defconfig | 2 ++ configs/am437x_gp_evm_defconfig | 2 ++ configs/am437x_sk_evm_defconfig | 2 ++ configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_ethboot_defconfig | 2 ++ configs/am43xx_evm_qspiboot_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/apalis_t30_defconfig | 1 + configs/bcm11130_defconfig | 2 ++ configs/bcm11130_nand_defconfig | 2 ++ configs/bcm28155_ap_defconfig | 2 ++ configs/bcm28155_w1d_defconfig | 2 ++ configs/beaver_defconfig | 1 + configs/birdland_bav335a_defconfig | 2 ++ configs/birdland_bav335b_defconfig | 2 ++ configs/cgtqmx6eval_defconfig | 2 ++ configs/colibri_t20_defconfig | 1 + configs/colibri_t30_defconfig | 1 + configs/colibri_vf_defconfig | 2 ++ configs/corvus_defconfig | 2 ++ configs/dalmore_defconfig | 1 + configs/dra72_evm_defconfig | 2 ++ configs/dra74_evm_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_evm_qspiboot_defconfig | 2 ++ configs/dra7xx_evm_uart3_defconfig | 2 ++ configs/draco_defconfig | 2 ++ configs/gwventana_defconfig | 2 ++ configs/jetson-tk1_defconfig | 1 + configs/kc1_defconfig | 1 + configs/ma5d4evk_defconfig | 2 ++ configs/mx6dlsabreauto_defconfig | 2 ++ configs/mx6dlsabresd_defconfig | 2 ++ configs/mx6qpsabreauto_defconfig | 2 ++ configs/mx6qsabreauto_defconfig | 2 ++ configs/mx6qsabrelite_defconfig | 2 ++ configs/mx6qsabresd_defconfig | 2 ++ configs/mx6sabresd_spl_defconfig | 2 ++ configs/mx7dsabresd_defconfig | 2 ++ configs/nitrogen6dl2g_defconfig | 2 ++ configs/nitrogen6dl_defconfig | 2 ++ configs/nitrogen6q2g_defconfig | 2 ++ configs/nitrogen6q_defconfig | 2 ++ configs/nitrogen6s1g_defconfig | 2 ++ configs/nitrogen6s_defconfig | 2 ++ configs/nyan-big_defconfig | 1 + configs/odroid-xu3_defconfig | 1 + configs/odroid_defconfig | 1 + configs/omap3_beagle_defconfig | 2 ++ configs/omap3_logic_defconfig | 2 ++ configs/omap5_uevm_defconfig | 2 ++ configs/origen_defconfig | 1 + configs/p2371-0000_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + configs/pengwyn_defconfig | 2 ++ configs/pxm2_defconfig | 2 ++ configs/rastaban_defconfig | 2 ++ configs/rut_defconfig | 2 ++ configs/s5p_goni_defconfig | 2 ++ configs/s5pc210_universal_defconfig | 1 + configs/sama5d2_xplained_mmc_defconfig | 2 ++ configs/sama5d2_xplained_spiflash_defconfig | 2 ++ configs/sama5d3xek_mmc_defconfig | 2 ++ configs/sama5d3xek_nandflash_defconfig | 2 ++ configs/sama5d3xek_spiflash_defconfig | 2 ++ configs/sama5d4_xplained_mmc_defconfig | 2 ++ configs/sama5d4_xplained_nandflash_defconfig | 2 ++ configs/sama5d4_xplained_spiflash_defconfig | 2 ++ configs/sama5d4ek_mmc_defconfig | 2 ++ configs/sama5d4ek_nandflash_defconfig | 2 ++ configs/sama5d4ek_spiflash_defconfig | 2 ++ configs/smartweb_defconfig | 2 ++ configs/sniper_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/taurus_defconfig | 2 ++ configs/tbs2910_defconfig | 2 ++ configs/thuban_defconfig | 2 ++ configs/trats2_defconfig | 1 + configs/trats_defconfig | 1 + configs/venice2_defconfig | 1 + configs/vinco_defconfig | 2 ++ configs/warp_defconfig | 2 ++ configs/zynq_picozed_defconfig | 2 ++ configs/zynq_zc706_defconfig | 2 ++ configs/zynq_zed_defconfig | 2 ++ configs/zynq_zybo_defconfig | 2 ++ drivers/usb/Kconfig | 2 ++ drivers/usb/gadget/Kconfig | 35 ++++++++++++++++++++++++++++ include/configs/am335x_evm.h | 1 - include/configs/am43xx_evm.h | 1 - include/configs/baltos.h | 1 - include/configs/bav335x.h | 1 - include/configs/bcm28155_ap.h | 1 - include/configs/cgtqmx6eval.h | 1 - include/configs/colibri_vf.h | 1 - include/configs/corvus.h | 1 - include/configs/dra7xx_evm.h | 1 - include/configs/e2220-1170.h | 6 +++++ include/configs/exynos4-common.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/kc1.h | 1 - include/configs/ma5d4evk.h | 1 - include/configs/mx6sabre_common.h | 1 - include/configs/mx7dsabresd.h | 1 - include/configs/nitrogen6x.h | 1 - include/configs/odroid_xu3.h | 1 - include/configs/omap3_beagle.h | 1 - include/configs/omap3_logic.h | 1 - include/configs/omap5_uevm.h | 1 - include/configs/pengwyn.h | 1 - include/configs/s5p_goni.h | 1 - include/configs/s5pc210_universal.h | 1 - include/configs/sama5d2_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h | 1 - include/configs/siemens-am33x-common.h | 1 - include/configs/smartweb.h | 1 - include/configs/smdkv310.h | 1 - include/configs/sniper.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/sunxi-common.h | 1 + include/configs/taurus.h | 1 - include/configs/tbs2910.h | 1 - include/configs/tegra-common-usb-gadget.h | 1 - include/configs/vinco.h | 1 - include/configs/warp.h | 1 - include/configs/xilinx_zynqmp.h | 3 +++ include/configs/zynq-common.h | 2 -- 143 files changed, 222 insertions(+), 39 deletions(-) create mode 100644 drivers/usb/gadget/Kconfig diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 276a650..96299cf 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -13,3 +13,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am335x_boneblack_defconfig b/configs/am335x_boneblack_defconfig index 4ba2579..b4fdb05 100644 --- a/configs/am335x_boneblack_defconfig +++ b/configs/am335x_boneblack_defconfig @@ -18,3 +18,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index 060aa1c..70fc5d7 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -24,3 +24,5 @@ CONFIG_DM_ETH=y CONFIG_SYS_NS16550=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 836950c..1731ae9 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -17,3 +17,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am335x_evm_nor_defconfig b/configs/am335x_evm_nor_defconfig index f336dfd..cffa338 100644 --- a/configs/am335x_evm_nor_defconfig +++ b/configs/am335x_evm_nor_defconfig @@ -13,3 +13,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am335x_evm_norboot_defconfig b/configs/am335x_evm_norboot_defconfig index 707014b..921e82f 100644 --- a/configs/am335x_evm_norboot_defconfig +++ b/configs/am335x_evm_norboot_defconfig @@ -10,3 +10,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 665dad3..0a2c374 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -13,3 +13,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am335x_evm_usbspl_defconfig b/configs/am335x_evm_usbspl_defconfig index 17370bb..ea79368 100644 --- a/configs/am335x_evm_usbspl_defconfig +++ b/configs/am335x_evm_usbspl_defconfig @@ -13,3 +13,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig index 7f12972..00c39c4 100644 --- a/configs/am335x_gp_evm_defconfig +++ b/configs/am335x_gp_evm_defconfig @@ -19,3 +19,5 @@ CONFIG_SYS_NS16550=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_RSA=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_gp_evm_defconfig index 1d79ba19..356f6fd 100644 --- a/configs/am437x_gp_evm_defconfig +++ b/configs/am437x_gp_evm_defconfig @@ -20,3 +20,5 @@ CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig index 149a028..037017d 100644 --- a/configs/am437x_sk_evm_defconfig +++ b/configs/am437x_sk_evm_defconfig @@ -24,3 +24,5 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_DMA=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 8ef28f3..526255e 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -12,3 +12,5 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig index 7143597..7aa9a42 100644 --- a/configs/am43xx_evm_ethboot_defconfig +++ b/configs/am43xx_evm_ethboot_defconfig @@ -11,3 +11,5 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index a9a862b..8dc53c4 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -10,3 +10,5 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 2c73dbe..a2fec65 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -11,3 +11,5 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index b370d6c..c78e4fe 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -16,5 +16,6 @@ CONFIG_E1000=y CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig index 4b1bc49..222c319 100644 --- a/configs/bcm11130_defconfig +++ b/configs/bcm11130_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig index 2e7aff9..7e1e682 100644 --- a/configs/bcm11130_nand_defconfig +++ b/configs/bcm11130_nand_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig index 7ec0d30..ba57944 100644 --- a/configs/bcm28155_ap_defconfig +++ b/configs/bcm28155_ap_defconfig @@ -7,3 +7,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig index 47eb31d..36849d5 100644 --- a/configs/bcm28155_w1d_defconfig +++ b/configs/bcm28155_w1d_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index fcfbf65..0cc7fba 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -19,5 +19,6 @@ CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_TEGRA20_SLINK=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/birdland_bav335a_defconfig b/configs/birdland_bav335a_defconfig index 6d7c20d..a822715 100644 --- a/configs/birdland_bav335a_defconfig +++ b/configs/birdland_bav335a_defconfig @@ -12,3 +12,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/birdland_bav335b_defconfig b/configs/birdland_bav335b_defconfig index 910ddc7..0f11379 100644 --- a/configs/birdland_bav335b_defconfig +++ b/configs/birdland_bav335b_defconfig @@ -12,3 +12,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index 8fc8e64..46bb56a 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -9,3 +9,5 @@ CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > " CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 778aae7..cdeeb11 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -18,6 +18,7 @@ CONFIG_DM_PWM=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_DM_VIDEO=y CONFIG_VIDEO_TEGRA20=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 35b29f9..6cc635c 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -14,5 +14,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 7356b77..cddeaa1 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -18,3 +18,5 @@ CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES=y CONFIG_FSL_LPUART=y CONFIG_FSL_DSPI=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 1aabf26..be1d8d7 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index 15bd9f1..2197858 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -18,5 +18,6 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig index 0a5f70b..da24992 100644 --- a/configs/dra72_evm_defconfig +++ b/configs/dra72_evm_defconfig @@ -23,3 +23,5 @@ CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/dra74_evm_defconfig b/configs/dra74_evm_defconfig index 916016d..9039b15 100644 --- a/configs/dra74_evm_defconfig +++ b/configs/dra74_evm_defconfig @@ -22,3 +22,5 @@ CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 7aaef1b..15235d9 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -14,3 +14,5 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/dra7xx_evm_qspiboot_defconfig index 0789cff..c94b05c 100644 --- a/configs/dra7xx_evm_qspiboot_defconfig +++ b/configs/dra7xx_evm_qspiboot_defconfig @@ -14,3 +14,5 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig index 768920b..cdb3b9d 100644 --- a/configs/dra7xx_evm_uart3_defconfig +++ b/configs/dra7xx_evm_uart3_defconfig @@ -15,3 +15,5 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SYS_NS16550=y CONFIG_TI_QSPI=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 967f2ff..f3084e4 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -13,3 +13,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig index 686bed6..a4c4003 100644 --- a/configs/gwventana_defconfig +++ b/configs/gwventana_defconfig @@ -17,3 +17,5 @@ CONFIG_DM=y CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index c07b278..95b1fc1 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -19,5 +19,6 @@ CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/kc1_defconfig b/configs/kc1_defconfig index 1e5c918..547f2e4 100644 --- a/configs/kc1_defconfig +++ b/configs/kc1_defconfig @@ -11,4 +11,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig index 378dc30..890410b 100644 --- a/configs/ma5d4evk_defconfig +++ b/configs/ma5d4evk_defconfig @@ -10,3 +10,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y +ONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index 46b8a9f..93c2163 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig index 45a7ec3..8b17b15 100644 --- a/configs/mx6dlsabresd_defconfig +++ b/configs/mx6dlsabresd_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig index 0877c41..cfbb005 100644 --- a/configs/mx6qpsabreauto_defconfig +++ b/configs/mx6qpsabreauto_defconfig @@ -6,3 +6,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index 36ebc89..81b0443 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index fc8323c..cf6de18 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -10,3 +10,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_DM_THERMAL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 224e6ed..adb10fa 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig index 406777c..d67abf0 100644 --- a/configs/mx6sabresd_spl_defconfig +++ b/configs/mx6sabresd_spl_defconfig @@ -9,3 +9,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 40b0e7e..6b7ce6b 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -13,3 +13,5 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 40da15c..704a2b1 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 5f7c17a..f6afe65 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index 8707d7e..08427d1 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index fbe9b6f..93c41b2 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index 078fc20..afd2b37 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 707fb58..594d3c3 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SST=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 604aacf..1c9192f 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -34,6 +34,7 @@ CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_TPM_TIS_INFINEON=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_DISPLAY=y CONFIG_I2C_EDID=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 3b543e8..2b51c93 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -18,6 +18,7 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_S2MPS11=y CONFIG_DM_REGULATOR=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_VIDEO_BRIDGE=y CONFIG_ERRNO_STR=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index 1f4016b..c3dd6eb 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -22,5 +22,6 @@ CONFIG_DM_PMIC_MAX77686=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_MAX77686=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_ERRNO_STR=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 1fb1f71..bba00fb 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -8,3 +8,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_CMD_GPIO=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index a58b85a..96874d3 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -12,3 +12,5 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_CMD_GPIO=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index cdd80cc..a685feb 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -8,3 +8,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 95c8ebc..a66b2c5 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -12,4 +12,5 @@ CONFIG_SYS_PROMPT="ORIGEN # " # CONFIG_CMD_MISC is not set CONFIG_OF_CONTROL=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 6282acf..d7d2a80 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -17,4 +17,5 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 392c539..26af6d4 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -18,4 +18,5 @@ CONFIG_PCI_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 04df7e9..f9c8c8d 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -17,4 +17,5 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 97ee71d..52fe100 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -7,3 +7,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 5b32bb1..dfc28e5 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -14,3 +14,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 6e7d0d2..913d550 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -13,3 +13,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 7a4011e..839ea31 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -14,3 +14,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index fc0a45e..eb0604e 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_PROMPT="Goni # " # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set # CONFIG_CMD_MISC is not set +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index 61f6d1f..e72085e 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -11,4 +11,5 @@ CONFIG_SYS_PROMPT="Universal # " # CONFIG_CMD_MISC is not set CONFIG_OF_CONTROL=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index d6bc70e..c9bcd54 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -11,3 +11,5 @@ CONFIG_CMD_SF=y # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index eb2f1f0..0f456b4 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -11,3 +11,5 @@ CONFIG_CMD_SF=y # CONFIG_CMD_FPGA is not set CONFIG_SPI_FLASH=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 4a97da1..6589f10 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -9,3 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 968cd66..37b31d7 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -9,3 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index bc98e6b..9056f3e 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -9,3 +9,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index f1261ab..6df9189 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 0e53b32..b78eb0d 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index a1b2c53..81140c7 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index bf81f9b..b548c4b 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index c78266e..cff422c 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 7c10aab..20efb62 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 2cb9c71..179f9a1 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -9,3 +9,5 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n" CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b" CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/sniper_defconfig b/configs/sniper_defconfig index 370c5fd..cb762b1 100644 --- a/configs/sniper_defconfig +++ b/configs/sniper_defconfig @@ -11,5 +11,6 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NFS is not set CONFIG_SYS_NS16550=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_USB_MUSB_GADGET=y CONFIG_OF_LIBFDT=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 7b60d95..e02d9dd 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -25,4 +25,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 6a487f4..a4dc686 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -25,4 +25,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index cfcae5d..dd676ad 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -20,4 +20,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index b6f6a65..8ff1d5a 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -20,4 +20,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index f45c3ed..a5729b8 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -25,4 +25,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index e25d09b..4935a30 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -24,4 +24,5 @@ CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 0af7f2d..061b334 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -15,3 +15,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_USE_TINY_PRINTF=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 3cfa09a..4aceb7f 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -9,3 +9,5 @@ CONFIG_CMD_GPIO=y CONFIG_DM=y CONFIG_DM_THERMAL=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 666cf5e..cf5332a 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -13,3 +13,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index 9c281f8..5704dbd 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -14,4 +14,5 @@ CONFIG_SYS_PROMPT="Trats2 # " # CONFIG_CMD_MISC is not set CONFIG_OF_CONTROL=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index eef22a6..d1ce93d 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -13,4 +13,5 @@ CONFIG_SYS_PROMPT="Trats # " # CONFIG_CMD_MISC is not set CONFIG_OF_CONTROL=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 954c1de..226900c 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -18,5 +18,6 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y CONFIG_TEGRA114_SPI=y CONFIG_USB=y +CONFIG_USB_GADGET=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index 7cae79b..a16f376 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -11,3 +11,5 @@ CONFIG_SYS_PROMPT="vinco => " CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index 959e29c..b68bfff 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -9,3 +9,5 @@ CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set # CONFIG_CMD_NFS is not set CONFIG_OF_LIBFDT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index f34e2e3..67e38e5 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -12,3 +12,5 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ZYNQ_SDHCI=y CONFIG_ZYNQ_GEM=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index 215f00d..d3ae438 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -21,3 +21,5 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index 4a2a2fc..9ad33ff 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -21,3 +21,5 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index 7c23fec..470c9cb 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -22,3 +22,5 @@ CONFIG_DEBUG_UART_ZYNQ=y CONFIG_DEBUG_UART_BASE=0xe0001000 CONFIG_DEBUG_UART_CLOCK=50000000 CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_GADGET=y diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index abb06fc..7fa99c6 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -88,4 +88,6 @@ endchoice endif +source "drivers/usb/gadget/Kconfig" + endif diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig new file mode 100644 index 0000000..f4698f4 --- /dev/null +++ b/drivers/usb/gadget/Kconfig @@ -0,0 +1,35 @@ +# +# USB Gadget support on a system involves +# (a) a peripheral controller, and +# (b) the gadget driver using it. +# +# NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !! +# +# - Host systems (like PCs) need CONFIG_USB (with "A" jacks). +# - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks). +# - Some systems have both kinds of controllers. +# +# With help from a special transceiver and a "Mini-AB" jack, systems with +# both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG). +# + +menuconfig USB_GADGET + bool "USB Gadget Support" + help + USB is a master/slave protocol, organized with one master + host (such as a PC) controlling up to 127 peripheral devices. + The USB hardware is asymmetric, which makes it easier to set up: + you can't connect a "to-the-host" connector to a peripheral. + + U-Boot can run in the host, or in the peripheral. In both cases + you need a low level bus controller driver, and some software + talking to it. Peripheral controllers are often discrete silicon, + or are integrated with the CPU in a microcontroller. The more + familiar host side controllers have names like "EHCI", "OHCI", + or "UHCI", and are usually integrated into southbridges on PC + motherboards. + + Enable this configuration option if you want to run U-Boot inside + a USB peripheral device. Configure one hardware driver for your + peripheral/device side bus controller, and a "gadget driver" for + your peripheral protocol. diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 150c523..29b693a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -288,7 +288,6 @@ #define CONFIG_USB_MUSB_GADGET #define CONFIG_USB_MUSB_PIO_ONLY #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index b982ed6..fd3f6a7 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -129,7 +129,6 @@ #define CONFIG_USB_DWC3 #define CONFIG_USB_DWC3_GADGET -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" diff --git a/include/configs/baltos.h b/include/configs/baltos.h index b8c915c..bfe3fa3 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -274,7 +274,6 @@ #define CONFIG_USB_MUSB_GADGET #define CONFIG_USB_MUSB_PIO_ONLY #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT -#define CONFIG_USB_GADGET #define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index a9df0b3..6c860a6 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -439,7 +439,6 @@ DEFAULT_LINUX_BOOT_ENV \ #define CONFIG_USB_MUSB_GADGET #define CONFIG_USB_MUSB_PIO_ONLY #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h index c9515a8..cf25bde 100644 --- a/include/configs/bcm28155_ap.h +++ b/include/configs/bcm28155_ap.h @@ -138,7 +138,6 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_FASTBOOT_BUF_SIZE (CONFIG_SYS_SDRAM_SIZE - SZ_1M) #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 0 #define CONFIG_USB_GADGET_DWC2_OTG diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 487c011..63e3b94 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -90,7 +90,6 @@ #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_GADGET_DOWNLOAD diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 9c73cff..7f57a54 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -233,7 +233,6 @@ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* USB Client Support */ -#define CONFIG_USB_GADGET #define CONFIG_CI_UDC #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/corvus.h b/include/configs/corvus.h index a1fd93f..fcf2bd6 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -117,7 +117,6 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_ATMEL_USBA diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 45bda4f..c0795ab 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -231,7 +231,6 @@ #define CONFIG_USB_DWC3 #define CONFIG_USB_DWC3_GADGET -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h index 33ebb7c..bf5a58f 100644 --- a/include/configs/e2220-1170.h +++ b/include/configs/e2220-1170.h @@ -54,6 +54,12 @@ /* General networking support */ #define CONFIG_CMD_DHCP +/* NOTE: There is no defconfig for this file, so don't touch this section */ +#ifndef CONFIG_SPL_BUILD +/* USB gadget mode support*/ +#define CONFIG_USB_GADGET +#endif + #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index d101a77..008d24c 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DWC2_OTG #define CONFIG_USB_GADGET_DWC2_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 38c921a..793b3fb 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -193,7 +193,6 @@ #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP /* USB Mass Storage Gadget */ -#define CONFIG_USB_GADGET #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_GADGET_DOWNLOAD diff --git a/include/configs/kc1.h b/include/configs/kc1.h index c2ac148..7f828f7 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -184,7 +184,6 @@ #define CONFIG_USB_MUSB_PIO_ONLY #define CONFIG_USB_MUSB_OMAP2PLUS -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 0 diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h index 7f8a59f..e061a10 100644 --- a/include/configs/ma5d4evk.h +++ b/include/configs/ma5d4evk.h @@ -131,7 +131,6 @@ #define CONFIG_USB_STORAGE /* USB device */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_ATMEL_USBA #define CONFIG_USB_ETHER diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index a6d821b..ceea74e 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -238,7 +238,6 @@ #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_GADGET_DOWNLOAD diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 2c981e0..5d897c2 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -253,7 +253,6 @@ #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_GADGET_DOWNLOAD diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 3416ce3..3604e44 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -330,7 +330,6 @@ #endif -#define CONFIG_USB_GADGET #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_GADGET_DOWNLOAD diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 500f0f9..01d08dc 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -53,7 +53,6 @@ #define CONFIG_USB_DWC3_PHY_SAMSUNG /* USB gadget */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 65f08a1..2112d9f 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -66,7 +66,6 @@ #define CONFIG_TWL4030_USB 1 #define CONFIG_USB_ETHER #define CONFIG_USB_ETHER_RNDIS -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_VBUS_DRAW 0 #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_G_DNL_VENDOR_NUM 0x0451 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 0fc9d1c..304e1ce 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -85,7 +85,6 @@ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER #define CONFIG_USB_ETHER_RNDIS -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_VBUS_DRAW 0 #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_G_DNL_VENDOR_NUM 0x0451 diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 18a2924..a5cfa0c 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -105,7 +105,6 @@ #define CONFIG_USB_DWC3 #define CONFIG_USB_DWC3_GADGET -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index bfc1c1e..1a670cb 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -199,7 +199,6 @@ #define CONFIG_USB_MUSB_GADGET #define CONFIG_USB_MUSB_PIO_ONLY #define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_USB_MUSB_HOST diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 40fb5ed..07a5134 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -270,7 +270,6 @@ #define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_MAX_I2C_BUS 7 -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DWC2_OTG #define CONFIG_USB_GADGET_DWC2_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 7bb62ca..ed5365a 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -176,7 +176,6 @@ #define CONFIG_POWER_I2C #define CONFIG_POWER_MAX8998 -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DWC2_OTG #define CONFIG_USB_GADGET_DWC2_OTG_PHY #define CONFIG_USB_GADGET_DUALSPEED diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index 272257e..1225aa8 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -74,7 +74,6 @@ #endif /* USB device */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_ATMEL_USBA #define CONFIG_USB_ETHER diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index bd5f4ee..ed6bafb 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -140,7 +140,6 @@ #endif /* USB device */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_ATMEL_USBA #define CONFIG_USB_ETHER diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 52b4584..d89609b 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -83,7 +83,6 @@ #endif /* USB device */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_ATMEL_USBA #define CONFIG_USB_ETHER diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index ce96a7c..3981c23 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -83,7 +83,6 @@ #endif /* USB device */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_ATMEL_USBA #define CONFIG_USB_ETHER diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 3a8b90e..df2a514 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -243,7 +243,6 @@ #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" #endif /* CONFIG_USB_MUSB_GADGET */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DOWNLOAD /* USB DRACO ID as default */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index d06e648..db820ba 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -169,7 +169,6 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_AT91 /* DFU class support */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index b7ac402..856bf7d 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -12,7 +12,6 @@ #include "exynos4-common.h" #undef CONFIG_BOARD_COMMON -#undef CONFIG_USB_GADGET #undef CONFIG_USB_GADGET_DWC2_OTG #undef CONFIG_USB_GADGET_DWC2_OTG_PHY #undef CONFIG_CMD_USB_MASS_STORAGE diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 171a8c4..45ab21f 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -201,7 +201,6 @@ #define CONFIG_USB_MUSB_OMAP2PLUS #define CONFIG_TWL4030_USB -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 0 diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 56d32e6..07519c1 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -252,7 +252,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DWC2_OTG #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b26363d..96e2b21 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -323,6 +323,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_USB_MUSB_PIO_ONLY #endif +/* NOTE: There is no defconfig for this file, so don't touch this section */ #ifdef CONFIG_USB_MUSB_GADGET #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED diff --git a/include/configs/taurus.h b/include/configs/taurus.h index c1581d8..5b190f6 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -132,7 +132,6 @@ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_AT91 /* DFU class support */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 33ac955..1b5046a 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -130,7 +130,6 @@ #ifdef CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_CI_UDC #define CONFIG_USBD_HS -#define CONFIG_USB_GADGET #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 0 diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h index f6e1d5c..c3a0151 100644 --- a/include/configs/tegra-common-usb-gadget.h +++ b/include/configs/tegra-common-usb-gadget.h @@ -10,7 +10,6 @@ #ifndef CONFIG_SPL_BUILD /* USB gadget mode support*/ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_CI_UDC #define CONFIG_CI_UDC_HAS_HOSTPC diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 92b1b4b..5073b9c 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -86,7 +86,6 @@ #endif /* USB device */ -#define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_ATMEL_USBA #define CONFIG_USB_ETHER diff --git a/include/configs/warp.h b/include/configs/warp.h index 3e9a5a3..cb93629 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -78,7 +78,6 @@ #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_USB_GADGET_DOWNLOAD diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 9d9ffd0..eaa4133 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -121,6 +121,9 @@ #define CONFIG_USB_DWC3 #define CONFIG_USB_DWC3_GADGET +/* NOTE: There is no defconfig for TARGET_ZYNQMP_EP, so don't touch this + * section + */ #define CONFIG_USB_GADGET #define CONFIG_USB_GADGET_DOWNLOAD #define CONFIG_USB_GADGET_DUALSPEED diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 77edbb8..9ff3df2 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -102,7 +102,6 @@ # define CONFIG_USB_MAX_CONTROLLER_COUNT 2 # define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ -# define CONFIG_USB_GADGET # define CONFIG_USB_GADGET_DUALSPEED # define CONFIG_USB_GADGET_DOWNLOAD # define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 @@ -113,7 +112,6 @@ # define CONFIG_G_DNL_VENDOR_NUM 0x03FD # define CONFIG_G_DNL_PRODUCT_NUM 0x0300 # define CONFIG_G_DNL_MANUFACTURER "Xilinx" -# define CONFIG_USB_GADGET # define CONFIG_USB_CABLE_CHECK # define CONFIG_CMD_DFU # define CONFIG_CMD_THOR_DOWNLOAD -- 2.7.0

3 3

[U-Boot] [PATCH] net: phy: Realtek RTL8211B/C PHY ID fix
by Karsten Merker 03 Apr '16

03 Apr '16

The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field. The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F) of the RTL8211 and the code originally applied a mask of 0xfffff0 to the PHY ID, so that matching the PHY ID to the appropriate driver code was only done on the chip type (RTL8211), but not on a specific revision. After introduction of support for the RTL8211E, which needed another startup function than the older chip revisions, commit 42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff to make the chip revision relevant for the match, but didn't provide the now-relevant lower bits of the uid field for the RTL8211B/C. Fix this by setting the full PHY ID in the RTL8211B_driver uid field. Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: Karsten Merker <merker(a)debian.org> --- drivers/net/phy/realtek.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 259a87f..b8525dd 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -5,6 +5,7 @@ * * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc. * author Andy Fleming + * Copyright 2016 Karsten Merker <merker(a)debian.org> */ #include <config.h> #include <common.h> @@ -223,7 +224,7 @@ static int rtl8211f_startup(struct phy_device *phydev) /* Support for RTL8211B PHY */ static struct phy_driver RTL8211B_driver = { .name = "RealTek RTL8211B", - .uid = 0x1cc910, + .uid = 0x1cc912, .mask = 0xffffff, .features = PHY_GBIT_FEATURES, .config = &rtl8211x_config, -- 2.1.4

3 2

[U-Boot] [PATCH] Revert "arm: Remove wireless_space board"
by Albert ARIBAUD 02 Apr '16

02 Apr '16

Revert commit b352182a and complete generic board support. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- arch/arm/mach-kirkwood/Kconfig | 4 + board/LaCie/wireless_space/Kconfig | 12 ++ board/LaCie/wireless_space/MAINTAINERS | 6 + board/LaCie/wireless_space/Makefile | 12 ++ board/LaCie/wireless_space/kwbimage.cfg | 71 +++++++++++ board/LaCie/wireless_space/wireless_space.c | 165 +++++++++++++++++++++++++ configs/wireless_space_defconfig | 7 ++ include/configs/wireless_space.h | 179 ++++++++++++++++++++++++++++ 8 files changed, 456 insertions(+) create mode 100644 board/LaCie/wireless_space/Kconfig create mode 100644 board/LaCie/wireless_space/MAINTAINERS create mode 100644 board/LaCie/wireless_space/Makefile create mode 100644 board/LaCie/wireless_space/kwbimage.cfg create mode 100644 board/LaCie/wireless_space/wireless_space.c create mode 100644 configs/wireless_space_defconfig create mode 100644 include/configs/wireless_space.h diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 9205b1e..9249564 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -37,6 +37,9 @@ config TARGET_NET2BIG_V2 config TARGET_NETSPACE_V2 bool "LaCie netspace_v2 Board" +config TARGET_WIRELESS_SPACE + bool "LaCie Wireless_space Board" + config TARGET_IB62X0 bool "ib62x0 Board" @@ -68,6 +71,7 @@ source "board/iomega/iconnect/Kconfig" source "board/keymile/km_arm/Kconfig" source "board/LaCie/net2big_v2/Kconfig" source "board/LaCie/netspace_v2/Kconfig" +source "board/LaCie/wireless_space/Kconfig" source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig new file mode 100644 index 0000000..75a2fc5 --- /dev/null +++ b/board/LaCie/wireless_space/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WIRELESS_SPACE + +config SYS_BOARD + default "wireless_space" + +config SYS_VENDOR + default "LaCie" + +config SYS_CONFIG_NAME + default "wireless_space" + +endif diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS new file mode 100644 index 0000000..c32ecb8 --- /dev/null +++ b/board/LaCie/wireless_space/MAINTAINERS @@ -0,0 +1,6 @@ +WIRELESS_SPACE BOARD +M: Albert ARIBAUD <albert.u.boot(a)aribaud.net> +S: Maintained +F: board/LaCie/wireless_space/ +F: include/configs/wireless_space.h +F: configs/wireless_space_defconfig diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile new file mode 100644 index 0000000..90a84f4 --- /dev/null +++ b/board/LaCie/wireless_space/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := wireless_space.o ../common/common.o diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg new file mode 100644 index 0000000..037248b --- /dev/null +++ b/board/LaCie/wireless_space/kwbimage.cfg @@ -0,0 +1,71 @@ +# +# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot(a)aribaud.net> +# +# Based on netspace_v2 kwbimage.cfg: +# Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # Boot from NAND flash +NAND_PAGE_SIZE 800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Values taken from image original LaCie U-Boot header dump! + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register + +DATA 0xFFD01404 0x37743000 # DDR Controller Control Low + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control + +DATA 0xFFD01418 0x00000000 # DDR Operation + +DATA 0xFFD0141C 0x00000662 # DDR Mode + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) + +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x66666666 +DATA 0xFFD10000 0x01112222 +DATA 0xFFD1000C 0x00000000 +DATA 0xFFD10104 0x00000000 +DATA 0xFFD10100 0x40000000 +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c new file mode 100644 index 0000000..8620e4b --- /dev/null +++ b/board/LaCie/wireless_space/wireless_space.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "../common/common.h" +#include "netdev.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO configuration: start FAN at low speed, USB and HDD */ + +#define WIRELESS_SPACE_OE_LOW 0xFF006808 +#define WIRELESS_SPACE_OE_HIGH 0x0000F989 +#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 +#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 + +#define WIRELESS_SPACE_REAR_BUTTON 13 +#define WIRELESS_SPACE_FRONT_BUTTON 43 + +const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Fan speed (bit 1) */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Red led */ + MPP14_GPIO, /* USB fuse */ + MPP15_SATA0_ACTn, + MPP16_GPIO, /* SATA 0 power */ + MPP17_GPIO, /* SATA 1 power */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, /* Gigabit Ethernet 1 */ + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GE1_8, + MPP29_GE1_9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GE1_15, + MPP36_GPIO, /* Fan speed (bit 2) */ + MPP37_GPIO, /* Fan speed (bit 0) */ + MPP38_GPIO, /* Fan power */ + MPP39_GPIO, /* Fan rotation fail */ + MPP40_GPIO, /* Ethernet switch link */ + MPP41_GPIO, /* USB enable host vbus */ + MPP42_GPIO, /* LED clock control */ + MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ + MPP44_GPIO, /* Red LED on/off */ + MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ + MPP46_GPIO, /* Green LED on/off */ + MPP47_GPIO, /* LED (blue, green) SATA activity blink */ + MPP48_GPIO, /* Blue LED on/off */ + 0 +}; + +struct mv88e61xx_config swcfg = { + .name = "egiga0", + .vlancfg = MV88E61XX_VLANCFG_ROUTER, + .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, + .led_init = MV88E61XX_LED_INIT_EN, + .mdip = MV88E61XX_MDIP_NOCHANGE, + .portstate = MV88E61XX_PORTSTT_FORWARDING, + .cpuport = 0x20, + .ports_enabled = 0x3F, +}; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* Boot parameters address */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); + } +#endif + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + /* configure switch on egiga0 */ + mv88e61xx_switch_initialize(&swcfg); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) +/* Return GPIO button status */ +static int +do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "button") == 0) { + if (strcmp(argv[2], "rear") == 0) + /* invert GPIO result for intuitive while/until use */ + return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); + else if (strcmp(argv[2], "front") == 0) + return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); + else + return -1; + } else { + return -1; + } +} + +U_BOOT_CMD(ws, 3, 0, do_ws, + "Return GPIO button status 0=off 1=on", + "- ws button rear|front: test buttons' states\n" +); +#endif diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig new file mode 100644 index 0000000..daf8870 --- /dev/null +++ b/configs/wireless_space_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_WIRELESS_SPACE=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h new file mode 100644 index 0000000..191ac1b --- /dev/null +++ b/include/configs/wireless_space.h @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot(a)aribaud.net> + * + * Based on the netspace_v2 code which is + * Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_WIRELESS_SPACE_H +#define _CONFIG_WIRELESS_SPACE_H + +/* + * Machine number definition + */ +#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE +#define CONFIG_IDENT_STRING " Wireless Space" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +/* SoC name */ +#define CONFIG_KW88F6281 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB + +/* + * Core clock definition + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * SDRAM configuration + */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * Different SDRAM configuration and size for some of the boards derived + * from the Network Space v2 + */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_RBTREE +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */ +#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */ +#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */ +#define CONFIG_MII +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_NETCONSOLE +#define CONFIG_MV88E61XX_SWITCH +#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define CONFIG_MV88E61XX_CMD +#define CONFIG_CMD_TFTPPUT +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Enable I2C support + */ +#ifdef CONFIG_CMD_I2C +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ +#endif /* CONFIG_CMD_I2C */ + +/* + * Partition support + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* + * File systems support + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment variables configurations + */ + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ + +/* + * Board-specific command to make using buttons etc easier + */ + +#define CONFIG_WIRELESS_SPACE_CMD + +/* + * Default environment variables + */ +#define CONFIG_PREBOOT + +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=ide reset && " \ + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \ + "preboot=" \ + "dhcp && run netconsole\0" + +#endif /* _CONFIG_WIRELESS_SPACE_H */ -- 2.5.0

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