March 2016 - U-Boot

[U-Boot] [PATCH V3] fsl: esdhc: support driver model
by Peng Fan 06 Apr '16

06 Apr '16

Support Driver Model for fsl esdhc driver. 1. Introduce a new structure struct fsl_esdhc_priv 2. Refactor fsl_esdhc_initialize which is originally used by board code. - Introduce fsl_esdhc_init to be common usage for DM and non-DM - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part. - The original API for board code is still there, but we use 'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it. 3. All the functions are changed to use 'struct fsl_esdhc_priv', except fsl_esdhc_initialize. 4. Since clk driver is not implemented, use mxc_get_clock to geth the clk and fill 'priv->sdhc_clk'. Has been tested on i.MX6UL 14X14 EVK board: " =>dm tree .... simple_bus [ + ] | `-- aips-bus@02100000 mmc [ + ] | |-- usdhc@02190000 mmc [ + ] | |-- usdhc@02194000 .... => mmc list FSL_SDHC: 0 (SD) FSL_SDHC: 1 (SD) " Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: York Sun <york.sun(a)nxp.com> Cc: Yangbo Lu <yangbo.lu(a)nxp.com> Cc: Hector Palacios <hector.palacios(a)digi.com> Cc: Eric Nelson <eric(a)nelint.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: Simon Glass <sjg(a)chromium.org> --- V3: Fix build error reported by York for PPC. V2: restructure the V1 patch. Introduce fsl_esdhc_priv structure. Introduce code to handle cd-gpios and non-removable. drivers/mmc/fsl_esdhc.c | 253 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 213 insertions(+), 40 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index ea5f4bf..3acf9e8 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -20,6 +20,8 @@ #include <fsl_esdhc.h> #include <fdt_support.h> #include <asm/io.h> +#include <dm.h> +#include <asm-generic/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -72,6 +74,30 @@ struct fsl_esdhc { uint scr; /* eSDHC control register */ }; +/** + * struct fsl_esdhc_priv + * + * @esdhc_regs: registers of the sdhc controller + * @sdhc_clk: Current clk of the sdhc controller + * @bus_width: bus width, 1bit, 4bit or 8bit + * @cfg: mmc config + * @mmc: mmc + * Following is used when Driver Model is enabled for MMC + * @dev: pointer for the device + * @non_removable: 0: removable; 1: non-removable + * @cd_gpio: gpio for card detection + */ +struct fsl_esdhc_priv { + struct fsl_esdhc *esdhc_regs; + unsigned int sdhc_clk; + unsigned int bus_width; + struct mmc_config cfg; + struct mmc *mmc; + struct udevice *dev; + int non_removable; + struct gpio_desc cd_gpio; +}; + /* Return the XFERTYP flags for a given command and data packet */ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) { @@ -118,8 +144,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) static void esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) { - struct fsl_esdhc_cfg *cfg = mmc->priv; - struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_priv *priv = mmc->priv; + struct fsl_esdhc *regs = priv->esdhc_regs; uint blocks; char *buffer; uint databuf; @@ -180,8 +206,8 @@ esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data) static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) { int timeout; - struct fsl_esdhc_cfg *cfg = mmc->priv; - struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_priv *priv = mmc->priv; + struct fsl_esdhc *regs = priv->esdhc_regs; #ifdef CONFIG_FSL_LAYERSCAPE dma_addr_t addr; #endif @@ -312,8 +338,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) int err = 0; uint xfertyp; uint irqstat; - struct fsl_esdhc_cfg *cfg = mmc->priv; - volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_priv *priv = mmc->priv; + struct fsl_esdhc *regs = priv->esdhc_regs; #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) @@ -482,9 +508,9 @@ out: static void set_sysctl(struct mmc *mmc, uint clock) { int div, pre_div; - struct fsl_esdhc_cfg *cfg = mmc->priv; - volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; - int sdhc_clk = cfg->sdhc_clk; + struct fsl_esdhc_priv *priv = mmc->priv; + struct fsl_esdhc *regs = priv->esdhc_regs; + int sdhc_clk = priv->sdhc_clk; uint clk; if (clock < mmc->cfg->f_min) @@ -527,8 +553,8 @@ static void set_sysctl(struct mmc *mmc, uint clock) #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK static void esdhc_clock_control(struct mmc *mmc, bool enable) { - struct fsl_esdhc_cfg *cfg = mmc->priv; - struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_priv *priv = mmc->priv; + struct fsl_esdhc *regs = priv->esdhc_regs; u32 value; u32 time_out; @@ -556,8 +582,8 @@ static void esdhc_clock_control(struct mmc *mmc, bool enable) static void esdhc_set_ios(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = mmc->priv; - struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_priv *priv = mmc->priv; + struct fsl_esdhc *regs = priv->esdhc_regs; #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK /* Select to use peripheral clock */ @@ -580,8 +606,8 @@ static void esdhc_set_ios(struct mmc *mmc) static int esdhc_init(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = mmc->priv; - struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_priv *priv = mmc->priv; + struct fsl_esdhc *regs = priv->esdhc_regs; int timeout = 1000; /* Reset the entire host controller */ @@ -621,14 +647,23 @@ static int esdhc_init(struct mmc *mmc) static int esdhc_getcd(struct mmc *mmc) { - struct fsl_esdhc_cfg *cfg = mmc->priv; - struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; + struct fsl_esdhc_priv *priv = mmc->priv; + struct fsl_esdhc *regs = priv->esdhc_regs; int timeout = 1000; #ifdef CONFIG_ESDHC_DETECT_QUIRK if (CONFIG_ESDHC_DETECT_QUIRK) return 1; #endif + +#ifdef CONFIG_DM_MMC + if (priv->non_removable) + return 1; + + if (dm_gpio_is_valid(&priv->cd_gpio)) + return dm_gpio_get_value(&priv->cd_gpio); +#endif + while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000); @@ -656,16 +691,29 @@ static const struct mmc_ops esdhc_ops = { .getcd = esdhc_getcd, }; -int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) +static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, + struct fsl_esdhc_priv *priv) +{ + if (!cfg || !priv) + return -EINVAL; + + priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); + priv->bus_width = cfg->max_bus_width; + priv->sdhc_clk = cfg->sdhc_clk; + + return 0; +}; + +static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) { struct fsl_esdhc *regs; struct mmc *mmc; u32 caps, voltage_caps; - if (!cfg) - return -1; + if (!priv) + return -EINVAL; - regs = (struct fsl_esdhc *)cfg->esdhc_base; + regs = priv->esdhc_regs; /* First reset the eSDHC controller */ esdhc_reset(regs); @@ -676,7 +724,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) #endif writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); - memset(&cfg->cfg, 0, sizeof(cfg->cfg)); + memset(&priv->cfg, 0, sizeof(priv->cfg)); voltage_caps = 0; caps = esdhc_read32(&regs->hostcapblt); @@ -698,47 +746,83 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) if (caps & ESDHC_HOSTCAPBLT_VS33) voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34; - cfg->cfg.name = "FSL_SDHC"; - cfg->cfg.ops = &esdhc_ops; + priv->cfg.name = "FSL_SDHC"; + priv->cfg.ops = &esdhc_ops; #ifdef CONFIG_SYS_SD_VOLTAGE - cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; + priv->cfg.voltages = CONFIG_SYS_SD_VOLTAGE; #else - cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; #endif - if ((cfg->cfg.voltages & voltage_caps) == 0) { + if ((priv->cfg.voltages & voltage_caps) == 0) { printf("voltage not supported by controller\n"); return -1; } - cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; + if (priv->bus_width == 8) + priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; + else if (priv->bus_width == 4) + priv->cfg.host_caps = MMC_MODE_4BIT; + + priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE - cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; + priv->cfg.host_caps |= MMC_MODE_DDR_52MHz; #endif - if (cfg->max_bus_width > 0) { - if (cfg->max_bus_width < 8) - cfg->cfg.host_caps &= ~MMC_MODE_8BIT; - if (cfg->max_bus_width < 4) - cfg->cfg.host_caps &= ~MMC_MODE_4BIT; + if (priv->bus_width > 0) { + if (priv->bus_width < 8) + priv->cfg.host_caps &= ~MMC_MODE_8BIT; + if (priv->bus_width < 4) + priv->cfg.host_caps &= ~MMC_MODE_4BIT; } if (caps & ESDHC_HOSTCAPBLT_HSS) - cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) - cfg->cfg.host_caps &= ~MMC_MODE_8BIT; + priv->cfg.host_caps &= ~MMC_MODE_8BIT; #endif - cfg->cfg.f_min = 400000; - cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000); + priv->cfg.f_min = 400000; + priv->cfg.f_max = min(priv->sdhc_clk, (u32)52000000); - cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - mmc = mmc_create(&cfg->cfg, cfg); + mmc = mmc_create(&priv->cfg, priv); if (mmc == NULL) return -1; + priv->mmc = mmc; + + return 0; +} + +int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) +{ + struct fsl_esdhc_priv *priv; + int ret; + + if (!cfg) + return -EINVAL; + + priv = calloc(sizeof(struct fsl_esdhc_priv), 1); + if (!priv) + return -ENOMEM; + + ret = fsl_esdhc_cfg_to_priv(cfg, priv); + if (ret) { + debug("%s xlate failure\n", __func__); + free(priv); + return ret; + } + + ret = fsl_esdhc_init(priv); + if (ret) { + debug("%s init failure\n", __func__); + free(priv); + return ret; + } + return 0; } @@ -819,3 +903,92 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) 4 + 1, 1); } #endif + +#ifdef CONFIG_DM_MMC +#include <asm/arch/clock.h> +static int fsl_esdhc_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct fsl_esdhc_priv *priv = dev_get_priv(dev); + const void *fdt = gd->fdt_blob; + int node = dev->of_offset; + fdt_addr_t addr; + unsigned int val; + int ret; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->esdhc_regs = (struct fsl_esdhc *)addr; + priv->dev = dev; + + val = fdtdec_get_int(fdt, node, "bus-width", -1); + if (val == 8) + priv->bus_width = 8; + else if (val == 4) + priv->bus_width = 4; + else + priv->bus_width = 1; + + if (fdt_get_property(fdt, node, "non-removable", NULL)) { + priv->non_removable = 1; + } else { + priv->non_removable = 0; + gpio_request_by_name_nodev(fdt, node, "cd-gpios", 0, + &priv->cd_gpio, GPIOD_IS_IN); + } + + /* + * TODO: + * Because lack of clk driver, if SDHC clk is not enabled, + * need to enable it first before this driver is invoked. + * + * we use MXC_ESDHC_CLK to get clk freq. + * If one would like to make this function work, + * the aliases should be provided in dts as this: + * + * aliases { + * mmc0 = &usdhc1; + * mmc1 = &usdhc2; + * mmc2 = &usdhc3; + * mmc3 = &usdhc4; + * }; + * Then if your board only supports mmc2 and mmc3, but we can + * correctly get the seq as 2 and 3, then let mxc_get_clock + * work as expected. + */ + priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); + if (priv->sdhc_clk <= 0) { + dev_err(dev, "Unable to get clk for %s\n", dev->name); + return -EINVAL; + } + + ret = fsl_esdhc_init(priv); + if (ret) { + dev_err(dev, "fsl_esdhc_init failure\n"); + return ret; + } + + upriv->mmc = priv->mmc; + + return 0; +} + +static const struct udevice_id fsl_esdhc_ids[] = { + { .compatible = "fsl,imx6ul-usdhc", }, + { .compatible = "fsl,imx6sx-usdhc", }, + { .compatible = "fsl,imx6sl-usdhc", }, + { .compatible = "fsl,imx6q-usdhc", }, + { .compatible = "fsl,imx7d-usdhc", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(fsl_esdhc) = { + .name = "fsl-esdhc-mmc", + .id = UCLASS_MMC, + .of_match = fsl_esdhc_ids, + .probe = fsl_esdhc_probe, + .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), +}; +#endif -- 2.6.2

4 11

[U-Boot] Fwd: Marvell Armada XP u-boot from uart
by Konstantin Lezhnyev 06 Apr '16

06 Apr '16

---------- Forwarded message ---------- From: Konstantin Lezhnyev <konst.ru(a)gmail.com> Date: 2015-05-26 13:30 GMT+05:00 Subject: Re: [U-Boot] Marvell Armada XP u-boot from uart To: Stefan Roese <sr(a)denx.de> I'm sorry, the wording of my question was too short. I have already fulfilled the steps described in the article. But the article describes loading of the image from manufacturer - it is not my case. 1. I create a configuration for my board from maxbcm config. 2. Set `BOOT_FROM` parameter in board\my\kwbimage.cfg to `uart`. 3. Set DDR timings/settings. 4. Upload and execute image via uart. 5. Memory training ended successfully. But then I get the following messages in the terminal: | >>spl:board_init_r() | boot device - 8 | ... | SPI probe failed. Boot device 8 - constant `BOOT_DEVICE_SPI`. Function code returns this value looks like: | u32 spl_boot_device(void) | { | /* Right now only booting via SPI NOR flash is supported */ | return BOOT_DEVICE_SPI; | } And now I repeat my question: >Is it possible to load and boot Marvell Armada XP u-boot completely from uart without spi or nand flash? Regards, kon5t. 2015-05-23 13:08 GMT+05:00 Stefan Roese <sr(a)denx.de>: > On 22.05.2015 16:12, Peter Robinson wrote: > >> Is it possible to load and boot Marvell Armada XP u-boot completely from >>> uart without spi or nand flash? >>> I have custom board with MV78460 and clean flash memory. >>> >> >> You can use kwboot I believe. >> > > Correct. kwboot can be used to upload and execute a binary (compiled for > UART booting) via UART. Please make sure to use the "-a" parameter for the > Armada XP timings. > > Thanks, > Stefan > >

4 3

[U-Boot] [PATCH] board: ge: bx50v3: Use pwm for display backlight
by Akshay Bhat 06 Apr '16

06 Apr '16

Setup the LCD backlight brightness control pin to use PWM Signed-off-by: Akshay Bhat <akshay.bhat(a)timesys.com> Cc: Stefano Babic <sbabic(a)denx.de> --- board/ge/bx50v3/bx50v3.c | 11 +++++++++++ include/configs/ge_bx50v3.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index cf2cd1a..8e55acf 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -25,6 +25,7 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <i2c.h> +#include <pwm.h> DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -324,6 +325,8 @@ static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight enable for LVDS display */ MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0) + /* backlight PWM brightness control */ + MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), }; static void do_enable_hdmi(struct display_info_t const *dev) @@ -676,9 +679,17 @@ int board_late_init(void) * as per specifications from CHI MEI */ mdelay(250); + /* enable backlight PWM 1 */ + pwm_init(0, 0, 0); + + /* duty cycle 5000000ns, period: 5000000ns */ + pwm_config(0, 5000000, 5000000); + /* Backlight Power */ gpio_direction_output(LVDS_BACKLIGHT_GP, 1); + pwm_enable(0); + return 0; } diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 6fa4a9a..e37cd33 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -327,6 +327,9 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + #undef CONFIG_CMD_PCI #ifdef CONFIG_CMD_PCI #define CONFIG_PCI -- 2.7.3

2 2

[U-Boot] [RFC PATCH v1] kirkwood_nand: claim MPP pins on the fly
by Chris Packham 06 Apr '16

06 Apr '16

Claim the MPP pins for the NAND flash controller only when it's actually being used. This allows the pins to be shared with the SPI interface which already supports an equivalent on-access MPP reconfiguration. Reviewed-by: Mark Tomlinson <mark.tomlinson(a)alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- I haven't wrapped this with a configuration option because I think it should be safe to enable by default. It will either re-apply the same MPP configuration that has already been done in the board init or put the MPP pins into the correct mode to access NAND. I've only got access to one kirkwood based board with NAND flash so I'd appreciate some feedback from someone with access to a few different boards. >From the datasheets I have access to it looks like there is only one possible MPP configuration for NF_IO[0-7] so that is what I've implemented. I'm not aware of anything using this driver that needs a different MPP config. drivers/mtd/nand/kirkwood_nand.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index 4fc34d6..ff81212 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/soc.h> +#include <asm/arch/mpp.h> #include <nand.h> /* NAND Flash Soc registers */ @@ -22,6 +23,8 @@ struct kwnandf_registers { static struct kwnandf_registers *nf_reg = (struct kwnandf_registers *)KW_NANDF_BASE; +static u32 nand_mpp_backup[9] = { 0 }; + /* * hardware specific access to control-lines/bits */ @@ -49,6 +52,22 @@ static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, void kw_nand_select_chip(struct mtd_info *mtd, int chip) { u32 data; + u32 nand_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP18_NF_IO0, + MPP19_NF_IO1, + 0 + }; + + if (chip >= 0) + kirkwood_mpp_conf(nand_config, nand_mpp_backup); + else + kirkwood_mpp_conf(nand_mpp_backup, NULL); data = readl(&nf_reg->ctrl); data |= NAND_ACTCEBOOT_BIT; -- 2.7.0

4 6

[U-Boot] [PATCH] spi: kirkwood_spi: Add support for multiple chip-selects on MVEBU
by Stefan Roese 06 Apr '16

06 Apr '16

Currently only chip-select 0 is supported by the kirkwood SPI driver. The Armada XP / 38x SoCs also use this driver and support multiple chip selects. This patch adds support for multiple CS on MVEBU. The register definitions are restructured a bit with this patch. Grouping them to the corresponding registers. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> Cc: Jagan Teki <jteki(a)openedev.com> --- arch/arm/include/asm/arch-mvebu/spi.h | 17 ++++++++++++----- drivers/spi/kirkwood_spi.c | 6 ++++++ 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-mvebu/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index e512dce..4b66499 100644 --- a/arch/arm/include/asm/arch-mvebu/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h @@ -32,13 +32,15 @@ struct kwspi_registers { #define SCK_MPP10 (1 << 1) #define MISO_MPP11 (1 << 2) +/* Control Register */ +#define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ +#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ +#define KWSPI_CS_SHIFT 2 /* chip select shift */ +#define KWSPI_CS_MASK 0x7 /* chip select mask */ + +/* Configuration Register */ #define KWSPI_CLKPRESCL_MASK 0x1f #define KWSPI_CLKPRESCL_MIN 0x12 -#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ -#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ -#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ -#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ -#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ #define KWSPI_XFERLEN_1BYTE 0 #define KWSPI_XFERLEN_2BYTE (1 << 5) #define KWSPI_XFERLEN_MASK (1 << 5) @@ -47,6 +49,11 @@ struct kwspi_registers { #define KWSPI_ADRLEN_3BYTE (2 << 8) #define KWSPI_ADRLEN_4BYTE (3 << 8) #define KWSPI_ADRLEN_MASK (3 << 8) + +#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ +#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ +#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ + #define KWSPI_TIMEOUT 10000 #endif /* __KW_SPI_H__ */ diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index 7890796..fa30be4 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -280,6 +280,12 @@ static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen, struct udevice *bus = dev->parent; struct mvebu_spi_platdata *plat = dev_get_platdata(bus); +#ifdef CONFIG_ARCH_MVEBU + clrsetbits_le32(&plat->spireg->ctrl, + KWSPI_CS_MASK << KWSPI_CS_SHIFT, + spi_chip_select(dev) << KWSPI_CS_SHIFT); +#endif + return _spi_xfer(plat->spireg, bitlen, dout, din, flags); } -- 2.7.1

3 5

[U-Boot] [PATCH] dm: core: device: set pinctrl state for pinctrl device
by Peng Fan 06 Apr '16

06 Apr '16

We may have pinmux settings for pinctrl device, like the following example: " &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; imx6ul-evk { pinctrl_hog_1: hoggrp-1 { fsl,pins = < MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 >; }; [......] }; " We should not only select pinctrl state for non pinctrl devices, we need also to handle pin mux settings such as pinctrl_log for pinctrl devices. So at the end of probing process of pinctrl device, select the default state of pinctrl device. Signed-off-by: Peng Fan <van.freenix(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/core/device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/core/device.c b/drivers/core/device.c index cb24a61..6b1ba22 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -332,6 +332,9 @@ int device_probe(struct udevice *dev) if (ret) goto fail_uclass; + if (dev->parent && device_get_uclass_id(dev) == UCLASS_PINCTRL) + pinctrl_select_state(dev, "default"); + return 0; fail_uclass: if (device_remove(dev)) { -- 2.6.2

3 3

[U-Boot] [PATCH v1] tpm: Fix uclass_first_device error handling
by Mario Six 05 Apr '16

05 Apr '16

uclass_first_device might return NULL for the device despite a zero return code. Currently, this might lead to null pointer dereferencing, since the returned device is not properly checked. Hence, always check if the device returned from uclass_first_device is NULL and return -ENODEV if it is. Signed-off-by: Mario Six <mario.six(a)gdsys.cc> --- lib/tpm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/tpm.c b/lib/tpm.c index f428d45..42aea0a 100644 --- a/lib/tpm.c +++ b/lib/tpm.c @@ -245,6 +245,8 @@ static uint32_t tpm_sendrecv_command(const void *command, ret = uclass_first_device(UCLASS_TPM, &dev); if (ret) return ret; + if (!dev) + return -ENODEV; err = tpm_xfer(dev, command, tpm_command_size(command), response, &response_length); @@ -262,8 +264,10 @@ int tpm_init(void) struct udevice *dev; err = uclass_first_device(UCLASS_TPM, &dev); - if (err || !dev) + if (err) return err; + if (!dev) + return -ENODEV; return tpm_open(dev); } -- 2.7.0.GIT

2 4

[U-Boot] [PATCH v1] Revert "fastboot: OUT transaction length must be aligned to wMaxPacketSize"
by Steve Rae 05 Apr '16

05 Apr '16

This reverts commit 9e4b510d40310bf46e09f4edd0a0b6356213df47. Signed-off-by: Steve Rae <srae(a)broadcom.com> --- As discussed on the mailing list, this change breaks the download portion of fastboot by causing the server (the device running U-Boot) to wait forever for bytes which are never sent by the client (the host connected via USB). Does anyone know how to contact: Dileep Katta <dileep.katta(a)linaro.org> (this email bounces) ? drivers/usb/gadget/f_fastboot.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index a54b4ee..887cf4f 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -57,7 +57,6 @@ static struct f_fastboot *fastboot_func; static unsigned int fastboot_flash_session_id; static unsigned int download_size; static unsigned int download_bytes; -static bool is_high_speed; static struct usb_endpoint_descriptor fs_ep_in = { .bLength = USB_DT_ENDPOINT_SIZE, @@ -241,13 +240,10 @@ static int fastboot_set_alt(struct usb_function *f, __func__, f->name, interface, alt); /* make sure we don't enable the ep twice */ - if (gadget->speed == USB_SPEED_HIGH) { + if (gadget->speed == USB_SPEED_HIGH) ret = usb_ep_enable(f_fb->out_ep, &hs_ep_out); - is_high_speed = true; - } else { + else ret = usb_ep_enable(f_fb->out_ep, &fs_ep_out); - is_high_speed = false; - } if (ret) { puts("failed to enable out ep\n"); return ret; @@ -419,20 +415,13 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) fastboot_tx_write_str(response); } -static unsigned int rx_bytes_expected(unsigned int maxpacket) +static unsigned int rx_bytes_expected(void) { int rx_remain = download_size - download_bytes; - int rem = 0; if (rx_remain < 0) return 0; if (rx_remain > EP_BUFFER_SIZE) return EP_BUFFER_SIZE; - if (rx_remain < maxpacket) { - rx_remain = maxpacket; - } else if (rx_remain % maxpacket != 0) { - rem = rx_remain % maxpacket; - rx_remain = rx_remain + (maxpacket - rem); - } return rx_remain; } @@ -444,7 +433,6 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) const unsigned char *buffer = req->buf; unsigned int buffer_size = req->actual; unsigned int pre_dot_num, now_dot_num; - unsigned int max; if (req->status != 0) { printf("Bad status: %d\n", req->status); @@ -482,9 +470,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) printf("\ndownloading of %d bytes finished\n", download_bytes); } else { - max = is_high_speed ? hs_ep_out.wMaxPacketSize : - fs_ep_out.wMaxPacketSize; - req->length = rx_bytes_expected(max); + req->length = rx_bytes_expected(); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } @@ -497,7 +483,6 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) { char *cmd = req->buf; char response[FASTBOOT_RESPONSE_LEN]; - unsigned int max; strsep(&cmd, ":"); download_size = simple_strtoul(cmd, NULL, 16); @@ -513,9 +498,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) } else { sprintf(response, "DATA%08x", download_size); req->complete = rx_handler_dl_image; - max = is_high_speed ? hs_ep_out.wMaxPacketSize : - fs_ep_out.wMaxPacketSize; - req->length = rx_bytes_expected(max); + req->length = rx_bytes_expected(); if (req->length < ep->maxpacket) req->length = ep->maxpacket; } -- 1.8.5

6 12

[U-Boot] [PATCH] dm: ns16550: Add support for reg-offset property
by Michal Simek 05 Apr '16

05 Apr '16

reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/serial/ns16550.c | 6 ++++-- include/ns16550.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 93dad338b375..28da9ddfd859 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -105,7 +105,7 @@ static void ns16550_writeb(NS16550_t port, int offset, int value) * As far as we know it doesn't make sense to support selection of * these options at run-time, so use the existing CONFIG options. */ - serial_out_shift(addr, plat->reg_shift, value); + serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); } static int ns16550_readb(NS16550_t port, int offset) @@ -116,7 +116,7 @@ static int ns16550_readb(NS16550_t port, int offset) offset *= 1 << plat->reg_shift; addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset; - return serial_in_shift(addr, plat->reg_shift); + return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); } /* We can clean these up once everything is moved to driver model */ @@ -401,6 +401,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) return -EINVAL; plat->base = addr; + plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "reg-offset", 0); plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg-shift", 0); plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, diff --git a/include/ns16550.h b/include/ns16550.h index 4e620676c453..5eeacd6ff945 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -54,6 +54,7 @@ */ struct ns16550_platdata { unsigned long base; + int reg_offset; int reg_shift; int clock; }; -- 1.9.1

7 24

[U-Boot] [PATCH v4 00/21] Add support for 96boards Dragonboard410C board
by Mateusz Kulikowski 05 Apr '16

05 Apr '16

Hi All, This is next last version of Dragonboard410c series ;) It should apply cleanly to latest master (080c499d). I welcome all improvement ideas but please bear in mind I will probably implement them after this series is merged. Very little updates this time: - Added ACKs - Added MMU configuration (I did that in mach code as it's shared for all devices using this SoC) - Fixed missing renames (ehci-fsl.h -> ehci-ci.h) - sorry for that! - Moved CONFIG_OF_LIBFDT to defconfig and cleaned it up with savedefconfig As for testing - I've manually tested it on dragonboard and did buildman test for all ARM targets (~540 boards, hopefuly I catched all that are affected by this series in any way). @Marek, Joe, Tom: thanks for the input! Regards, Mateusz V3 cover contents: Sorry for longer delay, but I had too many things to do recently. As always - for "simplicity" this series is available on my github: https://github.com/hallor/u-boot/tree/dragonboard-for-mainline-v3 There are almost no changes + one bugfix: - Bugfix: small rework of serial driver - U-Boot was interrupted when no serial converter was attached. - Updated dragonboard readme.txt with info on how to stop @ fastboot - Added SPMI entries into test.dts (so automatic DM tests would not fail) - Added Tested-by and Reviewed-by Simon (from v2 comments) - Rebased to recent master - Fixed warnings in ASIX and ULPI code - Added comments to head.S, little updates suggested by Daniel @Simon: Thanks for the tests of v2! Daniel Glöckner, Tom Rini, Jagan Teki: Thanks for the comments! V2 cover contents: This is updated series. 99% of review changes are applied, specific changes are (as always) include in each patch. You can find this series on my github (if anyone just want to try it - that branch has also wait_for_bit applied): https://github.com/hallor/u-boot/tree/dragonboard-for-mainline-v2 I did target tests on Dragonboard410c, and build tested platforms that may be affected by ULPI changes. @Simon: I decided not to rewrite pm8916_gpio for now, but for sake of "cleannes" moved offending bindings to separate file (and they are now properly childs of pm8916_gpio). I will update it during rework of SoC gpio driver (I will have to create proper pinmux/pinctrl drivers to get rid of Little Kernel eventually). This series still needs wait_for_bit series that is not included (yet). V1 cover contents: I finally managed to cleanup RFC for submission. I've included changes in each patch, there is a bit of them, but all are needed :) This series requires wait_for_bit patch that I send few days ago: https://patchwork.ozlabs.org/patch/561185/ RFC cover contents: http://lists.denx.de/pipermail/u-boot/2015-December/237365.html Changes in v4: - Add Ack from Marek - Add Ack from Marek - Add Ack from Marek - Add Ack from Marek and Joe - Add missing renames (arch/* and board/*) - Add sysmap for apq8016 (required to enable MMU) - Move CONFIG_OF_LIBFDT to defconfig and cleaned it up with savedefconfig Changes in v3: - Add msm_serial_fetch that tries to fetch characters from FIFO - Decrease no of characters requested in RX transaction - Try to fetch characters from FIFO when tstc()/pending() is called - New patch - New patch - New patch - Updated test.dts to include SPMI like sandbox.dts does - readme: Added info on how to enter fastboot mode and that dtbTool is also part of skales. Added more explanation on image generation. - head: Add comment why it's needed, drop MZ EFI signature that makes no sense on this particular SoC, fix confusing entry point name (+update .lds file) Changes in v2: - Added newline before return... (globally) - Renamed p to priv (priv data) - it required some rewrapping - Added Reviewed-by - Reordered includes (again) - Added newlines between returns - Fixed error handling in msm_gpio_probe - Added reviewed-by - Add reviewed-by - Add Reviewed-by (sjg) - Add better (any) descriptions for Kconfig items. - New patch, independent of the rest - Should compile cleanly on all affected platforms - Is orthogonal to series (i.e. if get's NAK will not break rest of series) - Add acked-by - Add reviewed-by - Add Acked-by - Use PORT_... macro to write to portsc - Remove extra whitespace in probe() - Add acked-by - Use proper entry order in Kconfig - Rename CONFIG_DM_SPMI -> CONFIG_SPMI - Fix header ordering - Add reviewed-by - Rename CONFIG_DM_SPMI -> CONFIG_SPMI - Rename r -> regs, p -> priv - Add reviewed-by - Update binding doc (drop unused bindig) - Rename DM_SPMI -> SPMI - Rename p -> priv (in write/read) - Fix header ordering (again) - Add reviewed-by - Add reviewed-by - Reordered Kconfig & Makefile (to keep alphabetical ordering) - Added link to dt binding @ help - Add Reviewed-by - Rename DM_SPMI -> SPMI - Make MND divider comments more compact :) - p -> priv - Add reviewed-by - Reordered Kconfig to keep alphabetical order - Renamed reset_sandbox -> msm_reset (typo in reset.c) - Renamed CONFIG_DM_SPMI -> CONFIG_SPMI - Removed extra enter in dragonboard file - Added ULPI* to defconfig - Added MAINTAINERS to board - Cleaned up config file - use distro defaults/environment: - Dropped multiple CONFIG_CMD* and other CONFIG_* - Added distro env/config - Dropped old boot commands - Split dts - pm8916_gpio entries are taken directly from Linux Dragonboard dts; Add handles for u-boot in -uboot.dtsi; They will be removed once gpio drivers are converted to pinctrl. - Renamed some pmic nodes, fixed dragonboard.c to find them properly. - Added header and converted comments to c98-style in head.S - Print error if pmic gpio node is not found. - New patch Changes in v1: - Added (better) help to KConfig - Added dt binding documentation - Fixed include ordering - Reworked msm_serial_getc - Added error handling to msm_uart_clk_init (that is ignored later for now) - Dropped unneeded DM_FLAG_PRE_RELOC - Added dt binding documentation - Added help to KConfig - Use clrsetbits() to switch direction - Fixed include order - Added #defines for registers/register fields - Added secondary compatible string - Added commit message - Added DT binding documentation - Added Kconfig help - Reordered includes - Dropped redundant fields from msm_sdhc - Cleaned up clock init code (+ added error handling) - Dropped mdelay - use wait_for_bit instead in reset code - Added missing newline after declarations - Added error handling if "reg" is missing - Converted base address to pointer - No changes, just added Acked-by, Reviewed-by - Reordered header files - Removed braces around constant - Added more verbose help to KConfig - Added ULPI dependency to Kconfig - Drop register #defines - use ehci-ci.h instead - Create fixed ulpi viewport for device - Use setbits/clearbits where possible - Use wait_for_bit to reset controller - Add dt binding documents - Reorder includes - Add read/write arguments documentation - add binding documentation and better Kconfig help - Changed a bit mapping - Change include order - Use clrsetbits* where possible - Add one more supported dts id - Handle missing fields in dt properly - Added dt bindings - Reoder includes - Replaced extract_* macros with ordinary shift/mask - Added error checking and whitespaces in probe - Add binding doc - Fixed inlcude ordering - Merged direction_input and direction_output functions - gpio_get: use switch instead of stacked if - use pmic_clrsetbits - add possibility to change prwkey bank name - Handle invalid bindings - Sanity HW check (i.e. check type/subtype registers) - Fix include order - Cleanup defines (added spaces for readibility) - Base address is integer to avoid casting - Use setbits_* family where possible - Drop unneded comments, added newlines where needed - Check return value of dev_get_addr - Add binding for apq8016 - Cleaned up divider calculation - Drop most of gpio.h (only empty file is needed) - Add better help for dragonboard - Move static structures to board_prepare_usb - Add DM_SPMI to defconfig Mateusz Kulikowski (21): serial: Add support for Qualcomm serial port gpio: Add support for Qualcomm gpio controller mmc: Add support for Qualcomm SDHCI controller ehci-hcd: Add init_after_reset usb: ulpi: Add Kconfig options for ULPI Migrate CONFIG_ULPI* to Kconfig usb: ulpi: Fix viewport_addr type usb: ulpi: Fix compile warning in read/write on 64-bit machines. eth: asix88179: Print packet length properly usb: Rename ehci-fsl.h to ehci-ci.h usb: ehci-ci: Add missing registers. ehci-ci.h: drop generic USBCMD fields ehci: Add support for Qualcomm EHCI drivers: Add SPMI bus uclass spmi: Add sandbox test driver drivers: spmi: Add support for Qualcomm SPMI bus driver pmic: Add support for Qualcomm PM8916 PMIC gpio: Add support for Qualcomm PM8916 gpios arm: Add support for Qualcomm Snapdragon family board: Add Qualcomm Dragonboard 410C support Add myself as Snapdragon and SPMI maintainer MAINTAINERS | 11 + arch/arm/Kconfig | 12 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/dragonboard410c-uboot.dtsi | 28 ++ arch/arm/dts/dragonboard410c.dts | 148 ++++++++++ arch/arm/mach-snapdragon/Kconfig | 26 ++ arch/arm/mach-snapdragon/Makefile | 9 + arch/arm/mach-snapdragon/clock-apq8016.c | 262 ++++++++++++++++++ arch/arm/mach-snapdragon/include/mach/gpio.h | 9 + .../mach-snapdragon/include/mach/sysmap-apq8016.h | 14 + arch/arm/mach-snapdragon/reset.c | 40 +++ arch/arm/mach-snapdragon/sysmap-apq8016.c | 30 ++ arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 +- arch/sandbox/dts/sandbox.dts | 20 ++ arch/sandbox/dts/test.dts | 20 ++ board/boundary/nitrogen6x/nitrogen6x.c | 2 +- board/denx/m53evk/m53evk.c | 2 +- board/freescale/mx51evk/mx51evk.c | 2 +- board/freescale/mx6slevk/mx6slevk.c | 2 +- board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- board/freescale/mx6sxsabresd/mx6sxsabresd.c | 2 +- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +- board/freescale/mx7dsabresd/mx7dsabresd.c | 2 +- board/qualcomm/dragonboard410c/Kconfig | 15 + board/qualcomm/dragonboard410c/MAINTAINERS | 6 + board/qualcomm/dragonboard410c/Makefile | 8 + board/qualcomm/dragonboard410c/dragonboard410c.c | 131 +++++++++ board/qualcomm/dragonboard410c/head.S | 34 +++ board/qualcomm/dragonboard410c/readme.txt | 71 +++++ board/qualcomm/dragonboard410c/u-boot.lds | 90 ++++++ board/solidrun/mx6cuboxi/mx6cuboxi.c | 2 +- configs/colibri_t20_defconfig | 2 + configs/dragonboard410c_defconfig | 26 ++ configs/harmony_defconfig | 2 + configs/mcx_defconfig | 3 + configs/mt_ventoux_defconfig | 3 + configs/sandbox_defconfig | 4 + configs/twister_defconfig | 3 + configs/zynq_picozed_defconfig | 2 + configs/zynq_zc702_defconfig | 2 + configs/zynq_zc706_defconfig | 2 + configs/zynq_zed_defconfig | 2 + configs/zynq_zybo_defconfig | 2 + doc/device-tree-bindings/gpio/gpio-msm.txt | 22 ++ doc/device-tree-bindings/gpio/pm8916_gpio.txt | 48 ++++ doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 ++ doc/device-tree-bindings/pmic/pm8916.txt | 18 ++ doc/device-tree-bindings/serial/msm-serial.txt | 6 + doc/device-tree-bindings/spmi/spmi-msm.txt | 26 ++ doc/device-tree-bindings/spmi/spmi-sandbox.txt | 31 +++ doc/device-tree-bindings/usb/ehci-msm.txt | 10 + doc/git-mailrc | 3 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/gpio/Kconfig | 24 ++ drivers/gpio/Makefile | 2 + drivers/gpio/msm_gpio.c | 135 +++++++++ drivers/gpio/pm8916_gpio.c | 302 +++++++++++++++++++++ drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/msm_sdhci.c | 180 ++++++++++++ drivers/power/pmic/Kconfig | 16 ++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/pm8916.c | 96 +++++++ drivers/serial/Kconfig | 8 + drivers/serial/Makefile | 1 + drivers/serial/serial_msm.c | 217 +++++++++++++++ drivers/spmi/Kconfig | 23 ++ drivers/spmi/Makefile | 9 + drivers/spmi/spmi-msm.c | 189 +++++++++++++ drivers/spmi/spmi-sandbox.c | 157 +++++++++++ drivers/spmi/spmi-uclass.c | 48 ++++ drivers/usb/Kconfig | 2 + drivers/usb/eth/asix88179.c | 2 +- drivers/usb/host/Kconfig | 11 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-fsl.c | 2 +- drivers/usb/host/ehci-hcd.c | 6 + drivers/usb/host/ehci-mpc512x.c | 6 +- drivers/usb/host/ehci-msm.c | 178 ++++++++++++ drivers/usb/host/ehci-mx5.c | 2 +- drivers/usb/host/ehci-mx6.c | 2 +- drivers/usb/host/ehci-mxc.c | 2 +- drivers/usb/host/ehci-vf.c | 2 +- drivers/usb/host/ehci-zynq.c | 2 +- drivers/usb/host/ehci.h | 1 + drivers/usb/ulpi/Kconfig | 33 +++ drivers/usb/ulpi/ulpi-viewport.c | 5 +- include/configs/colibri_t20.h | 3 +- include/configs/dragonboard410c.h | 150 ++++++++++ include/configs/harmony.h | 2 - include/configs/mcx.h | 2 - include/configs/tam3517-common.h | 2 - include/configs/zynq-common.h | 2 - include/dm/uclass-id.h | 1 + include/spmi/spmi.h | 47 ++++ include/usb/{ehci-fsl.h => ehci-ci.h} | 16 +- include/usb/ulpi.h | 4 +- test/dm/Makefile | 1 + test/dm/spmi.c | 115 ++++++++ 101 files changed, 3231 insertions(+), 41 deletions(-) create mode 100644 arch/arm/dts/dragonboard410c-uboot.dtsi create mode 100644 arch/arm/dts/dragonboard410c.dts create mode 100644 arch/arm/mach-snapdragon/Kconfig create mode 100644 arch/arm/mach-snapdragon/Makefile create mode 100644 arch/arm/mach-snapdragon/clock-apq8016.c create mode 100644 arch/arm/mach-snapdragon/include/mach/gpio.h create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h create mode 100644 arch/arm/mach-snapdragon/reset.c create mode 100644 arch/arm/mach-snapdragon/sysmap-apq8016.c create mode 100644 board/qualcomm/dragonboard410c/Kconfig create mode 100644 board/qualcomm/dragonboard410c/MAINTAINERS create mode 100644 board/qualcomm/dragonboard410c/Makefile create mode 100644 board/qualcomm/dragonboard410c/dragonboard410c.c create mode 100644 board/qualcomm/dragonboard410c/head.S create mode 100644 board/qualcomm/dragonboard410c/readme.txt create mode 100644 board/qualcomm/dragonboard410c/u-boot.lds create mode 100644 configs/dragonboard410c_defconfig create mode 100644 doc/device-tree-bindings/gpio/gpio-msm.txt create mode 100644 doc/device-tree-bindings/gpio/pm8916_gpio.txt create mode 100644 doc/device-tree-bindings/mmc/msm_sdhci.txt create mode 100644 doc/device-tree-bindings/pmic/pm8916.txt create mode 100644 doc/device-tree-bindings/serial/msm-serial.txt create mode 100644 doc/device-tree-bindings/spmi/spmi-msm.txt create mode 100644 doc/device-tree-bindings/spmi/spmi-sandbox.txt create mode 100644 doc/device-tree-bindings/usb/ehci-msm.txt create mode 100644 drivers/gpio/msm_gpio.c create mode 100644 drivers/gpio/pm8916_gpio.c create mode 100644 drivers/mmc/msm_sdhci.c create mode 100644 drivers/power/pmic/pm8916.c create mode 100644 drivers/serial/serial_msm.c create mode 100644 drivers/spmi/Kconfig create mode 100644 drivers/spmi/Makefile create mode 100644 drivers/spmi/spmi-msm.c create mode 100644 drivers/spmi/spmi-sandbox.c create mode 100644 drivers/spmi/spmi-uclass.c create mode 100644 drivers/usb/host/ehci-msm.c create mode 100644 drivers/usb/ulpi/Kconfig create mode 100644 include/configs/dragonboard410c.h create mode 100644 include/spmi/spmi.h rename include/usb/{ehci-fsl.h => ehci-ci.h} (96%) create mode 100644 test/dm/spmi.c -- 2.5.0

6 52