November 2016 - U-Boot

[U-Boot] [PATCH][v2] net: fman: fix 2.5G SGMII settings
by Shaohui Xie 08 Dec '16

08 Dec '16

The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in set_if_mode(), and the serdes PCS configuration are wrong, this patch uses the correct settings took from Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- changes in v2: 1. code style changes for readability. 2. uses leading 0's in values set to PHY registers. drivers/net/fm/eth.c | 33 +++++++++++++++++++++++---------- drivers/net/fm/memac.c | 1 + include/fsl_memac.h | 1 + 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index eb8e936..bf5f89b 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -45,9 +45,12 @@ static void dtsec_configure_serdes(struct fm_eth *priv) qsgmii_loop: /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ - value = PHY_SGMII_IF_MODE_SGMII; - if (!sgmii_2500) - value |= PHY_SGMII_IF_MODE_AN; + if (sgmii_2500) + value = PHY_SGMII_CR_PHY_RESET | + PHY_SGMII_IF_SPEED_GIGABIT | + PHY_SGMII_IF_MODE_SGMII; + else + value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN; memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value); @@ -55,15 +58,24 @@ qsgmii_loop: value = PHY_SGMII_DEV_ABILITY_SGMII; memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value); - /* Adjust link timer for SGMII - - 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */ - memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3); - memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40); + if (sgmii_2500) { + /* Adjust link timer for 2.5G SGMII, + * 1.6 ms in units of 3.2 ns: + * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120. + */ + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120); + } else { + /* Adjust link timer for SGMII, + * 1.6 ms in units of 8 ns: + * 1.6ms / 8ns = 2 * 10^5 = 0x30d40. + */ + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003); + memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40); + } /* Restart AN */ - value = PHY_SGMII_CR_DEF_VAL; - if (!sgmii_2500) - value |= PHY_SGMII_CR_RESET_AN; + value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN; memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value); if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) { @@ -391,6 +403,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth) /* For some reason we need to set SPEED_100 */ if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) || + (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) || (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) && mac->set_if_mode) mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100); diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 81a64bf..1b5779c 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -90,6 +90,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode |= (IF_MODE_GMII | IF_MODE_RM); break; case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_SGMII_2500: case PHY_INTERFACE_MODE_QSGMII: if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); diff --git a/include/fsl_memac.h b/include/fsl_memac.h index bed2a40..431c2a0 100644 --- a/include/fsl_memac.h +++ b/include/fsl_memac.h @@ -226,6 +226,7 @@ struct memac { #define PHY_SGMII_CR_PHY_RESET 0x8000 #define PHY_SGMII_CR_RESET_AN 0x0200 #define PHY_SGMII_CR_DEF_VAL 0x1140 +#define PHY_SGMII_IF_SPEED_GIGABIT 0x0008 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 #define PHY_SGMII_IF_MODE_AN 0x0002 #define PHY_SGMII_IF_MODE_SGMII 0x0001 -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] Do not force master mode on unaffected PHY's
by Olliver Schinagl 08 Dec '16

08 Dec '16

The current implementation to force the PHY into master mode is to have a define which affects all realtek PHY's. This is not needed as the problem only exists in the RTL8211C chips. Let us thus turn this into a quirk flag instead.

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[U-Boot] [PATCH v3 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D4
by Wenyou Yang 08 Dec '16

08 Dec '16

The purpose of the patchset is add the dts files for boards, sama5d4 Xplained board and sama5d4ek board. Changes in v3: - Fix the compatible of spi flash, use "spi-flash". - Fix the compatible of spi flash, use "spi-flash". Changes in v2: - Remove unneeded the pinctrl node for cs pin of spi0. - Remove unneeded the pinctrl node for cs pin of spi0. Wenyou Yang (2): ARM: dts: at91: add dts files for sama5d4 Xplained ARM: dts: at91: add dts file for sama5d4ek arch/arm/dts/Makefile | 6 + arch/arm/dts/at91-sama5d4_xplained.dts | 279 +++++ arch/arm/dts/at91-sama5d4ek.dts | 334 ++++++ arch/arm/dts/sama5d4.dtsi | 1910 ++++++++++++++++++++++++++++++++ 4 files changed, 2529 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d4_xplained.dts create mode 100644 arch/arm/dts/at91-sama5d4ek.dts create mode 100644 arch/arm/dts/sama5d4.dtsi -- 2.7.4

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[U-Boot] [PATCH v2] spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
by Vignesh R 08 Dec '16

08 Dec '16

According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit data interface writes until the last word of an indirect transfer otherwise indirect writes is known to fails sometimes. So, make sure that QSPI indirect writes are 32 bit sized except for the last write. If the txbuf is unaligned then use bounce buffer to avoid data aborts. So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER for all boards that use Cadence QSPI driver. [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf Signed-off-by: Vignesh R <vigneshr(a)ti.com> --- v2: - Use bounce buffer - Link to v1: https://patchwork.ozlabs.org/patch/693069/ drivers/spi/cadence_qspi_apb.c | 26 ++++++++++++++++++++------ include/configs/k2g_evm.h | 1 + include/configs/socfpga_common.h | 1 + include/configs/stv0991.h | 1 + 4 files changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e285d3c1e761..6ce98acf747d 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -30,6 +30,7 @@ #include <linux/errno.h> #include <wait_bit.h> #include <spi.h> +#include <bouncebuf.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US (1) /* 1us */ @@ -741,6 +742,17 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int remaining = n_tx; unsigned int write_bytes; int ret; + struct bounce_buffer bb; + u8 *bb_txbuf; + + /* + * Handle non-4-byte aligned accesses via bounce buffer to + * avoid data abort. + */ + ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ); + if (ret) + return ret; + bb_txbuf = bb.bounce_buffer; /* Configure the indirect read transfer bytes */ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); @@ -751,11 +763,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; - /* Handle non-4-byte aligned access to avoid data abort. */ - if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) - writesb(plat->ahbbase, txbuf, write_bytes); - else - writesl(plat->ahbbase, txbuf, write_bytes >> 2); + writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); + if (write_bytes % 4) + writesb(plat->ahbbase, + bb_txbuf + rounddown(write_bytes, 4), + write_bytes % 4); ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK << @@ -765,7 +777,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, goto failwr; } - txbuf += write_bytes; + bb_txbuf += write_bytes; remaining -= write_bytes; } @@ -776,6 +788,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, printf("Indirect write completion error (%i)\n", ret); goto failwr; } + bounce_buffer_stop(&bb); /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE_MASK, @@ -786,6 +799,7 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, plat->regbase + CQSPI_REG_INDIRECTWR); + bounce_buffer_stop(&bb); return ret; } diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index a14544526c71..1d603e0c002f 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -79,6 +79,7 @@ #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 #define CONFIG_CQSPI_DECODER 0x0 +#define CONFIG_BOUNCE_BUFFER #endif #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d37e5958b586..2de57b063334 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -208,6 +208,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 +#define CONFIG_BOUNCE_BUFFER /* * Designware SPI support diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index bfd1bd719285..09a3064bd6d6 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -74,6 +74,7 @@ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 +#define CONFIG_BOUNCE_BUFFER #endif -- 2.10.2

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[U-Boot] [PATCH v4 0/6] Add ARMv8 PSCI framework
by Hongbo Zhang 07 Dec '16

07 Dec '16

v3-v4 changes: - Re-added the 1/6 from v2, and move the newly re-named macro into Kconfig - Add "Reviewed-by: Tom Rini <trini(a)konsulko.com>" for patch 4/6 ~ 6/6. v2-v3 changes: - Drop the previous 1/6, since the previous CONFIG_ARMV8_PSCI in common parts of codes also work for generic PSCI framework, so there are 5 patches in this iteration. - Add "Reviewed-by: Tom Rini <trini(a)konsulko.com>" for patches 1/5 and 2/5, which were 2/6 and 3/6. - Move config values for ls1043 from armv8/Kconfig to s1043ardb_defconfig. v1-v2 changes: - The new config options are introduced in Kconfig when used for first time - Introduce new config options in armv8/Kconfig instead of LS1043 platform - Move previous patch 5/6 to current 2/6 place v1 notes: This patch set introduces ARMv8 PSCI framework, all the PSCI functions are implemented a default dummy one, it is up to each platform to implement their own specific ones. The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI. Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up. The last 6/6 adds a most simple implementation on NXP LS1043 platform, to verify this framework. This patch set mainly introduces ARMv8 PSCI framework, for easier review and merge, further PSCI implementation on LS1043 is coming later. Hongbo Zhang (6): ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition ARMv8: Enable SMC instruction ARMv8: Add secure sections for PSCI text and data ARMv8: Add basic PSCI framework ARMv8: Setup PSCI memory and device tree ARMv8: LS1043A: Enable LS1043A default PSCI support arch/arm/config.mk | 3 +- arch/arm/cpu/armv8/Kconfig | 41 ++++ arch/arm/cpu/armv8/Makefile | 1 + arch/arm/cpu/armv8/cpu-dt.c | 11 +- arch/arm/cpu/armv8/cpu.c | 22 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 20 ++ arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 3 +- arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | 20 ++ arch/arm/cpu/armv8/psci.S | 286 +++++++++++++++++++++++ arch/arm/cpu/armv8/sec_firmware.c | 2 +- arch/arm/cpu/armv8/sec_firmware_asm.S | 2 +- arch/arm/cpu/armv8/u-boot.lds | 57 +++++ arch/arm/include/asm/armv8/sec_firmware.h | 2 +- arch/arm/include/asm/macro.h | 2 +- arch/arm/include/asm/psci.h | 15 ++ arch/arm/include/asm/secure.h | 2 +- arch/arm/include/asm/system.h | 11 + arch/arm/lib/bootm-fdt.c | 3 +- arch/arm/lib/bootm.c | 3 + arch/arm/lib/psci-dt.c | 5 +- board/freescale/ls1043ardb/Kconfig | 9 + configs/ls1043ardb_defconfig | 3 + include/configs/ls1043ardb.h | 1 - 25 files changed, 515 insertions(+), 13 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S create mode 100644 arch/arm/cpu/armv8/psci.S -- 2.1.4

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[U-Boot] [PATCH 00/17] arm: mvebu: Add gdsys ControlCenter-Compact board
by Mario Six 07 Dec '16

07 Dec '16

This patch series adds support for the Guntermann & Drunck ControlCenter-Compact board. To this extent, some bugs in the mvebu PCI driver are fixed, a GPIO driver is added, support for the Marvell 88E1680 is added, the TPM library is extended, the kwbimage generation is streamlined, a board function for manipulating the device tree is added, and secure boot for the mvebu architecture is implemented. Dirk Eibach (4): pci: mvebu: Fix Armada 38x support arm: mvebu: Add gpio support net: phy: Support Marvell 88E1680 arm: mvebu: Add gdsys ControlCenter-Compact board Mario Six (12): mvebu: Add board_pex_config() dm: Add callback to modify the device tree lib: tpm: Add command to flush resources tools: kwbimage: Fix dest addr tools: kwbimage: Fix style violations tools: kwbimage: Fix arithmetic with void pointers tools: kwbimage: Reduce scope of variables tools: kwbimage: Remove unused parameter tools: kwbimage: Factor out add_binary_header_v1 tools: kwbimage: Refactor line parsing and fix error arm: mvebu: Implement secure boot controlcenterdc: Make secure boot available Reinhard Pfau (1): arm: mvebu: spl.c: Remove useless gd declaration Makefile | 3 +- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/controlcenterdc.dts | 629 ++++++++++++++++ arch/arm/mach-mvebu/Kconfig | 24 + arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/efuse.c | 293 ++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 2 + arch/arm/mach-mvebu/include/mach/efuse.h | 71 ++ arch/arm/mach-mvebu/include/mach/gpio.h | 41 +- arch/arm/mach-mvebu/include/mach/soc.h | 1 + arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 10 + arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 2 + arch/arm/mach-mvebu/spl.c | 2 - board/gdsys/38x/.gitignore | 1 + board/gdsys/38x/Kconfig | 51 ++ board/gdsys/38x/MAINTAINERS | 7 + board/gdsys/38x/Makefile | 45 ++ board/gdsys/38x/README | 18 + board/gdsys/38x/controlcenterdc.c | 717 ++++++++++++++++++ board/gdsys/38x/dt_helpers.c | 60 ++ board/gdsys/38x/dt_helpers.h | 16 + board/gdsys/38x/hre.c | 517 +++++++++++++ board/gdsys/38x/hre.h | 38 + board/gdsys/38x/keyprogram.c | 158 ++++ board/gdsys/38x/keyprogram.h | 14 + board/gdsys/38x/kwbimage.cfg.in | 40 + board/gdsys/38x/spl.c | 21 + board/gdsys/p1022/controlcenterd-id.c | 9 - common/board_f.c | 3 + configs/controlcenterdc_defconfig | 54 ++ drivers/net/phy/marvell.c | 51 ++ drivers/pci/pci_mvebu.c | 25 +- dts/Kconfig | 10 + include/asm-generic/global_data.h | 4 + include/common.h | 1 + include/configs/controlcenterdc.h | 244 +++++++ include/tpm.h | 45 ++ lib/tpm.c | 28 + tools/Makefile | 6 +- tools/kwbimage.c | 1091 ++++++++++++++++++++++++---- tools/kwbimage.h | 37 + 42 files changed, 4216 insertions(+), 178 deletions(-) create mode 100644 arch/arm/dts/controlcenterdc.dts create mode 100644 arch/arm/mach-mvebu/efuse.c create mode 100644 arch/arm/mach-mvebu/include/mach/efuse.h create mode 100644 board/gdsys/38x/.gitignore create mode 100644 board/gdsys/38x/Kconfig create mode 100644 board/gdsys/38x/MAINTAINERS create mode 100644 board/gdsys/38x/Makefile create mode 100644 board/gdsys/38x/README create mode 100644 board/gdsys/38x/controlcenterdc.c create mode 100644 board/gdsys/38x/dt_helpers.c create mode 100644 board/gdsys/38x/dt_helpers.h create mode 100644 board/gdsys/38x/hre.c create mode 100644 board/gdsys/38x/hre.h create mode 100644 board/gdsys/38x/keyprogram.c create mode 100644 board/gdsys/38x/keyprogram.h create mode 100644 board/gdsys/38x/kwbimage.cfg.in create mode 100644 board/gdsys/38x/spl.c create mode 100644 configs/controlcenterdc_defconfig create mode 100644 include/configs/controlcenterdc.h -- 2.9.0

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[U-Boot] uefi: x86: uboot as uefi payload
by Markus Valentin 07 Dec '16

07 Dec '16

Hi, im trying to run u-boot as uefi-payload for qemu this works totally fine. My real target is a Minnowboard Turbot. I did use the minnowmax_defconfig enabled CONFIG_EFI, CONFIG_EFI_STUB and CONFIG_EFI_STUB_64BIT. The Board has the latest uefi by Intel installed(0.93, X64). When i load U-Boot as payload for the board-uefi the efi_main function gets executed but the call to "cpu_call32" seems to get stuck ( i think its at the "retf" arch/x86/cpu/call32.S:37). Debuglog: Shell> u-boot-payload_64.efi U-Boot EFI Payload gdt: 00000047, addr: 00000000784fd570 00: 00000000 00000000 08: 00cf9200 0000ffff 10: 00af9a00 0000ffff 18: 00cf9300 0000ffff 20: 00cf9a00 0000ffff 28: 00000000 00000000 30: 00cf9200 0000ffff 38: 00af9b00 0000ffff 40: 00000000 00000000 32-bit code segment: 20 page_table: 79313000 EFI table at 78787018 size 00000760 Does anyone have experiences with this issue or with running u-boot as uefi-64 payload at all? regard Markus -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-60 Fax: (+49)-8142-66989-80 Email: mv(a)denx.de

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[U-Boot] [PATCH 0/6] dm: i2c: Set a timeline for conversion of i2c drivers
by Simon Glass 07 Dec '16

07 Dec '16

Driver-model I2C support was added about 2 years ago. So far a little over half of the driveres have been converted. This series sets a timeline for conversion of the rest by June next year. The Samsung I2C driver was one of the first converted, but some boards still remain using the old subsystem. This series converts these over in an experimental way: disabling code that uses the old framework. This should provide more time for the maintainers to take action while allowing the conversion to be completed. Simon Glass (6): arm: exynos: i2c: Convert exynos boards to use DM_I2C arm: samsung: Convert s5p_goni and smdkc100 to DM_I2C samsung: i2c: Drop old code from I2C driver samsung: i2c: Split the high-speed I2C code into a new driver dm: i2c: Add a note to I2C drivers which need conversion dm: Add timeline and guide for porting I2C drivers arch/arm/Kconfig | 2 + board/samsung/common/misc.c | 4 + board/samsung/goni/goni.c | 7 +- board/samsung/trats/trats.c | 20 +- board/samsung/trats2/trats2.c | 18 +- board/samsung/universal_c210/universal.c | 22 +- configs/origen_defconfig | 1 + doc/driver-model/i2c-howto.txt | 56 ++ drivers/i2c/Makefile | 2 +- drivers/i2c/adi_i2c.c | 3 + drivers/i2c/davinci_i2c.c | 3 + drivers/i2c/exynos_hs_i2c.c | 561 +++++++++++++++ drivers/i2c/fti2c010.c | 3 + drivers/i2c/ihs_i2c.c | 3 + drivers/i2c/kona_i2c.c | 3 + drivers/i2c/lpc32xx_i2c.c | 3 + drivers/i2c/pca9564_i2c.c | 3 + drivers/i2c/ppc4xx_i2c.c | 3 + drivers/i2c/rcar_i2c.c | 3 + drivers/i2c/s3c24x0_i2c.c | 1136 +----------------------------- drivers/i2c/s3c24x0_i2c.h | 22 + drivers/i2c/sh_i2c.c | 3 + drivers/i2c/sh_sh7734_i2c.c | 3 + drivers/i2c/soft_i2c.c | 3 + drivers/i2c/tsi108_i2c.c | 3 + drivers/i2c/zynq_i2c.c | 3 + include/configs/s5p_goni.h | 19 - include/configs/s5pc210_universal.h | 19 - include/configs/trats.h | 30 - include/configs/trats2.h | 33 - 30 files changed, 752 insertions(+), 1242 deletions(-) create mode 100644 doc/driver-model/i2c-howto.txt create mode 100644 drivers/i2c/exynos_hs_i2c.c -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v3] spi: Add error checking for invalid bus widths
by Simon Glass 06 Dec '16

06 Dec '16

At present an invalid bus width prints a message but does not return an error. This is the opposite of the correct behaviour. Adjust it to avoid code bloat in the common case, and avoid hard-to-debug failure in the uncommon case. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Display an error in U-Boot proper, but then continue - Drop patches previously applied drivers/spi/spi-uclass.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index f59a701..1ab5b75 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -418,7 +418,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_TX_QUAD; break; default: - error("spi-tx-bus-width %d not supported\n", value); + warn_non_spl("spi-tx-bus-width %d not supported\n", value); break; } @@ -433,7 +433,7 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, mode |= SPI_RX_QUAD; break; default: - error("spi-rx-bus-width %d not supported\n", value); + warn_non_spl("spi-rx-bus-width %d not supported\n", value); break; } -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v3 00/11] SF: Cadence QSPI driver fixes and clean up
by Phil Edworthy 06 Dec '16

06 Dec '16

This series has fixes, patches to clean the code up, and add support for specifying the sampling edge. Main changes in v3: 1. Added "spi: cadence_qspi: Use spi mode at the point it is needed" to address comments for SPI pol/phase code. 2. "spi: cadence_qspi: Support specifying the sample edge used" has been split into 3 separate patches. Phil Edworthy (11): spi: cadence_qspi: Fix clearing of pol/pha bits spi: cadence_qspi: Fix baud rate calculation spi: cadence_qspi: Better debug information on the SPI clock rate spi: cadence_qspi: Use #define for bits instead of bit shifts spi: cadence_qspi: Clean up the #define names spi: cadence_qspi: Use spi mode at the point it is needed spi: cadence_qspi: Remove returns from end of void functions spi: cadence_qspi: Fix CS timings spi: cadence_qspi: Move DT prop code to match layout spi: cadence_qspi: Change readdata_capture() arg to bool spi: cadence_qspi: Support specifying the sample edge used doc/device-tree-bindings/spi/spi-cadence.txt | 2 + drivers/spi/cadence_qspi.c | 17 ++- drivers/spi/cadence_qspi.h | 6 +- drivers/spi/cadence_qspi_apb.c | 193 +++++++++++++-------------- 4 files changed, 106 insertions(+), 112 deletions(-) -- 2.7.4

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