November 2016 - U-Boot

[U-Boot] U-Boot Support for SIL3531
by Rudolf J Streif 01 Nov '16

01 Nov '16

Does anyone know if u-boot supports the SIL3531 PCIE SATA controller? drivers/block/sata_sil.c explicitly lists SIL3131, SIL3132, and SIL3124. I am not that familiar with the history of the SIL SATA chips and maybe somebody knows if the SIL3531 is backwards compatible to those chips. Thank you, :rjs

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[U-Boot] [PATCH] net: add synopsys QoS ethernet driver
by Nathan Sullivan 01 Nov '16

01 Nov '16

This NIC is similar to the designware nic, however it has different registers and descriptors, hence the new driver. Signed-off-by: Nathan Sullivan <nathan.sullivan(a)ni.com> --- drivers/net/Kconfig | 19 ++ drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 773 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/dwc_eth_qos.h | 219 +++++++++++++ 4 files changed, 1012 insertions(+) create mode 100644 drivers/net/dwc_eth_qos.c create mode 100644 drivers/net/dwc_eth_qos.h diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 302c005..7a4dc68 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -124,6 +124,25 @@ config ETH_DESIGNWARE 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to provide the PHY (physical media interface). +config ETH_DESIGNWARE_QOS + bool "Synopsys Designware Ethernet QoS MAC" + select PHYLIB + help + This MAC is present in SoCs from various vendors. It supports + 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to + provide the PHY (physical media interface). It is similar to + designware ethernet, but with more features and a different + interface. + +config ETH_DESIGNWARE_QOS_FIXED_LINK + bool "Fixed 1G link on QoS MAC" + default n + depends on ETH_DESIGNWARE_QOS + help + Select to force the QoS MAC to always link at 1G, full duplex + with no attached phy. Useful for direct attachment to a + switch. + config ETHOC bool "OpenCores 10/100 Mbps Ethernet MAC" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a448526..c8ba347 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o obj-$(CONFIG_CS8900) += cs8900.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_ETH_DESIGNWARE) += designware.o +obj-$(CONFIG_ETH_DESIGNWARE_QOS) += dwc_eth_qos.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c new file mode 100644 index 0000000..f97fca1 --- /dev/null +++ b/drivers/net/dwc_eth_qos.c @@ -0,0 +1,773 @@ +/* + * (C) Copyright 2016 + * National Instruments + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Designware QoS ethernet IP driver for U-Boot + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <miiphy.h> +#include <malloc.h> +#include <pci.h> +#include <linux/compiler.h> +#include <linux/err.h> +#include <asm/io.h> +#include "dwc_eth_qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK + +static int dw_qos_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ +#ifdef CONFIG_DM_ETH + struct dw_qos_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); + struct eth_mac_regs *mac_p = priv->mac_regs_p; +#else + struct eth_mac_regs *mac_p = bus->priv; +#endif + ulong start; + u32 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_READ; + + miiaddr |= (MII_CLKRANGE_150_250M << MIICLKSHIFT) & MII_CLKMSK; + + writel(miiaddr | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + return readl(&mac_p->miidata); + udelay(10); + }; + + return -ETIMEDOUT; +} + +static int dw_qos_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ +#ifdef CONFIG_DM_ETH + struct dw_qos_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); + struct eth_mac_regs *mac_p = priv->mac_regs_p; +#else + struct eth_mac_regs *mac_p = bus->priv; +#endif + ulong start; + u32 miiaddr; + int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + miiaddr |= (MII_CLKRANGE_150_250M << MIICLKSHIFT) & MII_CLKMSK; + + writel(miiaddr | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) +static int dw_qos_mdio_reset(struct mii_dev *bus) +{ + struct udevice *dev = bus->priv; + struct dw_qos_eth_dev *priv = dev_get_priv(dev); + struct dw_qos_eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + if (!dm_gpio_is_valid(&priv->reset_gpio)) + return 0; + + /* reset the phy */ + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + udelay(pdata->reset_delays[0]); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) + return ret; + + udelay(pdata->reset_delays[1]); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + udelay(pdata->reset_delays[2]); + + return 0; +} +#endif + +static int dw_qos_mdio_init(const char *name, void *priv) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = dw_qos_mdio_read; + bus->write = dw_qos_mdio_write; + snprintf(bus->name, sizeof(bus->name), "%s", name); +#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) + bus->reset = dw_qos_mdio_reset; +#endif + + bus->priv = priv; + + return mdio_register(bus); +} + +static void dw_qos_adjust_link(struct eth_mac_regs *mac_p, + struct phy_device *phydev) +{ + u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } + + if (phydev->speed != 1000) + conf |= MII_PORTSELECT; + else + conf &= ~MII_PORTSELECT; + + if (phydev->speed == 100) + conf |= FES_100; + + if (phydev->duplex) + conf |= FULLDPLXMODE; + + writel(conf, &mac_p->conf); + + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); +} + +static int dw_qos_phy_init(struct dw_qos_eth_dev *priv, void *dev) +{ + struct phy_device *phydev; + int mask = 0xffffffff, ret; + +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; +#endif + + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_GBIT_FEATURES; + if (priv->max_speed) { + ret = phy_set_supported(phydev, priv->max_speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +#endif /* CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK */ + +static void tx_descs_init(struct dw_qos_eth_dev *priv) +{ + struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p; + struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; + char *txbuffs = &priv->txbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->des0 = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->des1 = 0; + desc_p->des2 = 0; + desc_p->des3 = DESC_TXSTS_TXLAST | DESC_TXSTS_TXFIRST; + } + + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((ulong)priv->tx_mac_descrtable, + (ulong)priv->tx_mac_descrtable + + sizeof(priv->tx_mac_descrtable)); + + writel(0, &ch0_p->txdescaddrhi); + writel((ulong)&desc_table_p[0], &ch0_p->txdescaddrlo); + writel(CONFIG_TX_DESCR_NUM - 1, &ch0_p->txdescringlen); + writel((ulong)&desc_table_p[CONFIG_TX_DESCR_NUM], &ch0_p->txdesctail); + priv->tx_currdescnum = 0; +} + +static void rx_descs_init(struct dw_qos_eth_dev *priv) +{ + struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p; + struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; + char *rxbuffs = &priv->rxbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->des0 = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->des1 = 0; + desc_p->des2 = 0; + desc_p->des3 = DESC_RXSTS_OWNBYDMA | DESC_RXSTS_BUF1V; + } + + /* Flush all Rx buffer descriptors at once */ + flush_dcache_range((ulong)priv->rx_mac_descrtable, + (ulong)priv->rx_mac_descrtable + + sizeof(priv->rx_mac_descrtable)); + + writel(0, &ch0_p->rxdescaddrhi); + writel((ulong)&desc_table_p[0], &ch0_p->rxdescaddrlo); + writel(CONFIG_RX_DESCR_NUM - 1, &ch0_p->rxdescringlen); + writel((ulong)&desc_table_p[CONFIG_RX_DESCR_NUM], &ch0_p->rxdesctail); + priv->rx_currdescnum = 0; +} + +static int _dw_qos_write_hwaddr(struct dw_qos_eth_dev *priv, u8 *mac_id) +{ + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; +} + +static void _dw_qos_eth_halt(struct dw_qos_eth_dev *priv) +{ + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p; + + writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); + writel(readl(&ch0_p->txcontrol) & ~(TXST), &ch0_p->txcontrol); + writel(readl(&ch0_p->rxcontrol) & ~(RXST), &ch0_p->rxcontrol); + +#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK + phy_shutdown(priv->phydev); +#endif +} + +static int _dw_qos_eth_init(struct dw_qos_eth_dev *priv, u8 *enetaddr) +{ + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p; + struct eth_mtl_q0_regs *mtl_p = priv->mtl_q0_regs_p; + unsigned int start, burst; + int ret = 0; + + writel(readl(&dma_p->dmamode) | DMAMAC_SRST, &dma_p->dmamode); + + start = get_timer(0); + while (readl(&dma_p->dmamode) & DMAMAC_SRST) { + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { + printf("DMA reset timeout\n"); + return -ETIMEDOUT; + } + + mdelay(100); + }; + + /* + * Soft reset above clears HW address registers. + * So we have to set it here once again. + */ + _dw_qos_write_hwaddr(priv, enetaddr); + + rx_descs_init(priv); + tx_descs_init(priv); + + writel(PBLX8, &ch0_p->control); + /* enable TX queue store-and-forward mode */ + writel(TXQ0_TSF, &mtl_p->txopmode); + +#ifdef CONFIG_DW_AXI_BURST_LEN + burst = CONFIG_DW_AXI_BURST_LEN / 8; +#else + burst = 2; +#endif + writel(TXST | (burst << TXPBLSHIFT), &ch0_p->txcontrol); + writel(RXST | (burst << RXPBLSHIFT) | + (CONFIG_ETH_BUFSIZE << RBSZSHIFT), &ch0_p->rxcontrol); + +#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK + /* Start up the PHY */ + ret = phy_startup(priv->phydev); + if (ret) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return ret; + } + + dw_qos_adjust_link(mac_p, priv->phydev); + + if (!priv->phydev->link) + return -EIO; +#else + /* just go into 1G full duplex mode and stay there */ + writel(MII_PORTSELECT | FRAMEBURSTENABLE | DISABLERXOWN | FULLDPLXMODE, + &mac_p->conf); +#endif + + writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); + + return ret; +} + +static int _dw_qos_eth_send(struct dw_qos_eth_dev *priv, void *packet, + int length) +{ + struct eth_dma_ch0_regs *ch0_p = priv->dma_ch0_regs_p; + u32 desc_num = priv->tx_currdescnum; + struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + ulong desc_start = (ulong)desc_p; + ulong desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + ulong data_start = (ulong)&priv->txbuffs[desc_num * CONFIG_ETH_BUFSIZE]; + ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + + /* + * Strictly we only need to invalidate the "txrx_status" field + * for the following check, but on some platforms we cannot + * invalidate only 4 bytes, so we flush the entire descriptor, + * which is 16 bytes in total. This is safe because the + * individual descriptors in the array are each aligned to + * ARCH_DMA_MINALIGN and padded appropriately. + */ + invalidate_dcache_range(desc_start, desc_end); + + /* Check if the descriptor is owned by CPU */ + if (desc_p->des3 & DESC_TXSTS_OWNBYDMA) { + printf("CPU not owner of tx frame\n"); + return -EPERM; + } + + memcpy((void *)data_start, packet, length); + + /* Flush data to be sent */ + flush_dcache_range(data_start, data_end); + + desc_p->des0 = data_start; + desc_p->des1 = 0; + desc_p->des2 = length & DESC_TXSTS_LENMASK; + desc_p->des3 = (length & DESC_TXSTS_LENMASK) | DESC_TXSTS_TXFIRST | + DESC_TXSTS_TXLAST; + + desc_p->des3 |= DESC_TXSTS_OWNBYDMA; + + /* Flush modified buffer descriptor */ + flush_dcache_range(desc_start, desc_end); + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_TX_DESCR_NUM) + desc_num = 0; + + priv->tx_currdescnum = desc_num; + + /* Start the transmission */ + writel((ulong)&priv->tx_mac_descrtable[CONFIG_TX_DESCR_NUM], + &ch0_p->txdesctail); + + return 0; +} + +static int _dw_qos_eth_recv(struct dw_qos_eth_dev *priv, uchar **packetp) +{ + u32 status, desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + int length = -EAGAIN; + ulong desc_start = (ulong)desc_p; + ulong desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + ulong data_start = (ulong)&priv->rxbuffs[desc_num * CONFIG_ETH_BUFSIZE]; + ulong data_end; + + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range(desc_start, desc_end); + + status = desc_p->des3; + + /* Check if the owner is the CPU */ + if (!(status & DESC_RXSTS_OWNBYDMA)) { + length = (status & DESC_RXSTS_FRMLENMSK); + + /* Invalidate received data */ + data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); + invalidate_dcache_range(data_start, data_end); + *packetp = (uchar *)data_start; + } + + return length; +} + +static int _dw_qos_free_pkt(struct dw_qos_eth_dev *priv) +{ + u32 desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + ulong desc_start = (ulong)desc_p; + ulong desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + + desc_p->des0 = (ulong)&priv->rxbuffs[desc_num * CONFIG_ETH_BUFSIZE]; + desc_p->des1 = 0; + desc_p->des2 = 0; + /* + * Make the current descriptor valid again and go to + * the next one + */ + desc_p->des3 = DESC_RXSTS_OWNBYDMA | DESC_RXSTS_BUF1V; + + /* Flush only status field - others weren't changed */ + flush_dcache_range(desc_start, desc_end); + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + priv->rx_currdescnum = desc_num; + + return 0; +} + +#ifndef CONFIG_DM_ETH +static int dw_qos_eth_init(struct eth_device *dev, bd_t *bis) +{ + return _dw_qos_eth_init(dev->priv, dev->enetaddr); +} + +static int dw_qos_eth_send(struct eth_device *dev, void *packet, int length) +{ + return _dw_qos_eth_send(dev->priv, packet, length); +} + +static int dw_qos_eth_recv(struct eth_device *dev) +{ + uchar *packet; + int length; + + length = _dw_qos_eth_recv(dev->priv, &packet); + if (length == -EAGAIN) + return 0; + net_process_received_packet(packet, length); + + _dw_qos_free_pkt(dev->priv); + + return 0; +} + +static void dw_qos_eth_halt(struct eth_device *dev) +{ + return _dw_qos_eth_halt(dev->priv); +} + +static int dw_qos_write_hwaddr(struct eth_device *dev) +{ + return _dw_qos_write_hwaddr(dev->priv, dev->enetaddr); +} + +int dw_qos_initialize(ulong base_addr, u32 interface) +{ + struct eth_device *dev; + struct dw_qos_eth_dev *priv; + + dev = (struct eth_device *)malloc(sizeof(struct eth_device)); + if (!dev) + return -ENOMEM; + + /* + * Since the priv structure contains the descriptors which need a strict + * buswidth alignment, memalign is used to allocate memory + */ + priv = (struct dw_qos_eth_dev *)memalign(ARCH_DMA_MINALIGN, + sizeof(struct dw_qos_eth_dev)); + if (!priv) { + free(dev); + return -ENOMEM; + } + + if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { + printf("dw_qos: buffers are outside DMA memory\n"); + return -EINVAL; + } + + memset(dev, 0, sizeof(struct eth_device)); + memset(priv, 0, sizeof(struct dw_qos_eth_dev)); + + sprintf(dev->name, "dwmac.%lx", base_addr); + dev->iobase = (int)base_addr; + dev->priv = priv; + + priv->dev = dev; + priv->mac_regs_p = (struct eth_mac_regs *)base_addr; + priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + + DW_DMA_BASE_OFFSET); + + dev->init = dw_qos_eth_init; + dev->send = dw_qos_eth_send; + dev->recv = dw_qos_eth_recv; + dev->halt = dw_qos_eth_halt; + dev->write_hwaddr = dw_qos_write_hwaddr; + + eth_register(dev); + + priv->interface = interface; + +#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK + dw_qos_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return dw_qos_phy_init(priv, dev); +#else + return 0; +#endif +} +#endif + +#ifdef CONFIG_DM_ETH +static int dw_qos_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + return _dw_qos_eth_init(dev->priv, pdata->enetaddr); +} + +static int dw_qos_eth_send(struct udevice *dev, void *packet, int length) +{ + struct dw_qos_eth_dev *priv = dev_get_priv(dev); + + return _dw_qos_eth_send(priv, packet, length); +} + +static int dw_qos_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct dw_qos_eth_dev *priv = dev_get_priv(dev); + + return _dw_qos_eth_recv(priv, packetp); +} + +static int dw_qos_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct dw_qos_eth_dev *priv = dev_get_priv(dev); + + return _dw_qos_free_pkt(priv); +} + +static void dw_qos_eth_stop(struct udevice *dev) +{ + struct dw_qos_eth_dev *priv = dev_get_priv(dev); + + return _dw_qos_eth_halt(priv); +} + +static int dw_qos_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_qos_eth_dev *priv = dev_get_priv(dev); + + return _dw_qos_write_hwaddr(priv, pdata->enetaddr); +} + +static int dw_qos_eth_bind(struct udevice *dev) +{ +#ifdef CONFIG_DM_PCI + static int num_cards; + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_is_on_pci_bus(dev)) { + sprintf(name, "eth_dw_qos#%u", num_cards++); + device_set_name(dev, name); + } +#endif + + return 0; +} + +static int dw_qos_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_qos_eth_dev *priv = dev_get_priv(dev); + u32 iobase = pdata->iobase; + ulong ioaddr; + int ret; + +#ifdef CONFIG_DM_PCI + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, fill in platdata before we probe the hardware. + */ + if (device_is_on_pci_bus(dev)) { + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase = dm_pci_mem_to_phys(dev, iobase); + + pdata->iobase = iobase; + pdata->phy_interface = PHY_INTERFACE_MODE_RMII; + } +#endif + + debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); + ioaddr = iobase; + priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; + priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); + priv->dma_ch0_regs_p = + (struct eth_dma_ch0_regs *)(ioaddr + DW_DMA_CH0_BASE_OFFSET); + priv->mtl_q0_regs_p = + (struct eth_mtl_q0_regs *)(ioaddr + DW_MTL_Q0_BASE_OFFSET); + priv->interface = pdata->phy_interface; + priv->max_speed = pdata->max_speed; + +#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK + dw_qos_mdio_init(dev->name, dev); + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = dw_qos_phy_init(priv, dev); +#else + ret = 0; +#endif + debug("%s, ret=%d\n", __func__, ret); + + return ret; +} + +static int dw_qos_eth_remove(struct udevice *dev) +{ + struct dw_qos_eth_dev *priv = dev_get_priv(dev); + + free(priv->phydev); +#ifndef CONFIG_ETH_DESIGNWARE_QOS_FIXED_LINK + mdio_unregister(priv->bus); + mdio_free(priv->bus); +#endif + + return 0; +} + +static const struct eth_ops dw_qos_eth_ops = { + .start = dw_qos_eth_start, + .send = dw_qos_eth_send, + .recv = dw_qos_eth_recv, + .free_pkt = dw_qos_eth_free_pkt, + .stop = dw_qos_eth_stop, + .write_hwaddr = dw_qos_eth_write_hwaddr, +}; + +static int dw_qos_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct dw_qos_eth_pdata *dw_qos_pdata = dev_get_platdata(dev); +#ifdef CONFIG_DM_GPIO + struct dw_qos_eth_dev *priv = dev_get_priv(dev); +#endif + struct eth_pdata *pdata = &dw_qos_pdata->eth_pdata; + const char *phy_mode; + const fdt32_t *cell; +#ifdef CONFIG_DM_GPIO + int reset_flags = GPIOD_IS_OUT; +#endif + int ret = 0; + + pdata->iobase = (ulong)dev_map_physmem(dev, 0x2000); + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + pdata->max_speed = 0; + cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL); + if (cell) + pdata->max_speed = fdt32_to_cpu(*cell); + +#ifdef CONFIG_DM_GPIO + if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "snps,reset-active-low")) + reset_flags |= GPIOD_ACTIVE_LOW; + + ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, + &priv->reset_gpio, reset_flags); + if (ret == 0) { + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "snps,reset-delays-us", dw_qos_pdata->reset_delays, 3); + } else if (ret == -ENOENT) { + ret = 0; + } +#endif + + return ret; +} + +static const struct udevice_id dw_qos_eth_ids[] = { + { .compatible = "snps,dwc-qos-ethernet-4.10" }, + { } +}; + +U_BOOT_DRIVER(eth_dw_qos) = { + .name = "eth_dw_qos", + .id = UCLASS_ETH, + .of_match = dw_qos_eth_ids, + .ofdata_to_platdata = dw_qos_eth_ofdata_to_platdata, + .bind = dw_qos_eth_bind, + .probe = dw_qos_eth_probe, + .remove = dw_qos_eth_remove, + .ops = &dw_qos_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_qos_eth_dev), + .platdata_auto_alloc_size = sizeof(struct dw_qos_eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static struct pci_device_id supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, + { } +}; + +U_BOOT_PCI_DEVICE(eth_dw_qos, supported); +#endif diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h new file mode 100644 index 0000000..cfe12e1 --- /dev/null +++ b/drivers/net/dwc_eth_qos.h @@ -0,0 +1,219 @@ +/* + * (C) Copyright 2016 + * National Instruments + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DW_ETH_QOS_H +#define _DW_ETH_QOS_H + +#ifdef CONFIG_DM_GPIO +#include <asm-generic/gpio.h> +#endif + +#define CONFIG_TX_DESCR_NUM 16 +#define CONFIG_RX_DESCR_NUM 16 +#define CONFIG_ETH_BUFSIZE 2048 +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) + +struct eth_mac_regs { + u32 conf; /* 0x00 */ + u32 ext_conf; /* 0x04 */ + u32 reserved_1[42]; + u32 intstatus; /* 0xb0 */ + u32 intenable; /* 0xb4 */ + u32 rx_tx_status; /* 0xb8 */ + u32 reserved_2[81]; + u32 miiaddr; /* 0x200 */ + u32 miidata; /* 0x204 */ + u32 reserved_3[62]; + u32 macaddr0hi; /* 0x300 */ + u32 macaddr0lo; /* 0x304 */ +}; + +/* MAC configuration register definitions */ +#define FRAMEBURSTENABLE (1 << 18) +#define MII_PORTSELECT (1 << 15) +#define FES_100 (1 << 14) +#define DISABLERXOWN (1 << 10) +#define FULLDPLXMODE (1 << 13) +#define RXENABLE (1 << 0) +#define TXENABLE (1 << 1) + +/* MII address register definitions */ +#define MII_BUSY (1 << 0) +#define MII_WRITE (1 << 2) +#define MII_READ (3 << 2) +#define MII_CLKRANGE_60_100M (0) +#define MII_CLKRANGE_100_150M (0x1) +#define MII_CLKRANGE_20_35M (0x2) +#define MII_CLKRANGE_35_60M (0x3) +#define MII_CLKRANGE_150_250M (0x4) +#define MII_CLKRANGE_250_300M (0x5) + +#define MIIADDRSHIFT (21) +#define MIIREGSHIFT (16) +#define MIICLKSHIFT (8) +#define MII_REGMSK (0x1F << 16) +#define MII_ADDRMSK (0x1F << 21) +#define MII_CLKMSK (0xF << 8); + +struct eth_mtl_q0_regs { + u32 txopmode; /* 0x00 */ + u32 reserved_1[5]; + u32 rxopmode; /* 0x30 */ +}; + +#define DW_MTL_Q0_BASE_OFFSET (0xd00) + +/* TX queue 0 operation mode definitions */ +#define TXQ0_TSF (1 << 1) + +struct eth_dma_regs { + u32 dmamode; /* 0x00 */ + u32 sysbusmode; /* 0x04 */ + u32 status; /* 0x08 */ + u32 debug0; /* 0x0c */ + u32 debug1; /* 0x10 */ + u32 debug2; /* 0x14 */ + u32 reserved_1[3]; + u32 axi_ace_ar; /* 0x20 */ + u32 axi_ace_aw; /* 0x24 */ + u32 axibus; /* 0x28 */ + u32 reserved2[7]; + u32 currhosttxdesc; /* 0x48 */ + u32 currhostrxdesc; /* 0x4c */ + u32 currhosttxbuffaddr; /* 0x50 */ + u32 currhostrxbuffaddr; /* 0x54 */ +}; + +#define DW_DMA_BASE_OFFSET (0x1000) + +/* Default DMA Burst length */ +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 +#endif + +/* DMA mode register definitions */ +#define PRIORXTX_41 (3 << 12) +#define PRIORXTX_31 (2 << 12) +#define PRIORXTX_21 (1 << 12) +#define PRIORXTX_11 (0 << 12) +#define TXHIGHPRIO (1 << 11) +#define DMAMAC_SRST (1 << 0) + +struct eth_dma_ch0_regs { + u32 control; /* 0x00 */ + u32 txcontrol; /* 0x04 */ + u32 rxcontrol; /* 0x08 */ + u32 reserved_1; /* 0x0c */ + u32 txdescaddrhi; /* 0x10 */ + u32 txdescaddrlo; /* 0x14 */ + u32 rxdescaddrhi; /* 0x18 */ + u32 rxdescaddrlo; /* 0x1c */ + u32 txdesctail; /* 0x20 */ + u32 reserved_2; /* 0x24 */ + u32 rxdesctail; /* 0x28 */ + u32 txdescringlen; /* 0x2c */ + u32 rxdescringlen; /* 0x30 */ + u32 reserved_3[12]; + u32 status; /* 0x60 */ +}; + +#define DW_DMA_CH0_BASE_OFFSET (0x1100) + +/* DMA control definitions */ +#define PBLX8 (1 << 16) + +/* DMA TX control definitions */ +#define TXST (1 << 0) + +#define TXPBLSHIFT (16) +#define TXPBLMASK (0x3F << 16) + +/* DMA RX control definitions */ +#define RXST (1 << 0) + +#define RXPBLSHIFT (16) +#define RBSZSHIFT (1) +#define RXPBLMASK (0x3F << 16) +#define RBSZMASK (0x7FFF << 1) + +/* Descriptior related definitions */ +#define MAC_MAX_FRAME_SZ (1600) + +struct dmamacdescr { + u32 des0; + u32 des1; + u32 des2; + u32 des3; +} __packed; + +/* + * txrx_status definitions + */ + +/* tx status bits definitions */ +/* des2 */ +#define DESC_TXSTS_TXINT (1 << 31) + +/* des3 */ +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_CTXT (1 << 30) +#define DESC_TXSTS_TXFIRST (1 << 29) +#define DESC_TXSTS_TXLAST (1 << 28) +#define DESC_TXSTS_LENMASK (0x1FFF << 0) + +/* rx status bits definitions */ +/* des3 */ +#define DESC_RXSTS_OWNBYDMA (1 << 31) +#define DESC_RXSTS_CTXT (1 << 30) +#define DESC_RXSTS_RXFIRST (1 << 29) +#define DESC_RXSTS_RXLAST (1 << 28) +#define DESC_RXSTS_BUF1V (1 << 24) +#define DESC_RXSTS_ERROR (1 << 15) +#define DESC_RXSTS_FRMLENMSK (0x7FFF << 0) + +/* + * dmamac_cntl definitions + */ + +struct dw_qos_eth_dev { + struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; + struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + + u32 interface; + u32 max_speed; + u32 tx_currdescnum; + u32 rx_currdescnum; + + struct eth_mac_regs *mac_regs_p; + struct eth_dma_regs *dma_regs_p; + struct eth_dma_ch0_regs *dma_ch0_regs_p; + struct eth_mtl_q0_regs *mtl_q0_regs_p; +#ifndef CONFIG_DM_ETH + struct eth_device *dev; +#endif +#ifdef CONFIG_DM_GPIO + struct gpio_desc reset_gpio; +#endif + + struct phy_device *phydev; + struct mii_dev *bus; +}; + +#ifdef CONFIG_DM_ETH +struct dw_qos_eth_pdata { + struct eth_pdata eth_pdata; + u32 reset_delays[3]; +}; +#endif + +#endif -- 2.1.4

2 1

[U-Boot] [PATCH 1/2] net: zynq_gem: Modify the nwcfg bit definitions
by Michal Simek 01 Nov '16

01 Nov '16

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: Siva Durga Prasad Paladugu <sivadur(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/zynq_gem.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 8b7c1be5d909..0023b1689efe 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -53,16 +53,16 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ -#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ -#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ -#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ -#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ -#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x080000000 /* SGMII Enable */ -#define ZYNQ_GEM_NWCFG_PCS_SEL 0x000000800 /* PCS select */ +#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ +#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ +#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ +#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ +#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x80000000 /* SGMII Enable */ +#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ #ifdef CONFIG_ARM64 -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000100000 /* Div pclk by 64, max 160MHz */ +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ #else -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ #endif #ifdef CONFIG_ARM64 -- 1.9.1

2 3

[U-Boot] [PATCH v3 0/2] spl: Convert MMC raw mode sector options to Kconfig
by Sam Protsenko 01 Nov '16

01 Nov '16

2 3

[U-Boot] [PATCH v2 0/2] spl: Convert MMC raw mode sector options to Kconfig
by Sam Protsenko 01 Nov '16

01 Nov '16

1 4

[U-Boot] [PATCH v3 0/2] spl: Convert MMC raw mode sector options to Kconfig
by Sam Protsenko 01 Nov '16

01 Nov '16

1 0

[U-Boot] [PATCH 1/2] fsl/ddr: Revise erratum a009942 and clean related erratum
by Shengzhou Liu 01 Nov '16

01 Nov '16

- add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 ++- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +- arch/powerpc/include/asm/config_mpc85xx.h | 2 - board/freescale/ls1021aqds/ls1021aqds.c | 6 +- board/freescale/ls1021atwr/ls1021atwr.c | 5 +- drivers/ddr/fsl/ctrl_regs.c | 100 +++++++++++++++++++++++++++++- drivers/ddr/fsl/fsl_ddr_gen4.c | 23 ------- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 3 - include/fsl_ddr.h | 2 + include/fsl_ddr_sdram.h | 3 +- 10 files changed, 122 insertions(+), 35 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index b7a2e0c..19de15e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -25,6 +25,9 @@ #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif +#ifdef CONFIG_SYS_FSL_DDR +#include <fsl_ddr.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -400,7 +403,9 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 erratum_a009635(); #endif - +#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) + erratum_a009942_check_cpo(); +#endif #ifdef CONFIG_MP #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI) /* Check the psci version to determine if the psci is supported */ diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 53b3729..c1dbd9c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -45,7 +45,7 @@ #include <nand.h> #include <errno.h> #endif - +#include <fsl_ddr.h> #include "../../../../drivers/block/fsl_sata.h" #ifdef CONFIG_U_QE #include <fsl_qe.h> @@ -947,6 +947,10 @@ int cpu_init_r(void) #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + erratum_a009942_check_cpo(); +#endif + #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e8..1e62a9c 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -681,7 +681,6 @@ #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A004468 -#define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A007186 @@ -720,7 +719,6 @@ #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A007186 diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 4eb38a7..79078d2 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -22,7 +22,7 @@ #include <spl.h> #include <fsl_devdis.h> #include <fsl_validate.h> - +#include <fsl_ddr.h> #include "../common/sleep.h" #include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -433,7 +433,9 @@ int board_init(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif - +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + erratum_a009942_check_cpo(); +#endif major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* Set CCI-400 control override register to diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index d96fd77..4bebe22 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -30,7 +30,7 @@ #include <fsl_qe.h> #endif #include <fsl_validate.h> - +#include <fsl_ddr.h> DECLARE_GLOBAL_DATA_PTR; @@ -488,6 +488,9 @@ int board_init(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + erratum_a009942_check_cpo(); +#endif #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 24fd366..29d1970 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -5,7 +5,7 @@ */ /* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller. * Based on code from spd_sdram.c * Author: James Yang [at freescale.com] */ @@ -2305,6 +2305,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, unsigned int wrlvl_en; unsigned int ip_rev = 0; unsigned int unq_mrs_en = 0; + unsigned int ddr_freq; int cs_en = 1; memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); @@ -2526,5 +2527,102 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, ddr->debug[2] |= 0x00000200; /* set bit 22 */ #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4) + /* Erratum applies when accumulated ECC is used, or DBI is enabled */ +#define IS_ACC_ECC_EN(v) ((v) & 0x4) +#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) + if (has_erratum_a008378()) { + if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) || + IS_DBI(ddr->ddr_sdram_cfg_3)) + ddr->debug[28] |= (0x9 << 20); + } +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + /* the POR value of debug_29 register is zero */ + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + if (ddr_freq <= 1333) + ddr->debug[28] |= 0x0080006a; + else if (ddr_freq <= 1600) + ddr->debug[28] |= 0x0070006f; + else if (ddr_freq <= 1867) + ddr->debug[28] |= 0x00700076; + else if (ddr_freq <= 2133) + ddr->debug[28] |= 0x0060007b; + if (popts->cpo_sample) + ddr->debug[28] = (ddr->debug[28] & 0xffffff00) | + popts->cpo_sample; +#endif + return check_fsl_memctl_config_regs(ddr); } + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 +/* + * This additional workaround of A009942 checks the condition to determine if + * the CPO value set by the existing A009942 workaround needs to be updated. + * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with + * expected optimal value, the optimal value is highly board dependent. + */ +void erratum_a009942_check_cpo(void) +{ + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal; + u32 min_cpo = 0, max_cpo = 0; + u32 sdram_cfg, i, tmp, lanes, ddr_type; + bool update_cpo = false, has_ecc = false; + + sdram_cfg = ddr_in32(&ddr->sdram_cfg); + if (sdram_cfg & SDRAM_CFG_32_BE) + lanes = 4; + else if (sdram_cfg & SDRAM_CFG_16_BE) + lanes = 2; + else + lanes = 8; + + if (sdram_cfg & SDRAM_CFG_ECC_EN) + has_ecc = true; + + /* determine the maximum and minimum CPO values */ + for (i = 9; i < 9 + lanes / 2; i++) { + cpo = ddr_in32(&ddr->debug[i]); + cpo_e = cpo >> 24; + cpo_o = (cpo >> 8) & 0xff; + tmp = min(cpo_e, cpo_o); + if (tmp < min_cpo) + min_cpo = tmp; + tmp = max(cpo_e, cpo_o); + if (tmp > max_cpo) + max_cpo = tmp; + } + + if (has_ecc) { + cpo = ddr_in32(&ddr->debug[13]); + cpo = cpo >> 24; + if (cpo << min_cpo) + min_cpo = cpo; + if (cpo > max_cpo) + max_cpo = cpo; + } + + cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; + cpo_optimal = ((max_cpo + min_cpo) >> 1) + 0x27; + debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal, + cpo_target); + debug("max_cpo = 0x%x, min_cpo = 0x%x\n", max_cpo, min_cpo); + + ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> + SDRAM_CFG_SDRAM_TYPE_SHIFT; + if (ddr_type == SDRAM_TYPE_DDR4) + update_cpo = (min_cpo + 0x3b) < cpo_target ? true : false; + else if (ddr_type == SDRAM_TYPE_DDR3) + update_cpo = (min_cpo + 0x3f) < cpo_target ? true : false; + + if (update_cpo) { + printf("WARN: This board needs to optimize debug_29, pls set "); + printf("\'popts->cpo_sample = 0x%x\' in <board>/ddr.c\n", + cpo_optimal); + } +} +#endif diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 042af09..2a5066a 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -230,16 +230,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[i], regs->debug[i]); } } -#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 - /* Erratum applies when accumulated ECC is used, or DBI is enabled */ -#define IS_ACC_ECC_EN(v) ((v) & 0x4) -#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) - if (has_erratum_a008378()) { - if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || - IS_DBI(regs->ddr_sdram_cfg_3)) - ddr_setbits32(&ddr->debug[28], 0x9 << 20); - } -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 /* Part 1 of 2 */ @@ -277,19 +267,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[25], temp32); #endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 - ddr_freq = get_ddr_freq(ctrl_num) / 1000000; - tmp = ddr_in32(&ddr->debug[28]); - if (ddr_freq <= 1333) - ddr_out32(&ddr->debug[28], tmp | 0x0080006a); - else if (ddr_freq <= 1600) - ddr_out32(&ddr->debug[28], tmp | 0x0070006f); - else if (ddr_freq <= 1867) - ddr_out32(&ddr->debug[28], tmp | 0x00700076); - else if (ddr_freq <= 2133) - ddr_out32(&ddr->debug[28], tmp | 0x0060007b); -#endif - #ifdef CONFIG_SYS_FSL_ERRATUM_A010165 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; if ((ddr_freq > 1900) && (ddr_freq < 2300)) { diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 653b7f0..1bfb9d4 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -174,9 +174,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->debug[i], regs->debug[i]); } } -#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 - out_be32(&ddr->debug[28], 0x30003000); -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 out_be32(&ddr->debug[12], 0x00000015); diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 3351acd..0c3be0e 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -138,4 +138,6 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr); + +void erratum_a009942_check_cpo(void); #endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 36bd9d7..1404c57 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -374,7 +374,8 @@ typedef struct memctl_options_s { unsigned int additive_latency_override_value; unsigned int clk_adjust; /* */ - unsigned int cpo_override; + unsigned int cpo_override; /* override timing_cfg_2[CPO]*/ + unsigned int cpo_sample; /* optimize debug_29[24:31] */ unsigned int write_data_delay; /* DQS adjust */ unsigned int cswl_override; -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v1] ARM: at91: add default config file for sama5d36ek CMP board
by Wenyou Yang 01 Nov '16

01 Nov '16

The sama5d36ek CMP board is the variant of sama5d3xek board. It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and some power rail. Its main purpose is used to measure the power consumption. As those changes are done in at91bootstrap, in U-Boot, use another device tree file, no code to change. As there is additional power consumption due to the USB Host and USB Device enabled, for the power consumption measurement, disable the USB host and device. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> This patch is based on [PATCH v1 0/7] board: sama5d3: convert boards to support DM/DT http://lists.denx.de/pipermail/u-boot/2016-October/271253.html --- configs/sama5d36ek_cmp_mmc_defconfig | 58 ++++++++++++++++++++++++++++++ configs/sama5d36ek_cmp_nandflash_defconfig | 57 +++++++++++++++++++++++++++++ configs/sama5d36ek_cmp_spiflash_defconfig | 57 +++++++++++++++++++++++++++++ include/configs/sama5d3xek.h | 2 +- 4 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 configs/sama5d36ek_cmp_mmc_defconfig create mode 100644 configs/sama5d36ek_cmp_nandflash_defconfig create mode 100644 configs/sama5d36ek_cmp_spiflash_defconfig diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig new file mode 100644 index 0000000..ee72c59 --- /dev/null +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -0,0 +1,58 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig new file mode 100644 index 0000000..aabbf4a --- /dev/null +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig new file mode 100644 index 0000000..e4131d9 --- /dev/null +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_SAMA5D3XEK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp" +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_BASE=0xffffee00 +CONFIG_DEBUG_UART_CLOCK=0 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_SPI=y +CONFIG_LCD=y diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 5839fff..35a287c 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -114,7 +114,6 @@ #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI #define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#define CONFIG_DOS_PARTITION #endif /* USB device */ @@ -123,6 +122,7 @@ #define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK" #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_DOS_PARTITION #define CONFIG_FAT_WRITE #endif -- 2.7.4

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