November 2016 - U-Boot

[U-Boot] [PATCH] Fix fastboot boot address
by Peter.Chubb＠data61.csiro.au 30 Dec '16

30 Dec '16

Fastboot loads an image at CONFIG_FASTBOOT_BUF_ADDR, but currently tells do_bootm() to look for an image at $loadaddr. This breaks if CONFIG_FASTBOOT_BUF_ADDR is different from the current user-set loadaddr. Instead, tell do_bootm() to pick up the image where it was laoded. Signed-off-by: Peter Chubb <peter.chubb(a)data61.csiro.au> --- drivers/usb/gadget/f_fastboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 2160b1c..6d02248 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -553,7 +553,7 @@ static void do_bootm_on_complete(struct usb_ep *ep, struct usb_request *req) puts("Booting kernel..\n"); - sprintf(boot_addr_start, "0x%lx", load_addr); + sprintf(boot_addr_start, "0x%lx", CONFIG_FASTBOOT_BUF_ADDR); do_bootm(NULL, 0, 2, bootm_args); /* This only happens if image is somehow faulty so we start over */ -- 2.9.3

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[U-Boot] [PATCH 2/7] ext4: determine group descriptor size for 64bit feature
by Stefan Brüns 27 Dec '16

27 Dec '16

If EXT4_FEATURE_INCOMPAT_64BIT is set, the descriptor can be read from the superblocks, otherwise it defaults to 32. Signed-off-by: Stefan Brüns <stefan.bruens(a)rwth-aachen.de> --- fs/ext4/ext4_common.c | 18 ++++++++++++++---- include/ext4fs.h | 2 ++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index a78b0b8..416a9db 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -2233,13 +2233,23 @@ int ext4fs_mount(unsigned part_length) goto fail; } - if (le32_to_cpu(data->sblock.revision_level) == 0) + if (le32_to_cpu(data->sblock.revision_level) == 0) { fs->inodesz = 128; - else + } else { + debug("EXT4 features COMPAT: %08x INCOMPAT: %08x RO_COMPAT: %08x\n", + __le32_to_cpu(data->sblock.feature_compatibility), + __le32_to_cpu(data->sblock.feature_incompat), + __le32_to_cpu(data->sblock.feature_ro_compat)); + fs->inodesz = le16_to_cpu(data->sblock.inode_size); + fs->gdsize = le32_to_cpu(data->sblock.feature_incompat) & + EXT4_FEATURE_INCOMPAT_64BIT ? + le16_to_cpu(data->sblock.descriptor_size) : 32; + } - debug("EXT2 rev %d, inode_size %d\n", - le32_to_cpu(data->sblock.revision_level), fs->inodesz); + debug("EXT2 rev %d, inode_size %d, descriptor size %d\n", + le32_to_cpu(data->sblock.revision_level), + fs->inodesz, fs->gdsize); data->diropen.data = data; data->diropen.ino = 2; diff --git a/include/ext4fs.h b/include/ext4fs.h index 6e31c73..7e1ee6c 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -87,6 +87,8 @@ struct ext_filesystem { uint32_t inodesz; /* Sectors per Block */ uint32_t sect_perblk; + /* Group Descriptor size */ + uint16_t gdsize; /* Group Descriptor Block Number */ uint32_t gdtable_blkno; /* Total block groups of partition */ -- 2.10.0

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[U-Boot] [PATCH v3 0/9] From Simon:
by Simon Glass 26 Dec '16

26 Dec '16

This v3 patch is an update on Sjoerd's original v2 series from Feburary. I have dealt with the changes requested at the time, and adjusted the way that the speed change is handled. Tested on firefly-rk3288, rock2. Original cover letter: To add support I've taken a slightly different approach then some of the other boards with a designware IP block, by creating a new driver to take care of the platfrom glue which subclasses the main designware driver instead of adding the compatibility string the designware driver directly and doing the SoC specific setup in the board files. This seems quite a bit more elegant in a device model based world. I've only tested this series on a Radxa Rock 2 board, it would be great if someone could test this on other boards with the designware IP especially for those with the reset GPIO in devicetree (e.g. some of the Allwinner boards). Compared to the first one round the pinctrl related bits were dropped as RK3288 now has a full pinctrl driver. Furthermore the started hook in the designware driver was renamed to fix_mac_speed in line with what linux uses and moved to the dw_link_adjust function. Changes in v3: - Add a few new patches - Add comments for struct gmac_rk3288_platdata - Add new patch to adjust dw_adjust_link() to return an error - Add new patch to enable networking on evb-rk3288 - Add new patch to export the operation functions - Add new patch to split the link init into a separate function - Adjust binding to use r/tx-delay instead of r/tx_delay - Drop the 'net: designware: Add a fix_mac_speed hook' patch - Sort includes - Use debug() instead of printf() for error - Use function calls instead of fix_mac_speed() hook - Use new clk interface Changes in v2: - Adjust to new hook name - Fix various coding style nits Simon Glass (4): net: designware: Adjust dw_adjust_link() to return an error net: designware: Split the link init into a separate function net: designware: Export the operation functions rockchip: evb-rk3339: Enable DHCP Sjoerd Simons (5): net: designware: Export various functions/struct to allow subclassing net: gmac_rk3288: Add RK3288 GMAC driver rockchip: Enable networking support on rock2 and firefly rockchip: Add PXE and DHCP to the default boot targets rockchip: Drop Ethernet from the TODO configs/evb-rk3399_defconfig | 3 + configs/firefly-rk3288_defconfig | 4 + configs/rock2_defconfig | 4 + doc/README.rockchip | 1 - drivers/net/Kconfig | 7 ++ drivers/net/Makefile | 1 + drivers/net/designware.c | 57 ++++++++++---- drivers/net/designware.h | 13 ++++ drivers/net/gmac_rk3288.c | 154 ++++++++++++++++++++++++++++++++++++++ include/configs/rockchip-common.h | 4 +- 10 files changed, 230 insertions(+), 18 deletions(-) create mode 100644 drivers/net/gmac_rk3288.c -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH] spi: Zap armada100_spi.c and env
by Jagan Teki 24 Dec '16

24 Dec '16

armada100_spi.c and related env is zapping becuase of "no DM conversion". Cc: Ajay Bhargav <ajay.bhargav(a)einfochips.com> Signed-off-by: Jagan Teki <jagan(a)openedev.com> --- Note: If someone want this to present, just respond with proper timeline. configs/gplugd_defconfig | 5 -- drivers/spi/Makefile | 1 - drivers/spi/armada100_spi.c | 203 ------------------------------------------- include/configs/gplugd.h | 9 +- scripts/config_whitelist.txt | 1 - 5 files changed, 1 insertion(+), 218 deletions(-) delete mode 100644 drivers/spi/armada100_spi.c diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig index 59c9fdf..3d98f8d 100644 --- a/configs/gplugd_defconfig +++ b/configs/gplugd_defconfig @@ -4,9 +4,7 @@ CONFIG_IDENT_STRING="\nMarvell-gplugD" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set -CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set -CONFIG_CMD_SF=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set @@ -16,9 +14,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_ATMEL=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 247c5f6..9e1f8df 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o -obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c deleted file mode 100644 index 53aaf95..0000000 --- a/drivers/spi/armada100_spi.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Based on SSP driver - * Written-by: Lei Wen <leiwen(a)marvell.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <malloc.h> -#include <spi.h> - -#include <asm/io.h> -#include <asm/arch/spi.h> -#include <asm/gpio.h> - -#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave) - -struct armd_spi_slave { - struct spi_slave slave; - struct ssp_reg *spi_reg; - u32 cr0, cr1; - u32 int_cr1; - u32 clear_sr; - const void *tx; - void *rx; - int gpio_cs_inverted; -}; - -static int spi_armd_write(struct armd_spi_slave *pss) -{ - int wait_timeout = SSP_FLUSH_NUM; - while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF)) - ; - if (!wait_timeout) { - debug("%s: timeout error\n", __func__); - return -1; - } - - if (pss->tx != NULL) { - writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr); - ++pss->tx; - } else { - writel(0, &pss->spi_reg->ssdr); - } - return 0; -} - -static int spi_armd_read(struct armd_spi_slave *pss) -{ - int wait_timeout = SSP_FLUSH_NUM; - while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE)) - ; - if (!wait_timeout) { - debug("%s: timeout error\n", __func__); - return -1; - } - - if (pss->rx != NULL) { - *(u8 *)pss->rx = readl(&pss->spi_reg->ssdr); - ++pss->rx; - } else { - readl(&pss->spi_reg->ssdr); - } - return 0; -} - -static int spi_armd_flush(struct armd_spi_slave *pss) -{ - unsigned long limit = SSP_FLUSH_NUM; - - do { - while (readl(&pss->spi_reg->sssr) & SSSR_RNE) - readl(&pss->spi_reg->ssdr); - } while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--); - - writel(SSSR_ROR, &pss->spi_reg->sssr); - - return limit; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - - gpio_set_value(slave->cs, pss->gpio_cs_inverted); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - - gpio_set_value(slave->cs, !pss->gpio_cs_inverted); -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct armd_spi_slave *pss; - - pss = spi_alloc_slave(struct armd_spi_slave, bus, cs); - if (!pss) - return NULL; - - pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT); - - pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE; - - pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) | - (SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT); - pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); - pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) - | (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); - - pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; - pss->clear_sr = SSSR_ROR | SSSR_TINT; - - pss->gpio_cs_inverted = mode & SPI_CS_HIGH; - gpio_set_value(cs, !pss->gpio_cs_inverted); - - return &pss->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - - free(pss); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - if (spi_armd_flush(pss) == 0) - return -1; - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - struct armd_spi_slave *pss = to_armd_spi_slave(slave); - uint bytes = bitlen / 8; - unsigned long limit; - int ret = 0; - - if (bitlen == 0) - goto done; - - /* we can only do 8 bit transfers */ - if (bitlen % 8) { - flags |= SPI_XFER_END; - goto done; - } - - pss->tx = dout; - pss->rx = din; - - if (flags & SPI_XFER_BEGIN) { - spi_cs_activate(slave); - writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1); - writel(TIMEOUT_DEF, &pss->spi_reg->ssto); - writel(pss->cr0, &pss->spi_reg->sscr0); - } - - while (bytes--) { - limit = SSP_FLUSH_NUM; - ret = spi_armd_write(pss); - if (ret) - break; - - while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--) - udelay(1); - - ret = spi_armd_read(pss); - if (ret) - break; - } - - done: - if (flags & SPI_XFER_END) { - /* Stop SSP */ - writel(pss->clear_sr, &pss->spi_reg->sssr); - clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1); - writel(0, &pss->spi_reg->ssto); - spi_cs_deactivate(slave); - } - - return ret; -} diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index c1b43fd..92e2117 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -72,11 +72,6 @@ /* GPIO Configuration for PHY */ #define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */ -/* SPI Support */ -#define CONFIG_ARMADA100_SPI -#define CONFIG_ENV_SPI_CS 110 -#define CONFIG_SYS_SSP_PORT 2 - /* Flash Support */ /* @@ -95,10 +90,8 @@ /* * Environment variables configurations */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE 0x4000 +#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_OFFSET 0x07C000 #ifdef CONFIG_CMD_USB #define CONFIG_USB_EHCI diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 9851251..6c7f8e0 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -178,7 +178,6 @@ CONFIG_ARIA_FPGA CONFIG_ARM926EJS CONFIG_ARMADA100 CONFIG_ARMADA100_FEC -CONFIG_ARMADA100_SPI CONFIG_ARMADA168 CONFIG_ARMADA_39X CONFIG_ARMCORTEXA9 -- 1.9.1

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[U-Boot] [PATCH 00/10] driver model bring-up of dwc3 usb peripheral
by Mugunthan V N 20 Dec '16

20 Dec '16

This patch series enables dwc3 usb driver to adopt driver model. This has been tested on AM437x evm sk (logs [1]) by loading kernel through usb ether Also pushed a branch for testing [2] [1] - http://pastebin.ubuntu.com/15391169/ [2] - git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-dwc3 Kishon Vijay Abraham I (1): configs: am43xx: Add am43xx_evm_usbspl_defconfig Mugunthan V N (8): drivers: usb: dwc3: remove devm_zalloc from linux_compact drivers: usb: dwc3-omap: move usb_gadget_handle_interrupts from board files to drivers am437x: board: do not register usb devices when CONFIG_DM_USB is defined dra7xx: board: do not register usb devices when CONFIG_DM_USB is defined drivers: usb: dwc3: add ti dwc3 misc driver for wrapper drivers: usb: common: add support to get maximum speed from dt drivers: usb: dwc3: add ti dwc3 peripheral driver with driver model support defconfig: am437x_sk_evm: enable usb driver model Tom Rini (1): am43xx: Add USB device boot support to SPL board/ti/am43xx/MAINTAINERS | 1 + board/ti/am43xx/board.c | 52 +++++--- board/ti/am57xx/board.c | 11 -- board/ti/dra7xx/evm.c | 13 +- configs/am437x_sk_evm_defconfig | 4 + configs/am43xx_evm_usbspl_defconfig | 9 ++ drivers/Makefile | 2 + drivers/usb/common/common.c | 29 +++++ drivers/usb/dwc3/core.c | 64 +++++++++- drivers/usb/dwc3/core.h | 6 + drivers/usb/dwc3/dwc3-omap.c | 230 +++++++++++++++++++++++++++++++++++- drivers/usb/dwc3/gadget.c | 2 +- drivers/usb/dwc3/linux-compat.h | 5 - drivers/usb/dwc3/ti_usb_phy.c | 1 + drivers/usb/gadget/gadget_chips.h | 2 + include/configs/am43xx_evm.h | 13 ++ include/linux/usb/otg.h | 9 ++ 17 files changed, 406 insertions(+), 47 deletions(-) create mode 100644 configs/am43xx_evm_usbspl_defconfig -- 2.7.2.333.g70bd996

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[U-Boot] [PATCH 1/4] fsl/ddr: Fix compiling warning
by Shengzhou Liu 16 Dec '16

16 Dec '16

Fix following warning in case multiple erratum macro was not defined. warning: unused variable 'tmp' warning: unused variable 'ddr_freq' Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- drivers/ddr/fsl/fsl_ddr_gen4.c | 43 +++++++++++++++++------------------------- 1 file changed, 17 insertions(+), 26 deletions(-) diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 042af09..2e36c75 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -47,13 +47,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, { unsigned int i, bus_width; struct ccsr_ddr __iomem *ddr; - u32 temp_sdram_cfg; + u32 temp32; u32 total_gb_size_per_controller; int timeout; -#if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A009801) - u32 temp32; -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 u32 mr6; @@ -61,11 +57,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ u32 *vref_seq = vref_seq1; #endif -#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \ - defined(CONFIG_SYS_FSL_ERRATUM_A010165) - ulong ddr_freq; - u32 tmp; -#endif #ifdef CONFIG_FSL_DDR_BIST u32 mtcr, err_detect, err_sbe; u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; @@ -291,10 +282,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A010165 - ddr_freq = get_ddr_freq(ctrl_num) / 1000000; - if ((ddr_freq > 1900) && (ddr_freq < 2300)) { - tmp = ddr_in32(&ddr->debug[28]); - ddr_out32(&ddr->debug[28], tmp | 0x000a0000); + temp32 = get_ddr_freq(ctrl_num) / 1000000; + if ((temp32 > 1900) && (temp32 < 2300)) { + temp32 = ddr_in32(&ddr->debug[28]); + ddr_out32(&ddr->debug[28], temp32 | 0x000a0000); } #endif /* @@ -312,9 +303,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, step2: /* Set, but do not enable the memory */ - temp_sdram_cfg = regs->ddr_sdram_cfg; - temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); - ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); + temp32 = regs->ddr_sdram_cfg; + temp32 &= ~(SDRAM_CFG_MEM_EN); + ddr_out32(&ddr->sdram_cfg, temp32); /* * 500 painful micro-seconds must elapse between @@ -329,18 +320,18 @@ step2: #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { /* enter self-refresh */ - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); - temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; - ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + temp32 = ddr_in32(&ddr->sdram_cfg_2); + temp32 |= SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp32); /* do board specific memory setup */ board_mem_sleep_setup(); - temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); } else #endif - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; /* Let the controller go */ - ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN); mb(); isb(); @@ -483,9 +474,9 @@ step2: #ifdef CONFIG_DEEP_SLEEP if (is_warm_boot()) { /* exit self-refresh */ - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); - temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; - ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + temp32 = ddr_in32(&ddr->sdram_cfg_2); + temp32 &= ~SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp32); } #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v4] arm: imx: add i.MX53 Beckhoff CX9020 Embedded PC
by linux-kernel-dev＠beckhoff.com 16 Dec '16

16 Dec '16

From: Patrick Bruenn <p.bruenn(a)beckhoff.com> Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by: Patrick Bruenn <p.bruenn(a)beckhoff.com> --- Version 4 should address most of the issues Stefan, Jagan and Simon pointed out. Missing: - moving CONFIG_FSL_ESDHC from mx53cx9020.h to defconfig, which would require DM_GPIO. But as soon as I enable that my imx53 device does not boot up and shows nothing on uart anymore. - and because of that DM_GPIO issue I am unable to use DM_LED_GPIO - I couldn't get DM_VIDEO working, too. If you have any hint or reference on how to get that running on imx53, please let me know and I will improve that. Changes in v4: - move TARGET_MX53CX9020 from arch/arm/Kconfig to arch/arm/cpu/armv7/mx5/Kconfig - move CONFIG_MX53 to arch/arm/cpu/armv7/mx5/Kconfig - move CONFIG_MXC_UART to mx53cx9020_defconfig - move CONFIG_FEC_MXC to mx53cx9020_defconfig - remove redundant SYS_SOC from board/beckhoff/mx53cx9020/Kconfig - enable MXC_UART for MX5 devices - enable FEC_MXC for MX5 devices - group ethernet related configs in mx53cx9020.h - make clear mx53cx9020 was derived from the u-boot version of mx53loco not from kernel code - replace 'loadccat' with 'fpga load' - add pinctrl-imx5 driver and use device tree for pinmux configuration on cx9020 Changes in v3: - replace CONFIG_TARGET_MX53CX9020 with CONFIG_MX53 in dts/Makefile - remove redundant CONFIG_DISPLAY_BOARDINFO from mx53cx9020.h Changes in v2: - remove #include <asm/errno.h> from mx53cx9020.c - remove obsolete CONFIG_CMD_CCAT from mx53cx9020.h arch/arm/cpu/armv7/mx5/Kconfig | 8 + arch/arm/dts/Makefile | 2 + arch/arm/dts/imx53-cx9020.dts | 190 ++++ arch/arm/dts/imx53-pinfunc.h | 1189 ++++++++++++++++++++++++++ arch/arm/dts/imx53.dtsi | 110 +++ board/beckhoff/mx53cx9020/Kconfig | 12 + board/beckhoff/mx53cx9020/MAINTAINERS | 6 + board/beckhoff/mx53cx9020/Makefile | 9 + board/beckhoff/mx53cx9020/imximage.cfg | 82 ++ board/beckhoff/mx53cx9020/mx53cx9020.c | 367 ++++++++ board/beckhoff/mx53cx9020/mx53cx9020_video.c | 49 ++ configs/mx53cx9020_defconfig | 29 + drivers/fpga/Kconfig | 20 + drivers/net/Kconfig | 2 +- drivers/pinctrl/nxp/Kconfig | 14 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx5.c | 44 + drivers/serial/Kconfig | 2 +- include/configs/mx53cx9020.h | 202 +++++ include/dt-bindings/clock/imx5-clock.h | 219 +++++ 20 files changed, 2555 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx53-cx9020.dts create mode 100644 arch/arm/dts/imx53-pinfunc.h create mode 100644 arch/arm/dts/imx53.dtsi create mode 100644 board/beckhoff/mx53cx9020/Kconfig create mode 100644 board/beckhoff/mx53cx9020/MAINTAINERS create mode 100644 board/beckhoff/mx53cx9020/Makefile create mode 100644 board/beckhoff/mx53cx9020/imximage.cfg create mode 100644 board/beckhoff/mx53cx9020/mx53cx9020.c create mode 100644 board/beckhoff/mx53cx9020/mx53cx9020_video.c create mode 100644 configs/mx53cx9020_defconfig create mode 100644 drivers/pinctrl/nxp/pinctrl-imx5.c create mode 100644 include/configs/mx53cx9020.h create mode 100644 include/dt-bindings/clock/imx5-clock.h diff --git a/arch/arm/cpu/armv7/mx5/Kconfig b/arch/arm/cpu/armv7/mx5/Kconfig index 9f250c6..5fb5513 100644 --- a/arch/arm/cpu/armv7/mx5/Kconfig +++ b/arch/arm/cpu/armv7/mx5/Kconfig @@ -18,11 +18,19 @@ config TARGET_USBARMORY bool "Support USB armory" select CPU_V7 +config TARGET_MX53CX9020 + bool "Support CX9020" + select CPU_V7 + select MX53 + select DM + select DM_SERIAL + endchoice config SYS_SOC default "mx5" +source "board/beckhoff/mx53cx9020/Kconfig" source "board/inversepath/usbarmory/Kconfig" endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 61eb852..cd00d53 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -282,6 +282,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ pcm052.dtb \ bk4r1.dtb +dtb-$(CONFIG_MX53) += imx53-cx9020.dtb + dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6dl-icore.dtb \ imx6q-icore.dtb diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts new file mode 100644 index 0000000..9610301 --- /dev/null +++ b/arch/arm/dts/imx53-cx9020.dts @@ -0,0 +1,190 @@ +/* + * Copyright 2016 Beckhoff Automation + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include "imx53.dtsi" + +#define MX53_PAD_EIM_D26__UART2_RXD_MUX 0x144 0x48c 0x880 0x2 0x0 +#define MX53_PAD_EIM_D27__UART2_TXD_MUX 0x148 0x490 0x000 0x2 0x0 +#define MX53_PAD_EIM_D28__UART2_RTS 0x14c 0x494 0x87c 0x2 0x0 +#define MX53_PAD_EIM_D29__UART2_CTS 0x150 0x498 0x000 0x2 0x0 + +/ { + model = "Beckhoff CX9020-0100 i.MX53"; + compatible = "fsl,imx53-qsb", "fsl,imx53"; + + chosen { + stdout-path = &uart2; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-qsb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 + MX53_PAD_GPIO_8__GPIO1_8 0x80000000 + MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 + MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 + MX53_PAD_GPIO_1__GPIO1_1 0x80000000 + MX53_PAD_GPIO_4__GPIO1_4 0x80000000 + MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 + MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 + MX53_PAD_GPIO_16__GPIO7_11 0x80000000 + + MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 + MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x80000000 + MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x80000000 + MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 + MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x80000000 + MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x80000000 + MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x80000000 + MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x80000000 + MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x80000000 + MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 + MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x80000000 + MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x80000000 + MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x80000000 + MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x80000000 + MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x80000000 + MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x80000000 + MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x80000000 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 + MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0xa4 + MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0xa4 + MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0xa4 + MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0xa4 + MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0xa4 + MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0xa4 + MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0xa4 + MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0xa4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0xa4 + MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0xa4 + MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0xa4 + MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0xa4 + MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0xa4 + MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0xa4 + MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0xa4 + MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0xa4 + MX53_PAD_NANDF_CLE__GPIO6_7 0x00000001 + MX53_PAD_NANDF_WP_B__GPIO6_9 0x00000001 + MX53_PAD_NANDF_ALE__GPIO6_8 0x00000001 + + MX53_PAD_EIM_D23__GPIO3_23 0x80000000 + + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 + + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + + MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec + MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec + + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5 + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5 + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5 + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5 + MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x5 + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5 + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5 + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5 + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5 + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5 + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5 + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5 + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5 + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5 + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5 + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5 + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5 + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5 + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5 + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5 + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5 + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5 + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5 + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5 + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5 + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5 + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5 + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5 + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_EIM_D26__UART2_RXD_MUX 0x1e4 + MX53_PAD_EIM_D27__UART2_TXD_MUX 0x1e4 + MX53_PAD_EIM_D28__UART2_RTS 0x1e4 + MX53_PAD_EIM_D29__UART2_CTS 0x1e4 + >; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + uart-has-rtscts; + fsl,dte-mode; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx53-pinfunc.h b/arch/arm/dts/imx53-pinfunc.h new file mode 100644 index 0000000..aec406b --- /dev/null +++ b/arch/arm/dts/imx53-pinfunc.h @@ -0,0 +1,1189 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX53_PINFUNC_H +#define __DTS_IMX53_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 +#define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 +#define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 +#define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 +#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 +#define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 +#define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 +#define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x024 0x34c 0x758 0x2 0x0 +#define MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x024 0x34c 0x000 0x4 0x0 +#define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 +#define MX53_PAD_KEY_COL0__FEC_RDATA_3 0x024 0x34c 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST 0x024 0x34c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW0__KPP_ROW_0 0x028 0x350 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW0__GPIO4_7 0x028 0x350 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x028 0x350 0x74c 0x2 0x0 +#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x028 0x350 0x890 0x4 0x1 +#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 +#define MX53_PAD_KEY_ROW0__FEC_TX_ER 0x028 0x350 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL1__KPP_COL_1 0x02c 0x354 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL1__GPIO4_8 0x02c 0x354 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x02c 0x354 0x75c 0x2 0x0 +#define MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x02c 0x354 0x000 0x4 0x0 +#define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 +#define MX53_PAD_KEY_COL1__FEC_RX_CLK 0x02c 0x354 0x808 0x6 0x0 +#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY 0x02c 0x354 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW1__KPP_ROW_1 0x030 0x358 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW1__GPIO4_9 0x030 0x358 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x030 0x358 0x748 0x2 0x0 +#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x030 0x358 0x898 0x4 0x1 +#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 +#define MX53_PAD_KEY_ROW1__FEC_COL 0x030 0x358 0x800 0x6 0x0 +#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID 0x030 0x358 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL2__KPP_COL_2 0x034 0x35c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL2__GPIO4_10 0x034 0x35c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL2__CAN1_TXCAN 0x034 0x35c 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL2__FEC_MDIO 0x034 0x35c 0x804 0x4 0x0 +#define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 +#define MX53_PAD_KEY_COL2__FEC_RDATA_2 0x034 0x35c 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE 0x034 0x35c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW2__KPP_ROW_2 0x038 0x360 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW2__GPIO4_11 0x038 0x360 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x038 0x360 0x760 0x2 0x0 +#define MX53_PAD_KEY_ROW2__FEC_MDC 0x038 0x360 0x000 0x4 0x0 +#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 +#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x038 0x360 0x000 0x6 0x0 +#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR 0x038 0x360 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL3__KPP_COL_3 0x03c 0x364 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL3__GPIO4_12 0x03c 0x364 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL3__USBOH3_H2_DP 0x03c 0x364 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL3__SPDIF_IN1 0x03c 0x364 0x870 0x3 0x0 +#define MX53_PAD_KEY_COL3__I2C2_SCL 0x03c 0x364 0x81c 0x4 0x0 +#define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 +#define MX53_PAD_KEY_COL3__FEC_CRS 0x03c 0x364 0x000 0x6 0x0 +#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK 0x03c 0x364 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW3__KPP_ROW_3 0x040 0x368 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW3__GPIO4_13 0x040 0x368 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM 0x040 0x368 0x000 0x2 0x0 +#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK 0x040 0x368 0x768 0x3 0x0 +#define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0 +#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 +#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP 0x040 0x368 0x77c 0x6 0x0 +#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 0x040 0x368 0x000 0x7 0x0 +#define MX53_PAD_KEY_COL4__KPP_COL_4 0x044 0x36c 0x000 0x0 0x0 +#define MX53_PAD_KEY_COL4__GPIO4_14 0x044 0x36c 0x000 0x1 0x0 +#define MX53_PAD_KEY_COL4__CAN2_TXCAN 0x044 0x36c 0x000 0x2 0x0 +#define MX53_PAD_KEY_COL4__IPU_SISG_4 0x044 0x36c 0x000 0x3 0x0 +#define MX53_PAD_KEY_COL4__UART5_RTS 0x044 0x36c 0x894 0x4 0x0 +#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 0x0 +#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 0x044 0x36c 0x000 0x7 0x0 +#define MX53_PAD_KEY_ROW4__KPP_ROW_4 0x048 0x370 0x000 0x0 0x0 +#define MX53_PAD_KEY_ROW4__GPIO4_15 0x048 0x370 0x000 0x1 0x0 +#define MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x048 0x370 0x764 0x2 0x0 +#define MX53_PAD_KEY_ROW4__IPU_SISG_5 0x048 0x370 0x000 0x3 0x0 +#define MX53_PAD_KEY_ROW4__UART5_CTS 0x048 0x370 0x000 0x4 0x0 +#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 0x048 0x370 0x000 0x5 0x0 +#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID 0x048 0x370 0x000 0x7 0x0 +#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x04c 0x378 0x000 0x0 0x0 +#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 0x04c 0x378 0x000 0x1 0x0 +#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR 0x04c 0x378 0x000 0x2 0x0 +#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 0x04c 0x378 0x000 0x5 0x0 +#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 0x04c 0x378 0x000 0x6 0x0 +#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID 0x04c 0x378 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x050 0x37c 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN15__GPIO4_17 0x050 0x37c 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC 0x050 0x37c 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 0x050 0x37c 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 0x050 0x37c 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID 0x050 0x37c 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x054 0x380 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN2__GPIO4_18 0x054 0x380 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD 0x054 0x380 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 0x054 0x380 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 0x054 0x380 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION 0x054 0x380 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x058 0x384 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN3__GPIO4_19 0x058 0x384 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS 0x058 0x384 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 0x058 0x384 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 0x058 0x384 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG 0x058 0x384 0x000 0x7 0x0 +#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 0x05c 0x388 0x000 0x0 0x0 +#define MX53_PAD_DI0_PIN4__GPIO4_20 0x05c 0x388 0x000 0x1 0x0 +#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD 0x05c 0x388 0x000 0x2 0x0 +#define MX53_PAD_DI0_PIN4__ESDHC1_WP 0x05c 0x388 0x7fc 0x3 0x0 +#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD 0x05c 0x388 0x000 0x5 0x0 +#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 0x05c 0x388 0x000 0x6 0x0 +#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT 0x05c 0x388 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x060 0x38c 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT0__GPIO4_21 0x060 0x38c 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT0__CSPI_SCLK 0x060 0x38c 0x780 0x2 0x0 +#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 0x060 0x38c 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN 0x060 0x38c 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 0x060 0x38c 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY 0x060 0x38c 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x064 0x390 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT1__GPIO4_22 0x064 0x390 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT1__CSPI_MOSI 0x064 0x390 0x788 0x2 0x0 +#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 0x064 0x390 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x064 0x390 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 0x064 0x390 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID 0x064 0x390 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x068 0x394 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT2__GPIO4_23 0x068 0x394 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT2__CSPI_MISO 0x068 0x394 0x784 0x2 0x0 +#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 0x068 0x394 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE 0x068 0x394 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 0x068 0x394 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE 0x068 0x394 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x06c 0x398 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT3__GPIO4_24 0x06c 0x398 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT3__CSPI_SS0 0x06c 0x398 0x78c 0x2 0x0 +#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 0x06c 0x398 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR 0x06c 0x398 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 0x06c 0x398 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR 0x06c 0x398 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x070 0x39c 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT4__GPIO4_25 0x070 0x39c 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT4__CSPI_SS1 0x070 0x39c 0x790 0x2 0x0 +#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 0x070 0x39c 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB 0x070 0x39c 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 0x070 0x39c 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK 0x070 0x39c 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x074 0x3a0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT5__GPIO4_26 0x074 0x3a0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT5__CSPI_SS2 0x074 0x3a0 0x794 0x2 0x0 +#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 0x074 0x3a0 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS 0x074 0x3a0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 0x074 0x3a0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 0x074 0x3a0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x078 0x3a4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT6__GPIO4_27 0x078 0x3a4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT6__CSPI_SS3 0x078 0x3a4 0x798 0x2 0x0 +#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 0x078 0x3a4 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE 0x078 0x3a4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 0x078 0x3a4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 0x078 0x3a4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x07c 0x3a8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT7__GPIO4_28 0x07c 0x3a8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT7__CSPI_RDY 0x07c 0x3a8 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 0x07c 0x3a8 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 0x07c 0x3a8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 0x07c 0x3a8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID 0x07c 0x3a8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x080 0x3ac 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT8__GPIO4_29 0x080 0x3ac 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x080 0x3ac 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B 0x080 0x3ac 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 0x080 0x3ac 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 0x080 0x3ac 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID 0x080 0x3ac 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x084 0x3b0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT9__GPIO4_30 0x084 0x3b0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT9__PWM2_PWMO 0x084 0x3b0 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B 0x084 0x3b0 0x000 0x3 0x0 +#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 0x084 0x3b0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 0x084 0x3b0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 0x084 0x3b0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x088 0x3b4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT10__GPIO4_31 0x088 0x3b4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP 0x088 0x3b4 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 0x088 0x3b4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 0x088 0x3b4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 0x088 0x3b4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x08c 0x3b8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT11__GPIO5_5 0x08c 0x3b8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT 0x08c 0x3b8 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 0x08c 0x3b8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 0x08c 0x3b8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 0x08c 0x3b8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x090 0x3bc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT12__GPIO5_6 0x090 0x3bc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK 0x090 0x3bc 0x000 0x2 0x0 +#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 0x090 0x3bc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 0x090 0x3bc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 0x090 0x3bc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x094 0x3c0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT13__GPIO5_7 0x094 0x3c0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS 0x094 0x3c0 0x754 0x3 0x0 +#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 0x094 0x3c0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 0x094 0x3c0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 0x094 0x3c0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x098 0x3c4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT14__GPIO5_8 0x098 0x3c4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC 0x098 0x3c4 0x750 0x3 0x0 +#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 0x098 0x3c4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 0x098 0x3c4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 0x098 0x3c4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x09c 0x3c8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT15__GPIO5_9 0x09c 0x3c8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 0x09c 0x3c8 0x7ac 0x2 0x1 +#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 0x09c 0x3c8 0x7c8 0x3 0x0 +#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 0x09c 0x3c8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 0x09c 0x3c8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 0x09c 0x3c8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x0a0 0x3cc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT16__GPIO5_10 0x0a0 0x3cc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0a0 0x3cc 0x7c0 0x2 0x0 +#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC 0x0a0 0x3cc 0x758 0x3 0x1 +#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 0x0a0 0x3cc 0x868 0x4 0x0 +#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 0x0a0 0x3cc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 0x0a0 0x3cc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 0x0a0 0x3cc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x0a4 0x3d0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT17__GPIO5_11 0x0a4 0x3d0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO 0x0a4 0x3d0 0x7bc 0x2 0x0 +#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD 0x0a4 0x3d0 0x74c 0x3 0x1 +#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 0x0a4 0x3d0 0x86c 0x4 0x0 +#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 0x0a4 0x3d0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 0x0a4 0x3d0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x0a8 0x3d4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT18__GPIO5_12 0x0a8 0x3d4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 0x0a8 0x3d4 0x7c4 0x2 0x0 +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS 0x0a8 0x3d4 0x75c 0x3 0x1 +#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS 0x0a8 0x3d4 0x73c 0x4 0x0 +#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 0x0a8 0x3d4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 0x0a8 0x3d4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 0x0a8 0x3d4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x0ac 0x3d8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT19__GPIO5_13 0x0ac 0x3d8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0ac 0x3d8 0x7b8 0x2 0x0 +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD 0x0ac 0x3d8 0x748 0x3 0x1 +#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC 0x0ac 0x3d8 0x738 0x4 0x0 +#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 0x0ac 0x3d8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 0x0ac 0x3d8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 0x0ac 0x3d8 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x0b0 0x3dc 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT20__GPIO5_14 0x0b0 0x3dc 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0b0 0x3dc 0x79c 0x2 0x1 +#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC 0x0b0 0x3dc 0x740 0x3 0x0 +#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 0x0b0 0x3dc 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 0x0b0 0x3dc 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI 0x0b0 0x3dc 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x0b4 0x3e0 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT21__GPIO5_15 0x0b4 0x3e0 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0b4 0x3e0 0x7a4 0x2 0x1 +#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD 0x0b4 0x3e0 0x734 0x3 0x0 +#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 0x0b4 0x3e0 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 0x0b4 0x3e0 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO 0x0b4 0x3e0 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x0b8 0x3e4 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT22__GPIO5_16 0x0b8 0x3e4 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO 0x0b8 0x3e4 0x7a0 0x2 0x1 +#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS 0x0b8 0x3e4 0x744 0x3 0x0 +#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 0x0b8 0x3e4 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 0x0b8 0x3e4 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK 0x0b8 0x3e4 0x000 0x7 0x0 +#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x0bc 0x3e8 0x000 0x0 0x0 +#define MX53_PAD_DISP0_DAT23__GPIO5_17 0x0bc 0x3e8 0x000 0x1 0x0 +#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 0x0bc 0x3e8 0x7a8 0x2 0x1 +#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD 0x0bc 0x3e8 0x730 0x3 0x0 +#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 0x0bc 0x3e8 0x000 0x5 0x0 +#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 0x0bc 0x3e8 0x000 0x6 0x0 +#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS 0x0bc 0x3e8 0x000 0x7 0x0 +#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x0c0 0x3ec 0x000 0x0 0x0 +#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x0c0 0x3ec 0x000 0x1 0x0 +#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 0x0c0 0x3ec 0x000 0x5 0x0 +#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 0x0c0 0x3ec 0x000 0x6 0x0 +#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x0c4 0x3f0 0x000 0x0 0x0 +#define MX53_PAD_CSI0_MCLK__GPIO5_19 0x0c4 0x3f0 0x000 0x1 0x0 +#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x0c4 0x3f0 0x000 0x2 0x0 +#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 0x0c4 0x3f0 0x000 0x5 0x0 +#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 0x0c4 0x3f0 0x000 0x6 0x0 +#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL 0x0c4 0x3f0 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x0c8 0x3f4 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x0c8 0x3f4 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 0x0c8 0x3f4 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 0x0c8 0x3f4 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK 0x0c8 0x3f4 0x000 0x7 0x0 +#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x0cc 0x3f8 0x000 0x0 0x0 +#define MX53_PAD_CSI0_VSYNC__GPIO5_21 0x0cc 0x3f8 0x000 0x1 0x0 +#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 0x0cc 0x3f8 0x000 0x5 0x0 +#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 0x0cc 0x3f8 0x000 0x6 0x0 +#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 0x0cc 0x3f8 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x0d0 0x3fc 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT4__GPIO5_22 0x0d0 0x3fc 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT4__KPP_COL_5 0x0d0 0x3fc 0x840 0x2 0x1 +#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK 0x0d0 0x3fc 0x79c 0x3 0x2 +#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP 0x0d0 0x3fc 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x0d0 0x3fc 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 0x0d0 0x3fc 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 0x0d0 0x3fc 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x0d4 0x400 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT5__GPIO5_23 0x0d4 0x400 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 0x0d4 0x400 0x84c 0x2 0x0 +#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI 0x0d4 0x400 0x7a4 0x3 0x2 +#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT 0x0d4 0x400 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x0d4 0x400 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 0x0d4 0x400 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 0x0d4 0x400 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x0d8 0x404 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT6__GPIO5_24 0x0d8 0x404 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT6__KPP_COL_6 0x0d8 0x404 0x844 0x2 0x0 +#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO 0x0d8 0x404 0x7a0 0x3 0x2 +#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK 0x0d8 0x404 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x0d8 0x404 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 0x0d8 0x404 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 0x0d8 0x404 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x0dc 0x408 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT7__GPIO5_25 0x0dc 0x408 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 0x0dc 0x408 0x850 0x2 0x0 +#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 0x0dc 0x408 0x7a8 0x3 0x2 +#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR 0x0dc 0x408 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x0dc 0x408 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 0x0dc 0x408 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 0x0dc 0x408 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x0e0 0x40c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT8__GPIO5_26 0x0e0 0x40c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT8__KPP_COL_7 0x0e0 0x40c 0x848 0x2 0x0 +#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK 0x0e0 0x40c 0x7b8 0x3 0x1 +#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC 0x0e0 0x40c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT8__I2C1_SDA 0x0e0 0x40c 0x818 0x5 0x0 +#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 0x0e0 0x40c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 0x0e0 0x40c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x0e4 0x410 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT9__GPIO5_27 0x0e4 0x410 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 0x0e4 0x410 0x854 0x2 0x0 +#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x0e4 0x410 0x7c0 0x3 0x1 +#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR 0x0e4 0x410 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT9__I2C1_SCL 0x0e4 0x410 0x814 0x5 0x0 +#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 0x0e4 0x410 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 0x0e4 0x410 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x0e8 0x414 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT10__GPIO5_28 0x0e8 0x414 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x0e8 0x414 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x0e8 0x414 0x7bc 0x3 0x1 +#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC 0x0e8 0x414 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 0x0e8 0x414 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 0x0e8 0x414 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 0x0e8 0x414 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x0ec 0x418 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT11__GPIO5_29 0x0ec 0x418 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x0ec 0x418 0x878 0x2 0x1 +#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 0x0ec 0x418 0x7c4 0x3 0x1 +#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS 0x0ec 0x418 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 0x0ec 0x418 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 0x0ec 0x418 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 0x0ec 0x418 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x0f0 0x41c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT12__GPIO5_30 0x0f0 0x41c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x0f0 0x41c 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 0x0f0 0x41c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 0x0f0 0x41c 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 0x0f0 0x41c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 0x0f0 0x41c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x0f4 0x420 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT13__GPIO5_31 0x0f4 0x420 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x0f4 0x420 0x890 0x2 0x3 +#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 0x0f4 0x420 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 0x0f4 0x420 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 0x0f4 0x420 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 0x0f4 0x420 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x0f8 0x424 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT14__GPIO6_0 0x0f8 0x424 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX 0x0f8 0x424 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 0x0f8 0x424 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 0x0f8 0x424 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 0x0f8 0x424 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 0x0f8 0x424 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x0fc 0x428 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT15__GPIO6_1 0x0fc 0x428 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX 0x0fc 0x428 0x898 0x2 0x3 +#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 0x0fc 0x428 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 0x0fc 0x428 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 0x0fc 0x428 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 0x0fc 0x428 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x100 0x42c 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT16__GPIO6_2 0x100 0x42c 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT16__UART4_RTS 0x100 0x42c 0x88c 0x2 0x0 +#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 0x100 0x42c 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 0x100 0x42c 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 0x100 0x42c 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 0x100 0x42c 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x104 0x430 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT17__GPIO6_3 0x104 0x430 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT17__UART4_CTS 0x104 0x430 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 0x104 0x430 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 0x104 0x430 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 0x104 0x430 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 0x104 0x430 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x108 0x434 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT18__GPIO6_4 0x108 0x434 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT18__UART5_RTS 0x108 0x434 0x894 0x2 0x2 +#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 0x108 0x434 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 0x108 0x434 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 0x108 0x434 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 0x108 0x434 0x000 0x7 0x0 +#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x10c 0x438 0x000 0x0 0x0 +#define MX53_PAD_CSI0_DAT19__GPIO6_5 0x10c 0x438 0x000 0x1 0x0 +#define MX53_PAD_CSI0_DAT19__UART5_CTS 0x10c 0x438 0x000 0x2 0x0 +#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 0x10c 0x438 0x000 0x4 0x0 +#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 0x10c 0x438 0x000 0x5 0x0 +#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 0x10c 0x438 0x000 0x6 0x0 +#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK 0x10c 0x438 0x000 0x7 0x0 +#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 0x110 0x458 0x000 0x0 0x0 +#define MX53_PAD_EIM_A25__GPIO5_2 0x110 0x458 0x000 0x1 0x0 +#define MX53_PAD_EIM_A25__ECSPI2_RDY 0x110 0x458 0x000 0x2 0x0 +#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x110 0x458 0x000 0x3 0x0 +#define MX53_PAD_EIM_A25__CSPI_SS1 0x110 0x458 0x790 0x4 0x1 +#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS 0x110 0x458 0x000 0x6 0x0 +#define MX53_PAD_EIM_A25__USBPHY1_BISTOK 0x110 0x458 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 0x114 0x45c 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB2__GPIO2_30 0x114 0x45c 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK 0x114 0x45c 0x76c 0x2 0x0 +#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS 0x114 0x45c 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB2__ECSPI1_SS0 0x114 0x45c 0x7a8 0x4 0x3 +#define MX53_PAD_EIM_EB2__I2C2_SCL 0x114 0x45c 0x81c 0x5 0x1 +#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x118 0x460 0x000 0x0 0x0 +#define MX53_PAD_EIM_D16__GPIO3_16 0x118 0x460 0x000 0x1 0x0 +#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 0x118 0x460 0x000 0x2 0x0 +#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK 0x118 0x460 0x000 0x3 0x0 +#define MX53_PAD_EIM_D16__ECSPI1_SCLK 0x118 0x460 0x79c 0x4 0x3 +#define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1 +#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x11c 0x464 0x000 0x0 0x0 +#define MX53_PAD_EIM_D17__GPIO3_17 0x11c 0x464 0x000 0x1 0x0 +#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 0x11c 0x464 0x000 0x2 0x0 +#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN 0x11c 0x464 0x830 0x3 0x0 +#define MX53_PAD_EIM_D17__ECSPI1_MISO 0x11c 0x464 0x7a0 0x4 0x3 +#define MX53_PAD_EIM_D17__I2C3_SCL 0x11c 0x464 0x824 0x5 0x0 +#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x120 0x468 0x000 0x0 0x0 +#define MX53_PAD_EIM_D18__GPIO3_18 0x120 0x468 0x000 0x1 0x0 +#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 0x120 0x468 0x000 0x2 0x0 +#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO 0x120 0x468 0x830 0x3 0x1 +#define MX53_PAD_EIM_D18__ECSPI1_MOSI 0x120 0x468 0x7a4 0x4 0x3 +#define MX53_PAD_EIM_D18__I2C3_SDA 0x120 0x468 0x828 0x5 0x0 +#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS 0x120 0x468 0x000 0x6 0x0 +#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x124 0x46c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D19__GPIO3_19 0x124 0x46c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 0x124 0x46c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS 0x124 0x46c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D19__ECSPI1_SS1 0x124 0x46c 0x7ac 0x4 0x2 +#define MX53_PAD_EIM_D19__EPIT1_EPITO 0x124 0x46c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D19__UART1_CTS 0x124 0x46c 0x000 0x6 0x0 +#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC 0x124 0x46c 0x8a4 0x7 0x0 +#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x128 0x470 0x000 0x0 0x0 +#define MX53_PAD_EIM_D20__GPIO3_20 0x128 0x470 0x000 0x1 0x0 +#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 0x128 0x470 0x000 0x2 0x0 +#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS 0x128 0x470 0x000 0x3 0x0 +#define MX53_PAD_EIM_D20__CSPI_SS0 0x128 0x470 0x78c 0x4 0x1 +#define MX53_PAD_EIM_D20__EPIT2_EPITO 0x128 0x470 0x000 0x5 0x0 +#define MX53_PAD_EIM_D20__UART1_RTS 0x128 0x470 0x874 0x6 0x1 +#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR 0x128 0x470 0x000 0x7 0x0 +#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x12c 0x474 0x000 0x0 0x0 +#define MX53_PAD_EIM_D21__GPIO3_21 0x12c 0x474 0x000 0x1 0x0 +#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 0x12c 0x474 0x000 0x2 0x0 +#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK 0x12c 0x474 0x000 0x3 0x0 +#define MX53_PAD_EIM_D21__CSPI_SCLK 0x12c 0x474 0x780 0x4 0x1 +#define MX53_PAD_EIM_D21__I2C1_SCL 0x12c 0x474 0x814 0x5 0x1 +#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC 0x12c 0x474 0x89c 0x6 0x1 +#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x130 0x478 0x000 0x0 0x0 +#define MX53_PAD_EIM_D22__GPIO3_22 0x130 0x478 0x000 0x1 0x0 +#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 0x130 0x478 0x000 0x2 0x0 +#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN 0x130 0x478 0x82c 0x3 0x0 +#define MX53_PAD_EIM_D22__CSPI_MISO 0x130 0x478 0x784 0x4 0x1 +#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR 0x130 0x478 0x000 0x6 0x0 +#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x134 0x47c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D23__GPIO3_23 0x134 0x47c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D23__UART3_CTS 0x134 0x47c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D23__UART1_DCD 0x134 0x47c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS 0x134 0x47c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x134 0x47c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN 0x134 0x47c 0x834 0x6 0x0 +#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 0x134 0x47c 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 0x138 0x480 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB3__GPIO2_31 0x138 0x480 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB3__UART3_RTS 0x138 0x480 0x884 0x2 0x1 +#define MX53_PAD_EIM_EB3__UART1_RI 0x138 0x480 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x138 0x480 0x000 0x5 0x0 +#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC 0x138 0x480 0x838 0x6 0x0 +#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 0x138 0x480 0x000 0x7 0x0 +#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x13c 0x484 0x000 0x0 0x0 +#define MX53_PAD_EIM_D24__GPIO3_24 0x13c 0x484 0x000 0x1 0x0 +#define MX53_PAD_EIM_D24__UART3_TXD_MUX 0x13c 0x484 0x000 0x2 0x0 +#define MX53_PAD_EIM_D24__ECSPI1_SS2 0x13c 0x484 0x7b0 0x3 0x1 +#define MX53_PAD_EIM_D24__CSPI_SS2 0x13c 0x484 0x794 0x4 0x1 +#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS 0x13c 0x484 0x754 0x5 0x1 +#define MX53_PAD_EIM_D24__ECSPI2_SS2 0x13c 0x484 0x000 0x6 0x0 +#define MX53_PAD_EIM_D24__UART1_DTR 0x13c 0x484 0x000 0x7 0x0 +#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x140 0x488 0x000 0x0 0x0 +#define MX53_PAD_EIM_D25__GPIO3_25 0x140 0x488 0x000 0x1 0x0 +#define MX53_PAD_EIM_D25__UART3_RXD_MUX 0x140 0x488 0x888 0x2 0x1 +#define MX53_PAD_EIM_D25__ECSPI1_SS3 0x140 0x488 0x7b4 0x3 0x1 +#define MX53_PAD_EIM_D25__CSPI_SS3 0x140 0x488 0x798 0x4 0x1 +#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC 0x140 0x488 0x750 0x5 0x1 +#define MX53_PAD_EIM_D25__ECSPI2_SS3 0x140 0x488 0x000 0x6 0x0 +#define MX53_PAD_EIM_D25__UART1_DSR 0x140 0x488 0x000 0x7 0x0 +#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x144 0x48c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D26__GPIO3_26 0x144 0x48c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D26__UART2_TXD_MUX 0x144 0x48c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D26__FIRI_RXD 0x144 0x48c 0x80c 0x3 0x0 +#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 0x144 0x48c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 0x144 0x48c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D26__IPU_SISG_2 0x144 0x48c 0x000 0x6 0x0 +#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x144 0x48c 0x000 0x7 0x0 +#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x148 0x490 0x000 0x0 0x0 +#define MX53_PAD_EIM_D27__GPIO3_27 0x148 0x490 0x000 0x1 0x0 +#define MX53_PAD_EIM_D27__UART2_RXD_MUX 0x148 0x490 0x880 0x2 0x1 +#define MX53_PAD_EIM_D27__FIRI_TXD 0x148 0x490 0x000 0x3 0x0 +#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 0x148 0x490 0x000 0x4 0x0 +#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 0x148 0x490 0x000 0x5 0x0 +#define MX53_PAD_EIM_D27__IPU_SISG_3 0x148 0x490 0x000 0x6 0x0 +#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x148 0x490 0x000 0x7 0x0 +#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x14c 0x494 0x000 0x0 0x0 +#define MX53_PAD_EIM_D28__GPIO3_28 0x14c 0x494 0x000 0x1 0x0 +#define MX53_PAD_EIM_D28__UART2_CTS 0x14c 0x494 0x000 0x2 0x0 +#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO 0x14c 0x494 0x82c 0x3 0x1 +#define MX53_PAD_EIM_D28__CSPI_MOSI 0x14c 0x494 0x788 0x4 0x1 +#define MX53_PAD_EIM_D28__I2C1_SDA 0x14c 0x494 0x818 0x5 0x1 +#define MX53_PAD_EIM_D28__IPU_EXT_TRIG 0x14c 0x494 0x000 0x6 0x0 +#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 0x14c 0x494 0x000 0x7 0x0 +#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x150 0x498 0x000 0x0 0x0 +#define MX53_PAD_EIM_D29__GPIO3_29 0x150 0x498 0x000 0x1 0x0 +#define MX53_PAD_EIM_D29__UART2_RTS 0x150 0x498 0x87c 0x2 0x1 +#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS 0x150 0x498 0x000 0x3 0x0 +#define MX53_PAD_EIM_D29__CSPI_SS0 0x150 0x498 0x78c 0x4 0x2 +#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 0x150 0x498 0x000 0x5 0x0 +#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC 0x150 0x498 0x83c 0x6 0x0 +#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 0x150 0x498 0x000 0x7 0x0 +#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x154 0x49c 0x000 0x0 0x0 +#define MX53_PAD_EIM_D30__GPIO3_30 0x154 0x49c 0x000 0x1 0x0 +#define MX53_PAD_EIM_D30__UART3_CTS 0x154 0x49c 0x000 0x2 0x0 +#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 0x154 0x49c 0x000 0x3 0x0 +#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 0x154 0x49c 0x000 0x4 0x0 +#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x154 0x49c 0x000 0x5 0x0 +#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC 0x154 0x49c 0x8a0 0x6 0x0 +#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC 0x154 0x49c 0x8a4 0x7 0x1 +#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x158 0x4a0 0x000 0x0 0x0 +#define MX53_PAD_EIM_D31__GPIO3_31 0x158 0x4a0 0x000 0x1 0x0 +#define MX53_PAD_EIM_D31__UART3_RTS 0x158 0x4a0 0x884 0x2 0x3 +#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 0x158 0x4a0 0x000 0x3 0x0 +#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 0x158 0x4a0 0x000 0x4 0x0 +#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x158 0x4a0 0x000 0x5 0x0 +#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR 0x158 0x4a0 0x000 0x6 0x0 +#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR 0x158 0x4a0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 0x15c 0x4a8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A24__GPIO5_4 0x15c 0x4a8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x15c 0x4a8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 0x15c 0x4a8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A24__IPU_SISG_2 0x15c 0x4a8 0x000 0x6 0x0 +#define MX53_PAD_EIM_A24__USBPHY2_BVALID 0x15c 0x4a8 0x000 0x7 0x0 +#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 0x160 0x4ac 0x000 0x0 0x0 +#define MX53_PAD_EIM_A23__GPIO6_6 0x160 0x4ac 0x000 0x1 0x0 +#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x160 0x4ac 0x000 0x2 0x0 +#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 0x160 0x4ac 0x000 0x3 0x0 +#define MX53_PAD_EIM_A23__IPU_SISG_3 0x160 0x4ac 0x000 0x6 0x0 +#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION 0x160 0x4ac 0x000 0x7 0x0 +#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 0x164 0x4b0 0x000 0x0 0x0 +#define MX53_PAD_EIM_A22__GPIO2_16 0x164 0x4b0 0x000 0x1 0x0 +#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x164 0x4b0 0x000 0x2 0x0 +#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 0x164 0x4b0 0x000 0x3 0x0 +#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 0x164 0x4b0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 0x168 0x4b4 0x000 0x0 0x0 +#define MX53_PAD_EIM_A21__GPIO2_17 0x168 0x4b4 0x000 0x1 0x0 +#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x168 0x4b4 0x000 0x2 0x0 +#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 0x168 0x4b4 0x000 0x3 0x0 +#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 0x168 0x4b4 0x000 0x7 0x0 +#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 0x16c 0x4b8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A20__GPIO2_18 0x16c 0x4b8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x16c 0x4b8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 0x16c 0x4b8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 0x16c 0x4b8 0x000 0x7 0x0 +#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 0x170 0x4bc 0x000 0x0 0x0 +#define MX53_PAD_EIM_A19__GPIO2_19 0x170 0x4bc 0x000 0x1 0x0 +#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x170 0x4bc 0x000 0x2 0x0 +#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 0x170 0x4bc 0x000 0x3 0x0 +#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 0x170 0x4bc 0x000 0x7 0x0 +#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 0x174 0x4c0 0x000 0x0 0x0 +#define MX53_PAD_EIM_A18__GPIO2_20 0x174 0x4c0 0x000 0x1 0x0 +#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x174 0x4c0 0x000 0x2 0x0 +#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 0x174 0x4c0 0x000 0x3 0x0 +#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 0x174 0x4c0 0x000 0x7 0x0 +#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 0x178 0x4c4 0x000 0x0 0x0 +#define MX53_PAD_EIM_A17__GPIO2_21 0x178 0x4c4 0x000 0x1 0x0 +#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x178 0x4c4 0x000 0x2 0x0 +#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 0x178 0x4c4 0x000 0x3 0x0 +#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 0x178 0x4c4 0x000 0x7 0x0 +#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 0x17c 0x4c8 0x000 0x0 0x0 +#define MX53_PAD_EIM_A16__GPIO2_22 0x17c 0x4c8 0x000 0x1 0x0 +#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x17c 0x4c8 0x000 0x2 0x0 +#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK 0x17c 0x4c8 0x000 0x3 0x0 +#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 0x17c 0x4c8 0x000 0x7 0x0 +#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 0x180 0x4cc 0x000 0x0 0x0 +#define MX53_PAD_EIM_CS0__GPIO2_23 0x180 0x4cc 0x000 0x1 0x0 +#define MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x180 0x4cc 0x7b8 0x2 0x2 +#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 0x180 0x4cc 0x000 0x3 0x0 +#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x184 0x4d0 0x000 0x0 0x0 +#define MX53_PAD_EIM_CS1__GPIO2_24 0x184 0x4d0 0x000 0x1 0x0 +#define MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x184 0x4d0 0x7c0 0x2 0x2 +#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x184 0x4d0 0x000 0x3 0x0 +#define MX53_PAD_EIM_OE__EMI_WEIM_OE 0x188 0x4d4 0x000 0x0 0x0 +#define MX53_PAD_EIM_OE__GPIO2_25 0x188 0x4d4 0x000 0x1 0x0 +#define MX53_PAD_EIM_OE__ECSPI2_MISO 0x188 0x4d4 0x7bc 0x2 0x2 +#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 0x188 0x4d4 0x000 0x3 0x0 +#define MX53_PAD_EIM_OE__USBPHY2_IDDIG 0x188 0x4d4 0x000 0x7 0x0 +#define MX53_PAD_EIM_RW__EMI_WEIM_RW 0x18c 0x4d8 0x000 0x0 0x0 +#define MX53_PAD_EIM_RW__GPIO2_26 0x18c 0x4d8 0x000 0x1 0x0 +#define MX53_PAD_EIM_RW__ECSPI2_SS0 0x18c 0x4d8 0x7c4 0x2 0x2 +#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 0x18c 0x4d8 0x000 0x3 0x0 +#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT 0x18c 0x4d8 0x000 0x7 0x0 +#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA 0x190 0x4dc 0x000 0x0 0x0 +#define MX53_PAD_EIM_LBA__GPIO2_27 0x190 0x4dc 0x000 0x1 0x0 +#define MX53_PAD_EIM_LBA__ECSPI2_SS1 0x190 0x4dc 0x7c8 0x2 0x1 +#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 0x190 0x4dc 0x000 0x3 0x0 +#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 0x190 0x4dc 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 0x194 0x4e4 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB0__GPIO2_28 0x194 0x4e4 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x194 0x4e4 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 0x194 0x4e4 0x000 0x4 0x0 +#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY 0x194 0x4e4 0x810 0x5 0x0 +#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 0x194 0x4e4 0x000 0x7 0x0 +#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 0x198 0x4e8 0x000 0x0 0x0 +#define MX53_PAD_EIM_EB1__GPIO2_29 0x198 0x4e8 0x000 0x1 0x0 +#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x198 0x4e8 0x000 0x3 0x0 +#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 0x198 0x4e8 0x000 0x4 0x0 +#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 0x198 0x4e8 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x19c 0x4ec 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA0__GPIO3_0 0x19c 0x4ec 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x19c 0x4ec 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 0x19c 0x4ec 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 0x19c 0x4ec 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x1a0 0x4f0 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA1__GPIO3_1 0x1a0 0x4f0 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x1a0 0x4f0 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 0x1a0 0x4f0 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 0x1a0 0x4f0 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x1a4 0x4f4 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA2__GPIO3_2 0x1a4 0x4f4 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x1a4 0x4f4 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 0x1a4 0x4f4 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 0x1a4 0x4f4 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x1a8 0x4f8 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA3__GPIO3_3 0x1a8 0x4f8 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x1a8 0x4f8 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 0x1a8 0x4f8 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 0x1a8 0x4f8 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x1ac 0x4fc 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA4__GPIO3_4 0x1ac 0x4fc 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x1ac 0x4fc 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 0x1ac 0x4fc 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 0x1ac 0x4fc 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x1b0 0x500 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA5__GPIO3_5 0x1b0 0x500 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x1b0 0x500 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 0x1b0 0x500 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 0x1b0 0x500 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x1b4 0x504 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA6__GPIO3_6 0x1b4 0x504 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x1b4 0x504 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 0x1b4 0x504 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 0x1b4 0x504 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0x1b8 0x508 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA7__GPIO3_7 0x1b8 0x508 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x1b8 0x508 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 0x1b8 0x508 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 0x1b8 0x508 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 0x1bc 0x50c 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA8__GPIO3_8 0x1bc 0x50c 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x1bc 0x50c 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 0x1bc 0x50c 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 0x1bc 0x50c 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 0x1c0 0x510 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA9__GPIO3_9 0x1c0 0x510 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x1c0 0x510 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 0x1c0 0x510 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 0x1c0 0x510 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 0x1c4 0x514 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA10__GPIO3_10 0x1c4 0x514 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x1c4 0x514 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN 0x1c4 0x514 0x834 0x4 0x1 +#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 0x1c4 0x514 0x000 0x7 0x0 +#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 0x1c8 0x518 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA11__GPIO3_11 0x1c8 0x518 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x1c8 0x518 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC 0x1c8 0x518 0x838 0x4 0x1 +#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 0x1cc 0x51c 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA12__GPIO3_12 0x1cc 0x51c 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x1cc 0x51c 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC 0x1cc 0x51c 0x83c 0x4 0x1 +#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 0x1d0 0x520 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA13__GPIO3_13 0x1d0 0x520 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x1d0 0x520 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK 0x1d0 0x520 0x76c 0x4 0x1 +#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 0x1d4 0x524 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA14__GPIO3_14 0x1d4 0x524 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x1d4 0x524 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK 0x1d4 0x524 0x000 0x4 0x0 +#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 0x1d8 0x528 0x000 0x0 0x0 +#define MX53_PAD_EIM_DA15__GPIO3_15 0x1d8 0x528 0x000 0x1 0x0 +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x1d8 0x528 0x000 0x3 0x0 +#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x1d8 0x528 0x000 0x4 0x0 +#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x1dc 0x52c 0x000 0x0 0x0 +#define MX53_PAD_NANDF_WE_B__GPIO6_12 0x1dc 0x52c 0x000 0x1 0x0 +#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x1e0 0x530 0x000 0x0 0x0 +#define MX53_PAD_NANDF_RE_B__GPIO6_13 0x1e0 0x530 0x000 0x1 0x0 +#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT 0x1e4 0x534 0x000 0x0 0x0 +#define MX53_PAD_EIM_WAIT__GPIO5_0 0x1e4 0x534 0x000 0x1 0x0 +#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B 0x1e4 0x534 0x000 0x2 0x0 +#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 0x1ec 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x1ec 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 0x1f0 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x1f0 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 0x1f4 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x1f4 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 0x1f8 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x1f8 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 0x1fc 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x1fc 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 0x200 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x200 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 0x204 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x204 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 0x208 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x208 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 0x20c 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x20c 0x000 0x000 0x1 0x0 +#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 0x210 0x000 0x000 0x0 0x0 +#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x210 0x000 0x000 0x1 0x0 +#define MX53_PAD_GPIO_10__GPIO4_0 0x214 0x540 0x000 0x0 0x0 +#define MX53_PAD_GPIO_10__OSC32k_32K_OUT 0x214 0x540 0x000 0x1 0x0 +#define MX53_PAD_GPIO_11__GPIO4_1 0x218 0x544 0x000 0x0 0x0 +#define MX53_PAD_GPIO_12__GPIO4_2 0x21c 0x548 0x000 0x0 0x0 +#define MX53_PAD_GPIO_13__GPIO4_3 0x220 0x54c 0x000 0x0 0x0 +#define MX53_PAD_GPIO_14__GPIO4_4 0x224 0x550 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x228 0x5a0 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CLE__GPIO6_7 0x228 0x5a0 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 0x228 0x5a0 0x000 0x7 0x0 +#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x22c 0x5a4 0x000 0x0 0x0 +#define MX53_PAD_NANDF_ALE__GPIO6_8 0x22c 0x5a4 0x000 0x1 0x0 +#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 0x22c 0x5a4 0x000 0x7 0x0 +#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0x230 0x5a8 0x000 0x0 0x0 +#define MX53_PAD_NANDF_WP_B__GPIO6_9 0x230 0x5a8 0x000 0x1 0x0 +#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 0x230 0x5a8 0x000 0x7 0x0 +#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0x234 0x5ac 0x000 0x0 0x0 +#define MX53_PAD_NANDF_RB0__GPIO6_10 0x234 0x5ac 0x000 0x1 0x0 +#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 0x234 0x5ac 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x238 0x5b0 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS0__GPIO6_11 0x238 0x5b0 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 0x238 0x5b0 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x23c 0x5b4 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS1__GPIO6_14 0x23c 0x5b4 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS1__MLB_MLBCLK 0x23c 0x5b4 0x858 0x6 0x0 +#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 0x23c 0x5b4 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x240 0x5b8 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS2__GPIO6_15 0x240 0x5b8 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS2__IPU_SISG_0 0x240 0x5b8 0x000 0x2 0x0 +#define MX53_PAD_NANDF_CS2__ESAI1_TX0 0x240 0x5b8 0x7e4 0x3 0x0 +#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE 0x240 0x5b8 0x000 0x4 0x0 +#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK 0x240 0x5b8 0x000 0x5 0x0 +#define MX53_PAD_NANDF_CS2__MLB_MLBSIG 0x240 0x5b8 0x860 0x6 0x0 +#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 0x240 0x5b8 0x000 0x7 0x0 +#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x244 0x5bc 0x000 0x0 0x0 +#define MX53_PAD_NANDF_CS3__GPIO6_16 0x244 0x5bc 0x000 0x1 0x0 +#define MX53_PAD_NANDF_CS3__IPU_SISG_1 0x244 0x5bc 0x000 0x2 0x0 +#define MX53_PAD_NANDF_CS3__ESAI1_TX1 0x244 0x5bc 0x7e8 0x3 0x0 +#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 0x244 0x5bc 0x000 0x4 0x0 +#define MX53_PAD_NANDF_CS3__MLB_MLBDAT 0x244 0x5bc 0x85c 0x6 0x0 +#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 0x244 0x5bc 0x000 0x7 0x0 +#define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1 +#define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0 +#define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0 +#define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1 +#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0 +#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0 +#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0 +#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x24c 0x5c8 0x000 0x0 0x0 +#define MX53_PAD_FEC_REF_CLK__GPIO1_23 0x24c 0x5c8 0x000 0x1 0x0 +#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR 0x24c 0x5c8 0x7cc 0x2 0x0 +#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 0x24c 0x5c8 0x000 0x5 0x0 +#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 0x24c 0x5c8 0x000 0x6 0x0 +#define MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x250 0x5cc 0x000 0x0 0x0 +#define MX53_PAD_FEC_RX_ER__GPIO1_24 0x250 0x5cc 0x000 0x1 0x0 +#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR 0x250 0x5cc 0x7d4 0x2 0x0 +#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK 0x250 0x5cc 0x808 0x3 0x1 +#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 0x250 0x5cc 0x000 0x4 0x0 +#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x254 0x5d0 0x000 0x0 0x0 +#define MX53_PAD_FEC_CRS_DV__GPIO1_25 0x254 0x5d0 0x000 0x1 0x0 +#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT 0x254 0x5d0 0x7e0 0x2 0x0 +#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x258 0x5d4 0x000 0x0 0x0 +#define MX53_PAD_FEC_RXD1__GPIO1_26 0x258 0x5d4 0x000 0x1 0x0 +#define MX53_PAD_FEC_RXD1__ESAI1_FST 0x258 0x5d4 0x7d0 0x2 0x0 +#define MX53_PAD_FEC_RXD1__MLB_MLBSIG 0x258 0x5d4 0x860 0x3 0x1 +#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 0x258 0x5d4 0x000 0x4 0x0 +#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x25c 0x5d8 0x000 0x0 0x0 +#define MX53_PAD_FEC_RXD0__GPIO1_27 0x25c 0x5d8 0x000 0x1 0x0 +#define MX53_PAD_FEC_RXD0__ESAI1_HCKT 0x25c 0x5d8 0x7d8 0x2 0x0 +#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT 0x25c 0x5d8 0x000 0x3 0x0 +#define MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x260 0x5dc 0x000 0x0 0x0 +#define MX53_PAD_FEC_TX_EN__GPIO1_28 0x260 0x5dc 0x000 0x1 0x0 +#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 0x260 0x5dc 0x7f0 0x2 0x0 +#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x264 0x5e0 0x000 0x0 0x0 +#define MX53_PAD_FEC_TXD1__GPIO1_29 0x264 0x5e0 0x000 0x1 0x0 +#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 0x264 0x5e0 0x7ec 0x2 0x0 +#define MX53_PAD_FEC_TXD1__MLB_MLBCLK 0x264 0x5e0 0x858 0x3 0x1 +#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK 0x264 0x5e0 0x000 0x4 0x0 +#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x268 0x5e4 0x000 0x0 0x0 +#define MX53_PAD_FEC_TXD0__GPIO1_30 0x268 0x5e4 0x000 0x1 0x0 +#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 0x268 0x5e4 0x7f4 0x2 0x0 +#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 0x268 0x5e4 0x000 0x7 0x0 +#define MX53_PAD_FEC_MDC__FEC_MDC 0x26c 0x5e8 0x000 0x0 0x0 +#define MX53_PAD_FEC_MDC__GPIO1_31 0x26c 0x5e8 0x000 0x1 0x0 +#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 0x26c 0x5e8 0x7f8 0x2 0x0 +#define MX53_PAD_FEC_MDC__MLB_MLBDAT 0x26c 0x5e8 0x85c 0x3 0x1 +#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG 0x26c 0x5e8 0x000 0x4 0x0 +#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 0x26c 0x5e8 0x000 0x7 0x0 +#define MX53_PAD_PATA_DIOW__PATA_DIOW 0x270 0x5f0 0x000 0x0 0x0 +#define MX53_PAD_PATA_DIOW__GPIO6_17 0x270 0x5f0 0x000 0x1 0x0 +#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x270 0x5f0 0x000 0x3 0x0 +#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 0x270 0x5f0 0x000 0x7 0x0 +#define MX53_PAD_PATA_DMACK__PATA_DMACK 0x274 0x5f4 0x000 0x0 0x0 +#define MX53_PAD_PATA_DMACK__GPIO6_18 0x274 0x5f4 0x000 0x1 0x0 +#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x274 0x5f4 0x878 0x3 0x3 +#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 0x274 0x5f4 0x000 0x7 0x0 +#define MX53_PAD_PATA_DMARQ__PATA_DMARQ 0x278 0x5f8 0x000 0x0 0x0 +#define MX53_PAD_PATA_DMARQ__GPIO7_0 0x278 0x5f8 0x000 0x1 0x0 +#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x278 0x5f8 0x000 0x3 0x0 +#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 0x278 0x5f8 0x000 0x5 0x0 +#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 0x278 0x5f8 0x000 0x7 0x0 +#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN 0x27c 0x5fc 0x000 0x0 0x0 +#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 0x27c 0x5fc 0x000 0x1 0x0 +#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x27c 0x5fc 0x880 0x3 0x3 +#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 0x27c 0x5fc 0x000 0x5 0x0 +#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 0x27c 0x5fc 0x000 0x7 0x0 +#define MX53_PAD_PATA_INTRQ__PATA_INTRQ 0x280 0x600 0x000 0x0 0x0 +#define MX53_PAD_PATA_INTRQ__GPIO7_2 0x280 0x600 0x000 0x1 0x0 +#define MX53_PAD_PATA_INTRQ__UART2_CTS 0x280 0x600 0x000 0x3 0x0 +#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x280 0x600 0x000 0x4 0x0 +#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 0x280 0x600 0x000 0x5 0x0 +#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 0x280 0x600 0x000 0x7 0x0 +#define MX53_PAD_PATA_DIOR__PATA_DIOR 0x284 0x604 0x000 0x0 0x0 +#define MX53_PAD_PATA_DIOR__GPIO7_3 0x284 0x604 0x000 0x1 0x0 +#define MX53_PAD_PATA_DIOR__UART2_RTS 0x284 0x604 0x87c 0x3 0x3 +#define MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x284 0x604 0x760 0x4 0x1 +#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 0x284 0x604 0x000 0x7 0x0 +#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B 0x288 0x608 0x000 0x0 0x0 +#define MX53_PAD_PATA_RESET_B__GPIO7_4 0x288 0x608 0x000 0x1 0x0 +#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x288 0x608 0x000 0x2 0x0 +#define MX53_PAD_PATA_RESET_B__UART1_CTS 0x288 0x608 0x000 0x3 0x0 +#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN 0x288 0x608 0x000 0x4 0x0 +#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 0x288 0x608 0x000 0x7 0x0 +#define MX53_PAD_PATA_IORDY__PATA_IORDY 0x28c 0x60c 0x000 0x0 0x0 +#define MX53_PAD_PATA_IORDY__GPIO7_5 0x28c 0x60c 0x000 0x1 0x0 +#define MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x28c 0x60c 0x000 0x2 0x0 +#define MX53_PAD_PATA_IORDY__UART1_RTS 0x28c 0x60c 0x874 0x3 0x3 +#define MX53_PAD_PATA_IORDY__CAN2_RXCAN 0x28c 0x60c 0x764 0x4 0x1 +#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 0x28c 0x60c 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_0__PATA_DA_0 0x290 0x610 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_0__GPIO7_6 0x290 0x610 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_0__ESDHC3_RST 0x290 0x610 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_0__OWIRE_LINE 0x290 0x610 0x864 0x4 0x0 +#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 0x290 0x610 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_1__PATA_DA_1 0x294 0x614 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_1__GPIO7_7 0x294 0x614 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_1__ESDHC4_CMD 0x294 0x614 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_1__UART3_CTS 0x294 0x614 0x000 0x4 0x0 +#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 0x294 0x614 0x000 0x7 0x0 +#define MX53_PAD_PATA_DA_2__PATA_DA_2 0x298 0x618 0x000 0x0 0x0 +#define MX53_PAD_PATA_DA_2__GPIO7_8 0x298 0x618 0x000 0x1 0x0 +#define MX53_PAD_PATA_DA_2__ESDHC4_CLK 0x298 0x618 0x000 0x2 0x0 +#define MX53_PAD_PATA_DA_2__UART3_RTS 0x298 0x618 0x884 0x4 0x5 +#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 0x298 0x618 0x000 0x7 0x0 +#define MX53_PAD_PATA_CS_0__PATA_CS_0 0x29c 0x61c 0x000 0x0 0x0 +#define MX53_PAD_PATA_CS_0__GPIO7_9 0x29c 0x61c 0x000 0x1 0x0 +#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x29c 0x61c 0x000 0x4 0x0 +#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 0x29c 0x61c 0x000 0x7 0x0 +#define MX53_PAD_PATA_CS_1__PATA_CS_1 0x2a0 0x620 0x000 0x0 0x0 +#define MX53_PAD_PATA_CS_1__GPIO7_10 0x2a0 0x620 0x000 0x1 0x0 +#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x2a0 0x620 0x888 0x4 0x3 +#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 0x2a0 0x620 0x000 0x7 0x0 +#define MX53_PAD_PATA_DATA0__PATA_DATA_0 0x2a4 0x628 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA0__GPIO2_0 0x2a4 0x628 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0x2a4 0x628 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x2a4 0x628 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 0x2a4 0x628 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 0x2a4 0x628 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 0x2a4 0x628 0x000 0x7 0x0 +#define MX53_PAD_PATA_DATA1__PATA_DATA_1 0x2a8 0x62c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA1__GPIO2_1 0x2a8 0x62c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0x2a8 0x62c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x2a8 0x62c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 0x2a8 0x62c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 0x2a8 0x62c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA2__PATA_DATA_2 0x2ac 0x630 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA2__GPIO2_2 0x2ac 0x630 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0x2ac 0x630 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x2ac 0x630 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 0x2ac 0x630 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 0x2ac 0x630 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA3__PATA_DATA_3 0x2b0 0x634 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA3__GPIO2_3 0x2b0 0x634 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0x2b0 0x634 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x2b0 0x634 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 0x2b0 0x634 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 0x2b0 0x634 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA4__PATA_DATA_4 0x2b4 0x638 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA4__GPIO2_4 0x2b4 0x638 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0x2b4 0x638 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 0x2b4 0x638 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 0x2b4 0x638 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 0x2b4 0x638 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA5__PATA_DATA_5 0x2b8 0x63c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA5__GPIO2_5 0x2b8 0x63c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0x2b8 0x63c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 0x2b8 0x63c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 0x2b8 0x63c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 0x2b8 0x63c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA6__PATA_DATA_6 0x2bc 0x640 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA6__GPIO2_6 0x2bc 0x640 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0x2bc 0x640 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 0x2bc 0x640 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 0x2bc 0x640 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 0x2bc 0x640 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA7__PATA_DATA_7 0x2c0 0x644 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA7__GPIO2_7 0x2c0 0x644 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0x2c0 0x644 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 0x2c0 0x644 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 0x2c0 0x644 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 0x2c0 0x644 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA8__PATA_DATA_8 0x2c4 0x648 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA8__GPIO2_8 0x2c4 0x648 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x2c4 0x648 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 0x2c4 0x648 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x2c4 0x648 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 0x2c4 0x648 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 0x2c4 0x648 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA9__PATA_DATA_9 0x2c8 0x64c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA9__GPIO2_9 0x2c8 0x64c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x2c8 0x64c 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 0x2c8 0x64c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x2c8 0x64c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 0x2c8 0x64c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 0x2c8 0x64c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA10__PATA_DATA_10 0x2cc 0x650 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA10__GPIO2_10 0x2cc 0x650 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x2cc 0x650 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 0x2cc 0x650 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x2cc 0x650 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 0x2cc 0x650 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 0x2cc 0x650 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA11__PATA_DATA_11 0x2d0 0x654 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA11__GPIO2_11 0x2d0 0x654 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x2d0 0x654 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 0x2d0 0x654 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x2d0 0x654 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 0x2d0 0x654 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 0x2d0 0x654 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA12__PATA_DATA_12 0x2d4 0x658 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA12__GPIO2_12 0x2d4 0x658 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 0x2d4 0x658 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 0x2d4 0x658 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 0x2d4 0x658 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 0x2d4 0x658 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 0x2d4 0x658 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA13__PATA_DATA_13 0x2d8 0x65c 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA13__GPIO2_13 0x2d8 0x65c 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 0x2d8 0x65c 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 0x2d8 0x65c 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 0x2d8 0x65c 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 0x2d8 0x65c 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 0x2d8 0x65c 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA14__PATA_DATA_14 0x2dc 0x660 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA14__GPIO2_14 0x2dc 0x660 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 0x2dc 0x660 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 0x2dc 0x660 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 0x2dc 0x660 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 0x2dc 0x660 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 0x2dc 0x660 0x000 0x6 0x0 +#define MX53_PAD_PATA_DATA15__PATA_DATA_15 0x2e0 0x664 0x000 0x0 0x0 +#define MX53_PAD_PATA_DATA15__GPIO2_15 0x2e0 0x664 0x000 0x1 0x0 +#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 0x2e0 0x664 0x000 0x2 0x0 +#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 0x2e0 0x664 0x000 0x3 0x0 +#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 0x2e0 0x664 0x000 0x4 0x0 +#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 0x2e0 0x664 0x000 0x5 0x0 +#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 0x2e0 0x664 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x2e4 0x66c 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA0__GPIO1_16 0x2e4 0x66c 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 0x2e4 0x66c 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA0__CSPI_MISO 0x2e4 0x66c 0x784 0x5 0x2 +#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP 0x2e4 0x66c 0x778 0x7 0x0 +#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x2e8 0x670 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA1__GPIO1_17 0x2e8 0x670 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 0x2e8 0x670 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA1__CSPI_SS0 0x2e8 0x670 0x78c 0x5 0x3 +#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP 0x2e8 0x670 0x77c 0x7 0x1 +#define MX53_PAD_SD1_CMD__ESDHC1_CMD 0x2ec 0x674 0x000 0x0 0x0 +#define MX53_PAD_SD1_CMD__GPIO1_18 0x2ec 0x674 0x000 0x1 0x0 +#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 0x2ec 0x674 0x000 0x3 0x0 +#define MX53_PAD_SD1_CMD__CSPI_MOSI 0x2ec 0x674 0x788 0x5 0x2 +#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP 0x2ec 0x674 0x770 0x7 0x0 +#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x2f0 0x678 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA2__GPIO1_19 0x2f0 0x678 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 0x2f0 0x678 0x000 0x2 0x0 +#define MX53_PAD_SD1_DATA2__PWM2_PWMO 0x2f0 0x678 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B 0x2f0 0x678 0x000 0x4 0x0 +#define MX53_PAD_SD1_DATA2__CSPI_SS1 0x2f0 0x678 0x790 0x5 0x2 +#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB 0x2f0 0x678 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP 0x2f0 0x678 0x774 0x7 0x0 +#define MX53_PAD_SD1_CLK__ESDHC1_CLK 0x2f4 0x67c 0x000 0x0 0x0 +#define MX53_PAD_SD1_CLK__GPIO1_20 0x2f4 0x67c 0x000 0x1 0x0 +#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT 0x2f4 0x67c 0x000 0x2 0x0 +#define MX53_PAD_SD1_CLK__GPT_CLKIN 0x2f4 0x67c 0x000 0x3 0x0 +#define MX53_PAD_SD1_CLK__CSPI_SCLK 0x2f4 0x67c 0x780 0x5 0x2 +#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 0x2f4 0x67c 0x000 0x7 0x0 +#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x2f8 0x680 0x000 0x0 0x0 +#define MX53_PAD_SD1_DATA3__GPIO1_21 0x2f8 0x680 0x000 0x1 0x0 +#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 0x2f8 0x680 0x000 0x2 0x0 +#define MX53_PAD_SD1_DATA3__PWM1_PWMO 0x2f8 0x680 0x000 0x3 0x0 +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B 0x2f8 0x680 0x000 0x4 0x0 +#define MX53_PAD_SD1_DATA3__CSPI_SS2 0x2f8 0x680 0x794 0x5 0x2 +#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB 0x2f8 0x680 0x000 0x6 0x0 +#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 0x2f8 0x680 0x000 0x7 0x0 +#define MX53_PAD_SD2_CLK__ESDHC2_CLK 0x2fc 0x688 0x000 0x0 0x0 +#define MX53_PAD_SD2_CLK__GPIO1_10 0x2fc 0x688 0x000 0x1 0x0 +#define MX53_PAD_SD2_CLK__KPP_COL_5 0x2fc 0x688 0x840 0x2 0x2 +#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS 0x2fc 0x688 0x73c 0x3 0x1 +#define MX53_PAD_SD2_CLK__CSPI_SCLK 0x2fc 0x688 0x780 0x5 0x3 +#define MX53_PAD_SD2_CLK__SCC_RANDOM_V 0x2fc 0x688 0x000 0x7 0x0 +#define MX53_PAD_SD2_CMD__ESDHC2_CMD 0x300 0x68c 0x000 0x0 0x0 +#define MX53_PAD_SD2_CMD__GPIO1_11 0x300 0x68c 0x000 0x1 0x0 +#define MX53_PAD_SD2_CMD__KPP_ROW_5 0x300 0x68c 0x84c 0x2 0x1 +#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC 0x300 0x68c 0x738 0x3 0x1 +#define MX53_PAD_SD2_CMD__CSPI_MOSI 0x300 0x68c 0x788 0x5 0x3 +#define MX53_PAD_SD2_CMD__SCC_RANDOM 0x300 0x68c 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x304 0x690 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA3__GPIO1_12 0x304 0x690 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA3__KPP_COL_6 0x304 0x690 0x844 0x2 0x1 +#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x304 0x690 0x740 0x3 0x1 +#define MX53_PAD_SD2_DATA3__CSPI_SS2 0x304 0x690 0x794 0x5 0x3 +#define MX53_PAD_SD2_DATA3__SJC_DONE 0x304 0x690 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x308 0x694 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA2__GPIO1_13 0x308 0x694 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA2__KPP_ROW_6 0x308 0x694 0x850 0x2 0x1 +#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x308 0x694 0x734 0x3 0x1 +#define MX53_PAD_SD2_DATA2__CSPI_SS1 0x308 0x694 0x790 0x5 0x3 +#define MX53_PAD_SD2_DATA2__SJC_FAIL 0x308 0x694 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x30c 0x698 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA1__GPIO1_14 0x30c 0x698 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA1__KPP_COL_7 0x30c 0x698 0x848 0x2 0x1 +#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x30c 0x698 0x744 0x3 0x1 +#define MX53_PAD_SD2_DATA1__CSPI_SS0 0x30c 0x698 0x78c 0x5 0x4 +#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO 0x30c 0x698 0x000 0x7 0x0 +#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x310 0x69c 0x000 0x0 0x0 +#define MX53_PAD_SD2_DATA0__GPIO1_15 0x310 0x69c 0x000 0x1 0x0 +#define MX53_PAD_SD2_DATA0__KPP_ROW_7 0x310 0x69c 0x854 0x2 0x1 +#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x310 0x69c 0x730 0x3 0x1 +#define MX53_PAD_SD2_DATA0__CSPI_MISO 0x310 0x69c 0x784 0x5 0x3 +#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT 0x310 0x69c 0x000 0x7 0x0 +#define MX53_PAD_GPIO_0__CCM_CLKO 0x314 0x6a4 0x000 0x0 0x0 +#define MX53_PAD_GPIO_0__GPIO1_0 0x314 0x6a4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_0__KPP_COL_5 0x314 0x6a4 0x840 0x2 0x3 +#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x314 0x6a4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_0__EPIT1_EPITO 0x314 0x6a4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB 0x314 0x6a4 0x000 0x5 0x0 +#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR 0x314 0x6a4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_0__CSU_TD 0x314 0x6a4 0x000 0x7 0x0 +#define MX53_PAD_GPIO_1__ESAI1_SCKR 0x318 0x6a8 0x7dc 0x0 0x1 +#define MX53_PAD_GPIO_1__GPIO1_1 0x318 0x6a8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_1__KPP_ROW_5 0x318 0x6a8 0x84c 0x2 0x2 +#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK 0x318 0x6a8 0x000 0x3 0x0 +#define MX53_PAD_GPIO_1__PWM2_PWMO 0x318 0x6a8 0x000 0x4 0x0 +#define MX53_PAD_GPIO_1__WDOG2_WDOG_B 0x318 0x6a8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_1__ESDHC1_CD 0x318 0x6a8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_1__SRC_TESTER_ACK 0x318 0x6a8 0x000 0x7 0x0 +#define MX53_PAD_GPIO_9__ESAI1_FSR 0x31c 0x6ac 0x7cc 0x0 0x1 +#define MX53_PAD_GPIO_9__GPIO1_9 0x31c 0x6ac 0x000 0x1 0x0 +#define MX53_PAD_GPIO_9__KPP_COL_6 0x31c 0x6ac 0x844 0x2 0x2 +#define MX53_PAD_GPIO_9__CCM_REF_EN_B 0x31c 0x6ac 0x000 0x3 0x0 +#define MX53_PAD_GPIO_9__PWM1_PWMO 0x31c 0x6ac 0x000 0x4 0x0 +#define MX53_PAD_GPIO_9__WDOG1_WDOG_B 0x31c 0x6ac 0x000 0x5 0x0 +#define MX53_PAD_GPIO_9__ESDHC1_WP 0x31c 0x6ac 0x7fc 0x6 0x1 +#define MX53_PAD_GPIO_9__SCC_FAIL_STATE 0x31c 0x6ac 0x000 0x7 0x0 +#define MX53_PAD_GPIO_3__ESAI1_HCKR 0x320 0x6b0 0x7d4 0x0 0x1 +#define MX53_PAD_GPIO_3__GPIO1_3 0x320 0x6b0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_3__I2C3_SCL 0x320 0x6b0 0x824 0x2 0x1 +#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN 0x320 0x6b0 0x000 0x3 0x0 +#define MX53_PAD_GPIO_3__CCM_CLKO2 0x320 0x6b0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 0x320 0x6b0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x320 0x6b0 0x8a0 0x6 0x1 +#define MX53_PAD_GPIO_3__MLB_MLBCLK 0x320 0x6b0 0x858 0x7 0x2 +#define MX53_PAD_GPIO_6__ESAI1_SCKT 0x324 0x6b4 0x7e0 0x0 0x1 +#define MX53_PAD_GPIO_6__GPIO1_6 0x324 0x6b4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_6__I2C3_SDA 0x324 0x6b4 0x828 0x2 0x1 +#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 0x324 0x6b4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB 0x324 0x6b4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 0x324 0x6b4 0x000 0x5 0x0 +#define MX53_PAD_GPIO_6__ESDHC2_LCTL 0x324 0x6b4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_6__MLB_MLBSIG 0x324 0x6b4 0x860 0x7 0x2 +#define MX53_PAD_GPIO_2__ESAI1_FST 0x328 0x6b8 0x7d0 0x0 0x1 +#define MX53_PAD_GPIO_2__GPIO1_2 0x328 0x6b8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_2__KPP_ROW_6 0x328 0x6b8 0x850 0x2 0x2 +#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 0x328 0x6b8 0x000 0x3 0x0 +#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 0x328 0x6b8 0x000 0x4 0x0 +#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 0x328 0x6b8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_2__ESDHC2_WP 0x328 0x6b8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_2__MLB_MLBDAT 0x328 0x6b8 0x85c 0x7 0x2 +#define MX53_PAD_GPIO_4__ESAI1_HCKT 0x32c 0x6bc 0x7d8 0x0 0x1 +#define MX53_PAD_GPIO_4__GPIO1_4 0x32c 0x6bc 0x000 0x1 0x0 +#define MX53_PAD_GPIO_4__KPP_COL_7 0x32c 0x6bc 0x848 0x2 0x2 +#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 0x32c 0x6bc 0x000 0x3 0x0 +#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 0x32c 0x6bc 0x000 0x4 0x0 +#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 0x32c 0x6bc 0x000 0x5 0x0 +#define MX53_PAD_GPIO_4__ESDHC2_CD 0x32c 0x6bc 0x000 0x6 0x0 +#define MX53_PAD_GPIO_4__SCC_SEC_STATE 0x32c 0x6bc 0x000 0x7 0x0 +#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 0x330 0x6c0 0x7ec 0x0 0x1 +#define MX53_PAD_GPIO_5__GPIO1_5 0x330 0x6c0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_5__KPP_ROW_7 0x330 0x6c0 0x854 0x2 0x2 +#define MX53_PAD_GPIO_5__CCM_CLKO 0x330 0x6c0 0x000 0x3 0x0 +#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 0x330 0x6c0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 0x330 0x6c0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_5__I2C3_SCL 0x330 0x6c0 0x824 0x6 0x2 +#define MX53_PAD_GPIO_5__CCM_PLL1_BYP 0x330 0x6c0 0x770 0x7 0x1 +#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 0x334 0x6c4 0x7f4 0x0 0x1 +#define MX53_PAD_GPIO_7__GPIO1_7 0x334 0x6c4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_7__EPIT1_EPITO 0x334 0x6c4 0x000 0x2 0x0 +#define MX53_PAD_GPIO_7__CAN1_TXCAN 0x334 0x6c4 0x000 0x3 0x0 +#define MX53_PAD_GPIO_7__UART2_TXD_MUX 0x334 0x6c4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_7__FIRI_RXD 0x334 0x6c4 0x80c 0x5 0x1 +#define MX53_PAD_GPIO_7__SPDIF_PLOCK 0x334 0x6c4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_7__CCM_PLL2_BYP 0x334 0x6c4 0x774 0x7 0x1 +#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 0x338 0x6c8 0x7f8 0x0 0x1 +#define MX53_PAD_GPIO_8__GPIO1_8 0x338 0x6c8 0x000 0x1 0x0 +#define MX53_PAD_GPIO_8__EPIT2_EPITO 0x338 0x6c8 0x000 0x2 0x0 +#define MX53_PAD_GPIO_8__CAN1_RXCAN 0x338 0x6c8 0x760 0x3 0x2 +#define MX53_PAD_GPIO_8__UART2_RXD_MUX 0x338 0x6c8 0x880 0x4 0x5 +#define MX53_PAD_GPIO_8__FIRI_TXD 0x338 0x6c8 0x000 0x5 0x0 +#define MX53_PAD_GPIO_8__SPDIF_SRCLK 0x338 0x6c8 0x000 0x6 0x0 +#define MX53_PAD_GPIO_8__CCM_PLL3_BYP 0x338 0x6c8 0x778 0x7 0x1 +#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 0x33c 0x6cc 0x7f0 0x0 0x1 +#define MX53_PAD_GPIO_16__GPIO7_11 0x33c 0x6cc 0x000 0x1 0x0 +#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT 0x33c 0x6cc 0x000 0x2 0x0 +#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 0x33c 0x6cc 0x000 0x4 0x0 +#define MX53_PAD_GPIO_16__SPDIF_IN1 0x33c 0x6cc 0x870 0x5 0x1 +#define MX53_PAD_GPIO_16__I2C3_SDA 0x33c 0x6cc 0x828 0x6 0x2 +#define MX53_PAD_GPIO_16__SJC_DE_B 0x33c 0x6cc 0x000 0x7 0x0 +#define MX53_PAD_GPIO_17__ESAI1_TX0 0x340 0x6d0 0x7e4 0x0 0x1 +#define MX53_PAD_GPIO_17__GPIO7_12 0x340 0x6d0 0x000 0x1 0x0 +#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 0x340 0x6d0 0x868 0x2 0x1 +#define MX53_PAD_GPIO_17__GPC_PMIC_RDY 0x340 0x6d0 0x810 0x3 0x1 +#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG 0x340 0x6d0 0x000 0x4 0x0 +#define MX53_PAD_GPIO_17__SPDIF_OUT1 0x340 0x6d0 0x000 0x5 0x0 +#define MX53_PAD_GPIO_17__IPU_SNOOP2 0x340 0x6d0 0x000 0x6 0x0 +#define MX53_PAD_GPIO_17__SJC_JTAG_ACT 0x340 0x6d0 0x000 0x7 0x0 +#define MX53_PAD_GPIO_18__ESAI1_TX1 0x344 0x6d4 0x7e8 0x0 0x1 +#define MX53_PAD_GPIO_18__GPIO7_13 0x344 0x6d4 0x000 0x1 0x0 +#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 0x344 0x6d4 0x86c 0x2 0x1 +#define MX53_PAD_GPIO_18__OWIRE_LINE 0x344 0x6d4 0x864 0x3 0x1 +#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG 0x344 0x6d4 0x000 0x4 0x0 +#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK 0x344 0x6d4 0x768 0x5 0x1 +#define MX53_PAD_GPIO_18__ESDHC1_LCTL 0x344 0x6d4 0x000 0x6 0x0 +#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST 0x344 0x6d4 0x000 0x7 0x0 + +#endif /* __DTS_IMX53_PINFUNC_H */ diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi new file mode 100644 index 0000000..1bdf066 --- /dev/null +++ b/arch/arm/dts/imx53.dtsi @@ -0,0 +1,110 @@ +/* + * Copyright 2016 Beckhoff Automation + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "skeleton.dtsi" +#include "imx53-pinfunc.h" +#include <dt-bindings/clock/imx5-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + serial1 = &uart2; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aips@50000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x10000000>; + ranges; + + iomuxc: iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + }; + + gpr: iomuxc-gpr@53fa8000 { + compatible = "fsl,imx53-iomuxc-gpr", "syscon"; + reg = <0x53fa8000 0xc>; + }; + + uart2: serial@53fc0000 { + compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, + <&clks IMX5_CLK_UART2_PER_GATE>; + clock-names = "ipg", "per"; + dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + clks: ccm@53fd4000{ + compatible = "fsl,imx53-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 0x04 0 72 0x04>; + #clock-cells = <1>; + }; + + gpio7: gpio@53fe4000 { + compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; + reg = <0x53fe4000 0x4000>; + interrupts = <107 108>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + aips@60000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x60000000 0x10000000>; + ranges; + + sdma: sdma@63fb0000 { + compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; + reg = <0x63fb0000 0x4000>; + interrupts = <6>; + clocks = <&clks IMX5_CLK_SDMA_GATE>, + <&clks IMX5_CLK_SDMA_GATE>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + + fec: ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + clocks = <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>, + <&clks IMX5_CLK_FEC_GATE>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + }; + }; +}; diff --git a/board/beckhoff/mx53cx9020/Kconfig b/board/beckhoff/mx53cx9020/Kconfig new file mode 100644 index 0000000..dcdafb6 --- /dev/null +++ b/board/beckhoff/mx53cx9020/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX53CX9020 + +config SYS_BOARD + default "mx53cx9020" + +config SYS_VENDOR + default "beckhoff" + +config SYS_CONFIG_NAME + default "mx53cx9020" + +endif diff --git a/board/beckhoff/mx53cx9020/MAINTAINERS b/board/beckhoff/mx53cx9020/MAINTAINERS new file mode 100644 index 0000000..f84413e --- /dev/null +++ b/board/beckhoff/mx53cx9020/MAINTAINERS @@ -0,0 +1,6 @@ +MX53 CX9020 +M: Patrick Bruenn <p.bruenn(a)beckhoff.com> +S: Maintained +F: board/beckhoff/mx53cx9020/ +F: include/configs/mx53cx9020.h +F: configs/mx53cx9020_defconfig diff --git a/board/beckhoff/mx53cx9020/Makefile b/board/beckhoff/mx53cx9020/Makefile new file mode 100644 index 0000000..a01c0f1 --- /dev/null +++ b/board/beckhoff/mx53cx9020/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG +# Patrick Bruenn <p.bruenn(a)beckhoff.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += mx53cx9020.o +obj-$(CONFIG_VIDEO) += mx53cx9020_video.o diff --git a/board/beckhoff/mx53cx9020/imximage.cfg b/board/beckhoff/mx53cx9020/imximage.cfg new file mode 100644 index 0000000..a11d04c --- /dev/null +++ b/board/beckhoff/mx53cx9020/imximage.cfg @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH + * Patrick Bruenn <p.bruenn(a)beckhoff.com> + * + * Based on <u-boot>/board/freescale/mx53loco/imximage.cfg + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8724 0x00000000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0x83190000 +DATA 4 0x63fd900c 0x40425333 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x05208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00005800 +DATA 4 0x63fd9040 0x05380003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c new file mode 100644 index 0000000..9b3ac22 --- /dev/null +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG + * Patrick Bruenn <p.bruenn(a)beckhoff.com> + * + * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux-mx53.h> +#include <asm/arch/clock.h> +#include <asm/imx-common/mx5_video.h> +#include <ACEX1K.h> +#include <netdev.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/gpio.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <fs.h> +#include <dm/platdata.h> +#include <dm/platform_data/serial_mxc.h> + +enum LED_GPIOS { + GPIO_SD1_CD = IMX_GPIO_NR(1, 1), + GPIO_SD2_CD = IMX_GPIO_NR(1, 4), + GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16), + GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17), + GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18), + GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19), + GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20), + GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21), + GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22), + GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23), + GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24), + GPIO_SUPS_INT = IMX_GPIO_NR(3, 31), + GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8), + GPIO_C3_STATUS = IMX_GPIO_NR(6, 7), + GPIO_C3_DONE = IMX_GPIO_NR(6, 9), +}; + +#define CCAT_BASE_ADDR ((void *)0xf0000000) +#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32)) +#define CCAT_SIZE 1191788 +#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12) +static const char CCAT_SIGNATURE[] = "CCAT"; + +static const u32 CCAT_MODE_CONFIG = 0x0024DC81; +static const u32 CCAT_MODE_RUN = 0x0033DC8F; + +DECLARE_GLOBAL_DATA_PTR; + +static uint32_t mx53_dram_size[2]; + +phys_size_t get_effective_memsize(void) +{ + /* + * WARNING: We must override get_effective_memsize() function here + * to report only the size of the first DRAM bank. This is to make + * U-Boot relocator place U-Boot into valid memory, that is, at the + * end of the first DRAM bank. If we did not override this function + * like so, U-Boot would be placed at the address of the first DRAM + * bank + total DRAM size - sizeof(uboot), which in the setup where + * each DRAM bank contains 512MiB of DRAM would result in placing + * U-Boot into invalid memory area close to the end of the first + * DRAM bank. + */ + return mx53_dram_size[0]; +} + +int dram_init(void) +{ + mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); + mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); + + gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = mx53_dram_size[0]; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = mx53_dram_size[1]; +} + +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +/* + * Set CCAT mode + * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN + */ +void weim_cs0_settings(u32 mode) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + writel(0x0, &weim_regs->cs0gcr1); + writel(mode, &weim_regs->cs0gcr1); + writel(0x00001002, &weim_regs->cs0gcr2); + + writel(0x04000000, &weim_regs->cs0rcr1); + writel(0x00000000, &weim_regs->cs0rcr2); + + writel(0x04000000, &weim_regs->cs0wcr1); + writel(0x00000000, &weim_regs->cs0wcr2); +} + +static void setup_gpio_eim(void) +{ + gpio_direction_input(GPIO_C3_STATUS); + gpio_direction_input(GPIO_C3_DONE); + gpio_direction_output(GPIO_C3_CONFIG, 1); + + weim_cs0_settings(CCAT_MODE_RUN); +} + +static void setup_gpio_sups(void) +{ + gpio_direction_input(GPIO_SUPS_INT); + + static const int BLINK_INTERVALL = 50000; + int status = 1; + while (gpio_get_value(GPIO_SUPS_INT)) { + /* signal "CX SUPS power fail" */ + gpio_set_value(GPIO_LED_PWR_R, + (++status / BLINK_INTERVALL) % 2); + } + + /* signal "CX power up" */ + gpio_set_value(GPIO_LED_PWR_R, 1); +} + +static void setup_gpio_leds(void) +{ + gpio_direction_output(GPIO_LED_SD2_R, 0); + gpio_direction_output(GPIO_LED_SD2_B, 0); + gpio_direction_output(GPIO_LED_SD2_G, 0); + gpio_direction_output(GPIO_LED_SD1_R, 0); + gpio_direction_output(GPIO_LED_SD1_B, 0); + gpio_direction_output(GPIO_LED_SD1_G, 0); + gpio_direction_output(GPIO_LED_PWR_R, 0); + gpio_direction_output(GPIO_LED_PWR_B, 0); + gpio_direction_output(GPIO_LED_PWR_G, 0); +} + +#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{ + /* request VBUS power enable pin, GPIO7_8 */ + gpio_direction_output(IMX_GPIO_NR(7, 8), 1); + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR}, + {MMC_SDHC2_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret; + + gpio_direction_input(GPIO_SD1_CD); + gpio_direction_input(GPIO_SD2_CD); + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + ret = !gpio_get_value(GPIO_SD1_CD); + else + ret = !gpio_get_value(GPIO_SD2_CD); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + u32 index; + int ret; + + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { + switch (index) { + case 0: + break; + case 1: + break; + default: + printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n", + CONFIG_SYS_FSL_ESDHC_NUM); + return -EINVAL; + } + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; +} +#endif + +static int power_init(void) +{ + /* nothing to do on CX9020 */ + return 0; +} + +static void clock_1GHz(void) +{ + int ret; + u32 ref_clk = MXC_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + +int board_early_init_f(void) +{ + setup_gpio_leds(); + setup_gpio_sups(); + setup_gpio_eim(); + setup_iomux_lcd(); + + return 0; +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + mxc_set_sata_internal_clock(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: Beckhoff CX9020\n"); + + return 0; +} + +static int ccat_config_fn(int assert_config, int flush, int cookie) +{ + /* prepare FPGA for programming */ + weim_cs0_settings(CCAT_MODE_CONFIG); + gpio_set_value(GPIO_C3_CONFIG, 0); + udelay(1); + gpio_set_value(GPIO_C3_CONFIG, 1); + udelay(230); + + return FPGA_SUCCESS; +} + +static int ccat_status_fn(int cookie) +{ + return FPGA_FAIL; +} + +static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie) +{ + const uint8_t *const buffer = buf; + + /* program CCAT */ + int i; + for (i = 0; i < buf_len; ++i) + writeb(buffer[i], CCAT_BASE_ADDR); + + writeb(0xff, CCAT_BASE_ADDR); + writeb(0xff, CCAT_BASE_ADDR); + + return FPGA_SUCCESS; +} + +static int ccat_done_fn(int cookie) +{ + /* programming complete? */ + return gpio_get_value(GPIO_C3_DONE); +} + +static int ccat_post_fn(int cookie) +{ + /* switch to FPGA run mode */ + weim_cs0_settings(CCAT_MODE_RUN); + invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR); + + if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) { + printf("Verifing CCAT firmware failed, signature not found\n"); + return FPGA_FAIL; + } + + /* signal "CX booting OS" */ + gpio_set_value(GPIO_LED_PWR_R, 1); + gpio_set_value(GPIO_LED_PWR_G, 1); + gpio_set_value(GPIO_LED_PWR_B, 0); + return FPGA_SUCCESS; +} + +static Altera_CYC2_Passive_Serial_fns ccat_fns = { + .config = ccat_config_fn, + .status = ccat_status_fn, + .done = ccat_done_fn, + .write = ccat_write_fn, + .abort = ccat_post_fn, + .post = ccat_post_fn, +}; + +static Altera_desc ccat_fpga = { + .family = Altera_CYC2, + .iface = passive_serial, + .size = CCAT_SIZE, + .iface_fns = &ccat_fns, + .base = CCAT_BASE_ADDR, +}; + +int board_late_init(void) +{ + if (!power_init()) + clock_1GHz(); + + fpga_init(); + fpga_add(fpga_altera, &ccat_fpga); + + return 0; +} diff --git a/board/beckhoff/mx53cx9020/mx53cx9020_video.c b/board/beckhoff/mx53cx9020/mx53cx9020_video.c new file mode 100644 index 0000000..4da83da --- /dev/null +++ b/board/beckhoff/mx53cx9020/mx53cx9020_video.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG + * Patrick Bruenn <p.bruenn(a)beckhoff.com> + * + * Based on <u-boot>/board/freescale/mx53loco/mx53loco_video.c + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/list.h> +#include <asm/gpio.h> +#include <asm/arch/iomux-mx53.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> + +#define CX9020_DVI_PWD IMX_GPIO_NR(6, 1) + +static struct fb_videomode const vga_640x480 = { + .name = "VESA_VGA_640x480", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39721, /* picosecond (25.175 MHz) */ + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +}; + +void setup_iomux_lcd(void) +{ + /* Turn on DVI_PWD */ + imx_iomux_v3_setup_pad(MX53_PAD_CSI0_DAT15__GPIO6_1); + gpio_direction_output(CX9020_DVI_PWD, 1); +} + +int board_video_skip(void) +{ + const int ret = ipuv3_fb_init(&vga_640x480, 0, IPU_PIX_FMT_RGB24); + if (ret) + printf("VESA VG 640x480 cannot be configured: %d\n", ret); + return ret; +} diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig new file mode 100644 index 0000000..3603907 --- /dev/null +++ b/configs/mx53cx9020_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX5=y +CONFIG_TARGET_MX53CX9020=y +CONFIG_DEFAULT_DEVICE_TREE="imx53-cx9020" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/beckhoff/mx53cx9020/imximage.cfg" +CONFIG_BOOTDELAY=1 +CONFIG_HUSH_PARSER=y +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +#CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_MXC_UART=y +CONFIG_OF_CONTROL=y +CONFIG_FPGA_ALTERA=y +CONFIG_FPGA_CYCLON2=y +CONFIG_CMD_FPGA=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX5=y diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index f3f6bf7..a760944 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -3,6 +3,26 @@ menu "FPGA support" config FPGA bool +config FPGA_ALTERA + bool "Enable Altera FPGA drivers" + select FPGA + help + Say Y here to enable the Altera FPGA driver + + This provides basic infrastructure to support Altera FPGA devices. + Enable Altera FPGA specific functions which includes bitstream + (in BIT format), fpga and device validation. + +config FPGA_CYCLON2 + bool "Enable Altera FPGA driver for Cyclone II" + depends on FPGA_ALTERA + help + Say Y here to enable the Altera Cyclone II FPGA specific driver + + This provides common functionality for Altera Cyclone II devices. + Enable FPGA driver for loading bitstream in BIT and BIN format + on Altera Cyclone II device. + config FPGA_XILINX bool "Enable Xilinx FPGA drivers" select FPGA diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7b9961d..a1dd87d 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -131,7 +131,7 @@ config ETHOC config FEC_MXC bool "FEC Ethernet controller" - depends on MX6 + depends on MX5 || MX6 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 35640f0..238f77d 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -1,6 +1,20 @@ config PINCTRL_IMX bool +config PINCTRL_IMX5 + bool "IMX5 pinctrl driver" + depends on ARCH_MX5 && PINCTRL_FULL + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the imx5 pinctrl driver + + This provides a simple pinctrl driver for i.MX 53SoC familiy, + i.MX53. This feature depends on device tree + configuration. This driver is different from the linux one, + this is a simple implementation, only parses the 'fsl,pins' + property and configure related registers. + config PINCTRL_IMX6 bool "IMX6 pinctrl driver" depends on ARCH_MX6 && PINCTRL_FULL diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index 0ee7f2f..e0f7325 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o +obj-$(CONFIG_PINCTRL_IMX5) += pinctrl-imx5.o obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c new file mode 100644 index 0000000..6942f39 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx5.c @@ -0,0 +1,44 @@ + +/* + * Copyright (C) 2016 Peng Fan <van.freenix(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm/device.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx5_pinctrl_soc_info; + +static int imx5_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx5_pinctrl_match[] = { + { + .compatible = "fsl,imx53-iomuxc", + .data = (ulong)&imx5_pinctrl_soc_info + }, + { + .compatible = "fsl,imx53-iomuxc-gpr", + .data = (ulong)&imx5_pinctrl_soc_info + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx5_pinctrl) = { + .name = "imx5-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx5_pinctrl_match), + .probe = imx5_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 317d158..cd2b73b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -311,7 +311,7 @@ config MVEBU_A3700_UART config MXC_UART bool "IMX serial port support" - depends on MX6 + depends on MX5 || MX6 help If you have a machine based on a Motorola IMX CPU you can enable its onboard serial port by enabling this option. diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h new file mode 100644 index 0000000..ac8b2a2 --- /dev/null +++ b/include/configs/mx53cx9020.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG + * Patrick Bruenn <p.bruenn(a)beckhoff.com> + * + * Configuration settings for Beckhoff CX9020. + * + * Based on Freescale's Linux i.MX mx53loco.h file: + * Copyright (C) 2010-2011 Freescale Semiconductor. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_FSL_CLK + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_GPIO +#define CONFIG_REVISION_TAG + +#define CONFIG_MXC_UART_BASE UART2_BASE + +#define CONFIG_FPGA_COUNT 1 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC + +/* bootz: zImage/initrd.img support */ +#define CONFIG_DOS_PARTITION + +/* Eth Configs */ +#define CONFIG_MII +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_ETHPRIME "FEC0" +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +/* USB Configs */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_MCS7830 +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#define CONFIG_SUPPORT_RAW_INITRD + +#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE 0x77800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr=0x71ff0000\0" \ + "rdaddr=0x72000000\0" \ + "console=ttymxc1,115200\0" \ + "uenv=/boot/uEnv.txt\0" \ + "optargs=\0" \ + "cmdline=\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcrootfstype=ext4 rootwait fixrtc\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \ + "rootfstype=${mmcrootfstype} " \ + "${cmdline}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadrd=load mmc ${bootpart} ${rdaddr} ${bootdir}/${rdfile};" \ + "setenv rdsize ${filesize}\0" \ + "loadfdt=echo loading ${fdt_path} ...;" \ + "load mmc ${bootpart} ${fdt_addr} ${fdt_path}\0" \ + "mmcboot=mmc dev ${mmcdev}; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "echo Checking for: ${uenv} ...;" \ + "setenv bootpart ${mmcdev}:${mmcpart};" \ + "if test -e mmc ${bootpart} ${uenv}; then " \ + "load mmc ${bootpart} ${loadaddr} ${uenv};" \ + "env import -t ${loadaddr} ${filesize};" \ + "echo Loaded environment from ${uenv};" \ + "if test -n ${dtb}; then " \ + "setenv fdt_file ${dtb};" \ + "echo Using: dtb=${fdt_file} ...;" \ + "fi;" \ + "echo Checking for uname_r in ${uenv}...;" \ + "if test -n ${uname_r}; then " \ + "echo Running uname_boot ...;" \ + "run uname_boot;" \ + "fi;" \ + "fi;" \ + "fi;\0" \ + "uname_boot="\ + "setenv bootdir /boot; " \ + "setenv bootfile vmlinuz-${uname_r}; " \ + "setenv ccatfile /boot/ccat.rbf; " \ + "echo loading CCAT firmware from ${ccatfile}; " \ + "load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \ + "fpga load 0 ${loadaddr} ${filesize}; " \ + "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \ + "echo loading ${bootdir}/${bootfile} ...; " \ + "run loadimage;" \ + "setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \ + "if test -e mmc ${bootpart} ${fdt_path}; then " \ + "run loadfdt;" \ + "else " \ + "echo; echo unable to find ${fdt_file} ...;" \ + "echo booting legacy ...;"\ + "run mmcargs;" \ + "echo debug: [${bootargs}] ... ;" \ + "echo debug: [bootz ${loadaddr}] ... ;" \ + "bootz ${loadaddr}; " \ + "fi;" \ + "run mmcargs;" \ + "echo debug: [${bootargs}] ... ;" \ + "echo debug: [bootz ${loadaddr} - ${fdt_addr}] ... ;" \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "run mmcboot;" + +#define CONFIG_ARP_TIMEOUT 200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x70000000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) +#define PHYS_SDRAM_SIZE (gd->ram_size) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* Framebuffer and LCD */ +#define CONFIG_PREBOOT +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 200000000 + +#endif /* __CONFIG_H */ diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h new file mode 100644 index 0000000..d382fc7 --- /dev/null +++ b/include/dt-bindings/clock/imx5-clock.h @@ -0,0 +1,219 @@ +/* + * Copyright 2013 Lucas Stach, Pengutronix <l.stach(a)pengutronix.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX5_H +#define __DT_BINDINGS_CLOCK_IMX5_H + +#define IMX5_CLK_DUMMY 0 +#define IMX5_CLK_CKIL 1 +#define IMX5_CLK_OSC 2 +#define IMX5_CLK_CKIH1 3 +#define IMX5_CLK_CKIH2 4 +#define IMX5_CLK_AHB 5 +#define IMX5_CLK_IPG 6 +#define IMX5_CLK_AXI_A 7 +#define IMX5_CLK_AXI_B 8 +#define IMX5_CLK_UART_PRED 9 +#define IMX5_CLK_UART_ROOT 10 +#define IMX5_CLK_ESDHC_A_PRED 11 +#define IMX5_CLK_ESDHC_B_PRED 12 +#define IMX5_CLK_ESDHC_C_SEL 13 +#define IMX5_CLK_ESDHC_D_SEL 14 +#define IMX5_CLK_EMI_SEL 15 +#define IMX5_CLK_EMI_SLOW_PODF 16 +#define IMX5_CLK_NFC_PODF 17 +#define IMX5_CLK_ECSPI_PRED 18 +#define IMX5_CLK_ECSPI_PODF 19 +#define IMX5_CLK_USBOH3_PRED 20 +#define IMX5_CLK_USBOH3_PODF 21 +#define IMX5_CLK_USB_PHY_PRED 22 +#define IMX5_CLK_USB_PHY_PODF 23 +#define IMX5_CLK_CPU_PODF 24 +#define IMX5_CLK_DI_PRED 25 +#define IMX5_CLK_TVE_SEL 27 +#define IMX5_CLK_UART1_IPG_GATE 28 +#define IMX5_CLK_UART1_PER_GATE 29 +#define IMX5_CLK_UART2_IPG_GATE 30 +#define IMX5_CLK_UART2_PER_GATE 31 +#define IMX5_CLK_UART3_IPG_GATE 32 +#define IMX5_CLK_UART3_PER_GATE 33 +#define IMX5_CLK_I2C1_GATE 34 +#define IMX5_CLK_I2C2_GATE 35 +#define IMX5_CLK_GPT_IPG_GATE 36 +#define IMX5_CLK_PWM1_IPG_GATE 37 +#define IMX5_CLK_PWM1_HF_GATE 38 +#define IMX5_CLK_PWM2_IPG_GATE 39 +#define IMX5_CLK_PWM2_HF_GATE 40 +#define IMX5_CLK_GPT_HF_GATE 41 +#define IMX5_CLK_FEC_GATE 42 +#define IMX5_CLK_USBOH3_PER_GATE 43 +#define IMX5_CLK_ESDHC1_IPG_GATE 44 +#define IMX5_CLK_ESDHC2_IPG_GATE 45 +#define IMX5_CLK_ESDHC3_IPG_GATE 46 +#define IMX5_CLK_ESDHC4_IPG_GATE 47 +#define IMX5_CLK_SSI1_IPG_GATE 48 +#define IMX5_CLK_SSI2_IPG_GATE 49 +#define IMX5_CLK_SSI3_IPG_GATE 50 +#define IMX5_CLK_ECSPI1_IPG_GATE 51 +#define IMX5_CLK_ECSPI1_PER_GATE 52 +#define IMX5_CLK_ECSPI2_IPG_GATE 53 +#define IMX5_CLK_ECSPI2_PER_GATE 54 +#define IMX5_CLK_CSPI_IPG_GATE 55 +#define IMX5_CLK_SDMA_GATE 56 +#define IMX5_CLK_EMI_SLOW_GATE 57 +#define IMX5_CLK_IPU_SEL 58 +#define IMX5_CLK_IPU_GATE 59 +#define IMX5_CLK_NFC_GATE 60 +#define IMX5_CLK_IPU_DI1_GATE 61 +#define IMX5_CLK_VPU_SEL 62 +#define IMX5_CLK_VPU_GATE 63 +#define IMX5_CLK_VPU_REFERENCE_GATE 64 +#define IMX5_CLK_UART4_IPG_GATE 65 +#define IMX5_CLK_UART4_PER_GATE 66 +#define IMX5_CLK_UART5_IPG_GATE 67 +#define IMX5_CLK_UART5_PER_GATE 68 +#define IMX5_CLK_TVE_GATE 69 +#define IMX5_CLK_TVE_PRED 70 +#define IMX5_CLK_ESDHC1_PER_GATE 71 +#define IMX5_CLK_ESDHC2_PER_GATE 72 +#define IMX5_CLK_ESDHC3_PER_GATE 73 +#define IMX5_CLK_ESDHC4_PER_GATE 74 +#define IMX5_CLK_USB_PHY_GATE 75 +#define IMX5_CLK_HSI2C_GATE 76 +#define IMX5_CLK_MIPI_HSC1_GATE 77 +#define IMX5_CLK_MIPI_HSC2_GATE 78 +#define IMX5_CLK_MIPI_ESC_GATE 79 +#define IMX5_CLK_MIPI_HSP_GATE 80 +#define IMX5_CLK_LDB_DI1_DIV_3_5 81 +#define IMX5_CLK_LDB_DI1_DIV 82 +#define IMX5_CLK_LDB_DI0_DIV_3_5 83 +#define IMX5_CLK_LDB_DI0_DIV 84 +#define IMX5_CLK_LDB_DI1_GATE 85 +#define IMX5_CLK_CAN2_SERIAL_GATE 86 +#define IMX5_CLK_CAN2_IPG_GATE 87 +#define IMX5_CLK_I2C3_GATE 88 +#define IMX5_CLK_LP_APM 89 +#define IMX5_CLK_PERIPH_APM 90 +#define IMX5_CLK_MAIN_BUS 91 +#define IMX5_CLK_AHB_MAX 92 +#define IMX5_CLK_AIPS_TZ1 93 +#define IMX5_CLK_AIPS_TZ2 94 +#define IMX5_CLK_TMAX1 95 +#define IMX5_CLK_TMAX2 96 +#define IMX5_CLK_TMAX3 97 +#define IMX5_CLK_SPBA 98 +#define IMX5_CLK_UART_SEL 99 +#define IMX5_CLK_ESDHC_A_SEL 100 +#define IMX5_CLK_ESDHC_B_SEL 101 +#define IMX5_CLK_ESDHC_A_PODF 102 +#define IMX5_CLK_ESDHC_B_PODF 103 +#define IMX5_CLK_ECSPI_SEL 104 +#define IMX5_CLK_USBOH3_SEL 105 +#define IMX5_CLK_USB_PHY_SEL 106 +#define IMX5_CLK_IIM_GATE 107 +#define IMX5_CLK_USBOH3_GATE 108 +#define IMX5_CLK_EMI_FAST_GATE 109 +#define IMX5_CLK_IPU_DI0_GATE 110 +#define IMX5_CLK_GPC_DVFS 111 +#define IMX5_CLK_PLL1_SW 112 +#define IMX5_CLK_PLL2_SW 113 +#define IMX5_CLK_PLL3_SW 114 +#define IMX5_CLK_IPU_DI0_SEL 115 +#define IMX5_CLK_IPU_DI1_SEL 116 +#define IMX5_CLK_TVE_EXT_SEL 117 +#define IMX5_CLK_MX51_MIPI 118 +#define IMX5_CLK_PLL4_SW 119 +#define IMX5_CLK_LDB_DI1_SEL 120 +#define IMX5_CLK_DI_PLL4_PODF 121 +#define IMX5_CLK_LDB_DI0_SEL 122 +#define IMX5_CLK_LDB_DI0_GATE 123 +#define IMX5_CLK_USB_PHY1_GATE 124 +#define IMX5_CLK_USB_PHY2_GATE 125 +#define IMX5_CLK_PER_LP_APM 126 +#define IMX5_CLK_PER_PRED1 127 +#define IMX5_CLK_PER_PRED2 128 +#define IMX5_CLK_PER_PODF 129 +#define IMX5_CLK_PER_ROOT 130 +#define IMX5_CLK_SSI_APM 131 +#define IMX5_CLK_SSI1_ROOT_SEL 132 +#define IMX5_CLK_SSI2_ROOT_SEL 133 +#define IMX5_CLK_SSI3_ROOT_SEL 134 +#define IMX5_CLK_SSI_EXT1_SEL 135 +#define IMX5_CLK_SSI_EXT2_SEL 136 +#define IMX5_CLK_SSI_EXT1_COM_SEL 137 +#define IMX5_CLK_SSI_EXT2_COM_SEL 138 +#define IMX5_CLK_SSI1_ROOT_PRED 139 +#define IMX5_CLK_SSI1_ROOT_PODF 140 +#define IMX5_CLK_SSI2_ROOT_PRED 141 +#define IMX5_CLK_SSI2_ROOT_PODF 142 +#define IMX5_CLK_SSI_EXT1_PRED 143 +#define IMX5_CLK_SSI_EXT1_PODF 144 +#define IMX5_CLK_SSI_EXT2_PRED 145 +#define IMX5_CLK_SSI_EXT2_PODF 146 +#define IMX5_CLK_SSI1_ROOT_GATE 147 +#define IMX5_CLK_SSI2_ROOT_GATE 148 +#define IMX5_CLK_SSI3_ROOT_GATE 149 +#define IMX5_CLK_SSI_EXT1_GATE 150 +#define IMX5_CLK_SSI_EXT2_GATE 151 +#define IMX5_CLK_EPIT1_IPG_GATE 152 +#define IMX5_CLK_EPIT1_HF_GATE 153 +#define IMX5_CLK_EPIT2_IPG_GATE 154 +#define IMX5_CLK_EPIT2_HF_GATE 155 +#define IMX5_CLK_CAN_SEL 156 +#define IMX5_CLK_CAN1_SERIAL_GATE 157 +#define IMX5_CLK_CAN1_IPG_GATE 158 +#define IMX5_CLK_OWIRE_GATE 159 +#define IMX5_CLK_GPU3D_SEL 160 +#define IMX5_CLK_GPU2D_SEL 161 +#define IMX5_CLK_GPU3D_GATE 162 +#define IMX5_CLK_GPU2D_GATE 163 +#define IMX5_CLK_GARB_GATE 164 +#define IMX5_CLK_CKO1_SEL 165 +#define IMX5_CLK_CKO1_PODF 166 +#define IMX5_CLK_CKO1 167 +#define IMX5_CLK_CKO2_SEL 168 +#define IMX5_CLK_CKO2_PODF 169 +#define IMX5_CLK_CKO2 170 +#define IMX5_CLK_SRTC_GATE 171 +#define IMX5_CLK_PATA_GATE 172 +#define IMX5_CLK_SATA_GATE 173 +#define IMX5_CLK_SPDIF_XTAL_SEL 174 +#define IMX5_CLK_SPDIF0_SEL 175 +#define IMX5_CLK_SPDIF1_SEL 176 +#define IMX5_CLK_SPDIF0_PRED 177 +#define IMX5_CLK_SPDIF0_PODF 178 +#define IMX5_CLK_SPDIF1_PRED 179 +#define IMX5_CLK_SPDIF1_PODF 180 +#define IMX5_CLK_SPDIF0_COM_SEL 181 +#define IMX5_CLK_SPDIF1_COM_SEL 182 +#define IMX5_CLK_SPDIF0_GATE 183 +#define IMX5_CLK_SPDIF1_GATE 184 +#define IMX5_CLK_SPDIF_IPG_GATE 185 +#define IMX5_CLK_OCRAM 186 +#define IMX5_CLK_SAHARA_IPG_GATE 187 +#define IMX5_CLK_SATA_REF 188 +#define IMX5_CLK_STEP_SEL 189 +#define IMX5_CLK_CPU_PODF_SEL 190 +#define IMX5_CLK_ARM 191 +#define IMX5_CLK_FIRI_PRED 192 +#define IMX5_CLK_FIRI_SEL 193 +#define IMX5_CLK_FIRI_PODF 194 +#define IMX5_CLK_FIRI_SERIAL_GATE 195 +#define IMX5_CLK_FIRI_IPG_GATE 196 +#define IMX5_CLK_CSI0_MCLK1_PRED 197 +#define IMX5_CLK_CSI0_MCLK1_SEL 198 +#define IMX5_CLK_CSI0_MCLK1_PODF 199 +#define IMX5_CLK_CSI0_MCLK1_GATE 200 +#define IMX5_CLK_IEEE1588_PRED 201 +#define IMX5_CLK_IEEE1588_SEL 202 +#define IMX5_CLK_IEEE1588_PODF 203 +#define IMX5_CLK_IEEE1588_GATE 204 +#define IMX5_CLK_END 205 + +#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ -- 2.10.1

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[U-Boot] [PATCH 0/2] ARM: imx6ul: Support liteSOM and liteBoard
by Marcin Niestroj 16 Dec '16

16 Dec '16

Hi, These patches add support for liteSOM (http://grinn-global.com/litesom/), and liteBoard (which uses liteSOM as it's base). liteSOM consists of processor (NXP i.MX6UL), RAM memory (up to 512M DDR3) and flash (eMMC card). The idea is that every board vendor can use liteSOM as it's base for designed board. Hence, we need a way to reuse common code between those board. liteBoard is a development kit (and reference platform for liteSOM), that mainly shows possibilities and use cases of liteSOM. Patches were developed and tested on 2016.09. Marcin Niestroj (2): ARM: imx6ul: Add support for liteSOM board/liteboard: Add support for liteBoard arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/cpu/armv7/mx6/Kconfig | 5 + arch/arm/mach-litesom/Kconfig | 6 + arch/arm/mach-litesom/Makefile | 6 + arch/arm/mach-litesom/include/mach/litesom.h | 16 ++ arch/arm/mach-litesom/litesom.c | 200 ++++++++++++++++++++ board/grinn/liteboard/Kconfig | 12 ++ board/grinn/liteboard/MAINTAINERS | 6 + board/grinn/liteboard/Makefile | 6 + board/grinn/liteboard/README | 31 +++ board/grinn/liteboard/board.c | 270 +++++++++++++++++++++++++++ configs/liteboard_defconfig | 22 +++ include/configs/liteboard.h | 174 +++++++++++++++++ 14 files changed, 757 insertions(+) create mode 100644 arch/arm/mach-litesom/Kconfig create mode 100644 arch/arm/mach-litesom/Makefile create mode 100644 arch/arm/mach-litesom/include/mach/litesom.h create mode 100644 arch/arm/mach-litesom/litesom.c create mode 100644 board/grinn/liteboard/Kconfig create mode 100644 board/grinn/liteboard/MAINTAINERS create mode 100644 board/grinn/liteboard/Makefile create mode 100644 board/grinn/liteboard/README create mode 100644 board/grinn/liteboard/board.c create mode 100644 configs/liteboard_defconfig create mode 100644 include/configs/liteboard.h -- 2.9.3

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[U-Boot] [PATCH 0/2] arm: imx: add boards apalis imx6, colibri imx6
by Max Krummenacher 16 Dec '16

16 Dec '16

This series adds support for the Toradex Apalis iMX6 and Colibri iMX6 computer on modules. Tha Apalis iMX6 requires the following patch currently in the u-boot-imx maintainer tree: http://git.denx.de/?p=u-boot/u-boot-imx.git;a=commit;h=15fde0fc11f93f19f40c… The whole series is also available here: http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Max Krummenacher (2): arm: imx: initial support for apalis imx6 arm: imx: initial support for colibri imx6 arch/arm/cpu/armv7/mx6/Kconfig | 16 + board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg | 48 + board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg | 48 + board/toradex/apalis_imx6/Kconfig | 55 + board/toradex/apalis_imx6/MAINTAINERS | 9 + board/toradex/apalis_imx6/Makefile | 5 + board/toradex/apalis_imx6/apalis_imx6.c | 1292 +++++++++++++++++++++++ board/toradex/apalis_imx6/apalis_imx6q.cfg | 34 + board/toradex/apalis_imx6/clocks.cfg | 42 + board/toradex/apalis_imx6/ddr-setup.cfg | 97 ++ board/toradex/apalis_imx6/do_fuse.c | 98 ++ board/toradex/apalis_imx6/pf0100.c | 228 ++++ board/toradex/apalis_imx6/pf0100.h | 56 + board/toradex/apalis_imx6/pf0100_otp.inc | 191 ++++ board/toradex/colibri_imx6/800mhz_2x64mx16.cfg | 59 ++ board/toradex/colibri_imx6/800mhz_4x64mx16.cfg | 59 ++ board/toradex/colibri_imx6/Kconfig | 44 + board/toradex/colibri_imx6/MAINTAINERS | 8 + board/toradex/colibri_imx6/Makefile | 5 + board/toradex/colibri_imx6/clocks.cfg | 42 + board/toradex/colibri_imx6/colibri_imx6.c | 1130 ++++++++++++++++++++ board/toradex/colibri_imx6/colibri_imx6.cfg | 38 + board/toradex/colibri_imx6/ddr-setup.cfg | 98 ++ board/toradex/colibri_imx6/do_fuse.c | 98 ++ board/toradex/colibri_imx6/pf0100.c | 211 ++++ board/toradex/colibri_imx6/pf0100.h | 56 + board/toradex/colibri_imx6/pf0100_otp.inc | 189 ++++ configs/apalis_imx6_defconfig | 52 + configs/apalis_imx6_nospl_com_defconfig | 42 + configs/apalis_imx6_nospl_it_defconfig | 44 + configs/colibri_imx6_defconfig | 50 + configs/colibri_imx6_nospl_defconfig | 44 + include/configs/apalis_imx6.h | 342 ++++++ include/configs/colibri_imx6.h | 310 ++++++ 34 files changed, 5140 insertions(+) create mode 100644 board/toradex/apalis_imx6/1066mhz_4x128mx16.cfg create mode 100644 board/toradex/apalis_imx6/1066mhz_4x256mx16.cfg create mode 100644 board/toradex/apalis_imx6/Kconfig create mode 100644 board/toradex/apalis_imx6/MAINTAINERS create mode 100644 board/toradex/apalis_imx6/Makefile create mode 100644 board/toradex/apalis_imx6/apalis_imx6.c create mode 100644 board/toradex/apalis_imx6/apalis_imx6q.cfg create mode 100644 board/toradex/apalis_imx6/clocks.cfg create mode 100644 board/toradex/apalis_imx6/ddr-setup.cfg create mode 100644 board/toradex/apalis_imx6/do_fuse.c create mode 100644 board/toradex/apalis_imx6/pf0100.c create mode 100644 board/toradex/apalis_imx6/pf0100.h create mode 100644 board/toradex/apalis_imx6/pf0100_otp.inc create mode 100644 board/toradex/colibri_imx6/800mhz_2x64mx16.cfg create mode 100644 board/toradex/colibri_imx6/800mhz_4x64mx16.cfg create mode 100644 board/toradex/colibri_imx6/Kconfig create mode 100644 board/toradex/colibri_imx6/MAINTAINERS create mode 100644 board/toradex/colibri_imx6/Makefile create mode 100644 board/toradex/colibri_imx6/clocks.cfg create mode 100644 board/toradex/colibri_imx6/colibri_imx6.c create mode 100644 board/toradex/colibri_imx6/colibri_imx6.cfg create mode 100644 board/toradex/colibri_imx6/ddr-setup.cfg create mode 100644 board/toradex/colibri_imx6/do_fuse.c create mode 100644 board/toradex/colibri_imx6/pf0100.c create mode 100644 board/toradex/colibri_imx6/pf0100.h create mode 100644 board/toradex/colibri_imx6/pf0100_otp.inc create mode 100644 configs/apalis_imx6_defconfig create mode 100644 configs/apalis_imx6_nospl_com_defconfig create mode 100644 configs/apalis_imx6_nospl_it_defconfig create mode 100644 configs/colibri_imx6_defconfig create mode 100644 configs/colibri_imx6_nospl_defconfig create mode 100644 include/configs/apalis_imx6.h create mode 100644 include/configs/colibri_imx6.h -- 2.7.4

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[U-Boot] [PATCH v2 0/6] cleanup and enhancements for Colibri VFxx
by Stefan Agner 16 Dec '16

16 Dec '16

From: Stefan Agner <stefan.agner(a)toradex.com> This patchset cleans up the board file, speeds up NAND slightly and enhances the board support with device tree MTD partition support. It also fixes a bug in the new Toradex config block code. Not sure through which tree that should go, especially since patch 1 and 2 touches common code... Tom? -- Stefan Changes in v2: - Rebased ontop of master (after config block support merged) - Add patch which uses proper config to guard g_dnl_bind_fixup - Add patch to fix device tree warning Stefan Agner (6): toradex: fix USB Download gadget fixup callback toradex: allow custom fdt board setup in board file colibri_vf: use device-tree for MTD partitions colibri_vf: cleanup USB clock initialization colibri_vf: use same NAND clock as Linux uses ARM: dts: vf: Fix warning about missing reg property arch/arm/dts/vf.dtsi | 2 ++ board/toradex/apalis_t30/apalis_t30.c | 8 ++++++ board/toradex/colibri_imx7/colibri_imx7.c | 8 ++++++ board/toradex/colibri_pxa270/colibri_pxa270.c | 8 ++++++ board/toradex/colibri_t20/colibri_t20.c | 8 ++++++ board/toradex/colibri_t30/colibri_t30.c | 8 ++++++ board/toradex/colibri_vf/colibri_vf.c | 37 +++++++++++++++++++++++---- board/toradex/common/tdx-common.c | 12 ++++----- board/toradex/common/tdx-common.h | 2 ++ 9 files changed, 81 insertions(+), 12 deletions(-) -- 2.10.2

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