November 2016 - U-Boot

[U-Boot] [PATCH v2] powerpc/t2080: CPU erratum A-007907
by Darwin Dingel 24 Jan '17

24 Jan '17

Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham <chris.packham(a)alliedtelesis.co.nz> Signed-off-by: Darwin Dingel <darwin.dingel(a)alliedtelesis.co.nz> Cc: York Sun <york.sun(a)nxp.com> --- Changes for v2: - Enabled for T4240 and B4860 arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++- arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++ arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/processor.h | 1 + 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3b06ae4..197eb2f 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -329,7 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 puts("Work-around for Erratum A009663 enabled\n"); #endif - +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + puts("Work-around for Erratum A007907 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 53b3729..0e744f0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -775,6 +775,13 @@ int cpu_init_r(void) sync(); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 + flush_dcache(); + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); + sync(); +#endif + #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 /* * A-005812 workaround sets bit 32 of SPR 976 for SoCs running diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e8..c2bf44b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -642,6 +642,7 @@ #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A007907 #else #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -748,6 +749,7 @@ #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_SRIO_LIODN +#define CONFIG_SYS_FSL_ERRATUM_A007907 #else #define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_DSP_CPUS 2 @@ -910,6 +912,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define CONFIG_SYS_FSL_ERRATUM_A006593 #define CONFIG_SYS_FSL_ERRATUM_A007186 #define CONFIG_SYS_FSL_ERRATUM_A006379 +#define CONFIG_SYS_FSL_ERRATUM_A007907 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define CONFIG_SYS_FSL_SFP_VER_3_0 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index fdfca90..6f9b297 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -501,6 +501,7 @@ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */ +#define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */ #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ -- 2.10.1

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[U-Boot] ext4: crash when writing a file
by Sébastien Szymanski 24 Jan '17

24 Jan '17

Hello, I am working on a i.MX6UL based board with a 4GB eMMC partitioned as following: Device Boot Start End Sectors Size Id Type /dev/sdb1 2048 264191 262144 128M 83 Linux /dev/sdb2 264192 4458495 4194304 2G 83 Linux /dev/sdb3 4458496 7634943 3176448 1.5G 83 Linux On the 2nd partition, I write this ext4 filesystem file generated by Buildroot: Filesystem volume name: "ROOTFS" Last mounted on: <not available> Filesystem UUID: b9833a36-e89d-429a-b120-c3b00bcb7785 Filesystem magic number: 0xEF53 Filesystem revision #: 1 (dynamic) Filesystem features: has_journal dir_index filetype extent sparse_super uninit_bg Filesystem flags: signed_directory_hash Default mount options: (none) Filesystem state: clean Errors behavior: Unknown (continue) Filesystem OS type: Linux Inode count: 3456 Block count: 91756 Reserved block count: 4587 Free blocks: 13458 Free inodes: 488 First block: 1 Block size: 1024 Fragment size: 1024 Blocks per group: 7648 Fragments per group: 7648 Inodes per group: 288 Inode blocks per group: 36 Last mount time: n/a Last write time: Tue Nov 29 09:44:52 2016 Mount count: 0 Maximum mount count: -1 Last checked: Tue Nov 29 09:44:52 2016 Check interval: 0 (<none>) Reserved blocks uid: 0 (user root) Reserved blocks gid: 0 (group root) First inode: 11 Inode size: 128 Journal inode: 8 Default directory hash: half_md4 Directory Hash Seed: a583a07f-6b59-442d-8e08-9be305f78d17 Journal backup: inode blocks This filesystem is written with the following commands: BIOS> setexpr nbblocks ${filesize} / 0x200 BIOS> setexpr nbblocks ${nbblocks} + 1 BIOS> mmc write ${loadaddr} 0x40800 ${nbblocks} MMC write: dev # 0, block # 264192, count 183513 ... 183513 blocks written: OK I can boot Linux with it without any issues, however if I try to write a file in it I get the following crash: BIOS> ext4write mmc 0:2 ${loadaddr} /boot/${kernelimg} ${filesize} File System is consistent file found, deleting update journal finished File System is consistent update journal finished data abort pc : [<8ff783ac>] lr : [<8ff86c95>] reloc pc : [<8780e3ac>] lr : [<8781cc95>] sp : 8ef696b8 ip : 00000000 fp : 8ffbc6d8 r10: 00000200 r9 : 8ef69ee8 r8 : 8ffbc744 r7 : 8ef9f600 r6 : 8ef999b6 r5 : 00000003 r4 : 8ffa35fc r3 : 8ef999b8 r2 : 00000001 r1 : fffffffe r0 : 8ef999c0 Flags: NzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... I have investigated a bit and I found that the crash is in the ext4fs_deinit() function provoked by the free() call at line 722 (fs/ext4/ext4_write.c) and the ext4fs_deinit() is called in ext4fs_write() at line 980. If I resize the filesystem under Linux, I don't get the crash but the following error: ext4fs_devread read outside partition 4294967294 error in File System init ** Error ext4fs_write() ** ** Unable to write file /boot/opos6ul-linux.bin ** Any idea ? Regards, -- Sébastien Szymanski Software Engineer, Armadeus Systems sebastien.szymanski(a)armadeus.com Tel: +33 (0)9 72 29 41 44 Fax: +33 (0)9 72 28 79 26

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[U-Boot] [PATCH v6 00/13] binman: A tool for creating firmware images
by Simon Glass 21 Jan '17

21 Jan '17

This series introduces binman, a tool designed to create firmware images. It provides a way to bring together various binaries and place them in an image, at particular positions and with configurable alignment. Packaging of firmware is quite a different task from building the various parts. In many cases the various binaries which go into the image come from separate build systems. For example, ARM Trusted Firmware is used on ARMv8 devices but is not built in the U-Boot tree. If a Linux kernel is included in the firmware image, it is built elsewhere. It is of course possible to add more and more build rules to the U-Boot build system to cover these cases. It can shell out to other Makefiles and build scripts. But it seems better to create a clear divide between building software and packaging it. U-Boot supports a very large number of boards. Many of these have their own specific rules for how an image should be put together so that it boots correctly. At present these rules are described by manual instructions, different for each board. By turning these instructions into a standard format, we can support making valid images for any board without manual effort, lots of READMEs, etc. Images consist of a number of entries which are combined to make up the final image. The image is described in the device tree for the board, meaning that it can be accessed at run-time if desired. Binman is an extensible tool. A set of standard entries is provides, but new entries can be created fairly easily. Entries can be as simple as providing the name of a file to include. They can also handle more complex requirements, such as adjusting the input file or reading header information from one entry to control the position of another. U-Boot's mkimage builds FIT images and various other binaries. Binman augments this by allowing these binaries to be packed together. While FIT should be used where possible, it cannot be used everywhere. For example, many devices require executable code at a particular offset in the image. X86 machines require lots of binary blobs at particular places, and a microcode collection easily accessible at boot. So far binman has enough functionality to be useful, so sunxi and x86 boards are switched over to use it, as examples. The series is available at u-boot-dm/binman-working Future work and missing features are documented in the README. Changes in v6: - Deal with optional microcode in SPL - Drop unwanted root-node properties from tegra20-u-boot.dtsi - Use __import__() when importlib is not available Changes in v5: - Add a Makefile 'warning' line for debugging - Add a dependency on u-boot.dtb for buildman - Add a new for optional microcode - Add a new patch to drop microcode features from ifdtool - Add a new tegra patch to use an automatically included .dtsi file - Add documentation for the 'optional-ucode' property - Add documentation for this feature - Add instructions on how to generate html code coverage - Add missing 'descriptor.bin' file - Allow microcode to be optional - Allow the compiled device tree to be returned from _DoReadFileDtb() - Change the Makefile variable from binman_... to u_boot_... - Print 'binman' before all errors - Put the code to calculate dtb total length in a function - Remove commented-out PYTHONPATH code which is not needed now Changes in v4: - Add an option to bring in an soc .dtsi file also - Add new patch to support building x86 images with FSP/CMC - Fix incorrect comments at the top of intel_*.py - Remove RFC tag - Use binman for all sunxi boards - Use binman for all x86 boards Changes in v3: - Add a new patch to automatically include a U-Boot .dtsi file - Put the binman definition in u-boot.dtsi - Use a <dts>-u-boot.dtsi file for the binman changes Changes in v2: - Add automated test coverage - Add test for code coverage - Fix the -b option - Put the binman definition in a common file for x86 - Various changes and improvements based on using this tool for a while - drop the unused __len__() method Simon Glass (13): binman: Introduce binman, a tool for building binary images binman: Add basic entry types for U-Boot binman: Add support for building x86 ROMs binman: Add support for u-boot.img as an input binary binman: Add support for building x86 ROMs with SPL binman: Add support for building x86 images with FSP/CMC binman: Add a build rule for binman binman: Allow configuration options to be used in .dts files binman: Automatically include a U-Boot .dtsi file tegra: Use a U-Boot-specific .dtsi file sunxi: Use binman for sunxi boards x86: Use binman all x86 boards binman: Drop microcode features from ifdtool Makefile | 57 +- arch/arm/dts/sunxi-u-boot.dtsi | 14 + arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 15 + arch/arm/dts/tegra124-nyan-big.dts | 2 - arch/arm/dts/tegra20-u-boot.dtsi | 8 + arch/arm/dts/tegra20.dtsi | 2 - arch/x86/dts/emulation-u-boot.dtsi | 18 + arch/x86/dts/u-boot.dtsi | 62 ++ scripts/Makefile.lib | 25 +- tools/binman/.gitignore | 1 + tools/binman/README | 541 ++++++++++++++ tools/binman/binman | 1 + tools/binman/binman.py | 114 +++ tools/binman/cmdline.py | 53 ++ tools/binman/control.py | 118 +++ tools/binman/entry_test.py | 27 + tools/binman/etype/_testing.py | 26 + tools/binman/etype/blob.py | 37 + tools/binman/etype/entry.py | 200 +++++ tools/binman/etype/intel_cmc.py | 17 + tools/binman/etype/intel_descriptor.py | 55 ++ tools/binman/etype/intel_fsp.py | 17 + tools/binman/etype/intel_me.py | 17 + tools/binman/etype/intel_mrc.py | 17 + tools/binman/etype/intel_vga.py | 17 + tools/binman/etype/u_boot.py | 17 + tools/binman/etype/u_boot_dtb.py | 17 + tools/binman/etype/u_boot_dtb_with_ucode.py | 78 ++ tools/binman/etype/u_boot_img.py | 17 + tools/binman/etype/u_boot_nodtb.py | 17 + tools/binman/etype/u_boot_spl.py | 17 + tools/binman/etype/u_boot_spl_bss_pad.py | 26 + tools/binman/etype/u_boot_spl_with_ucode_ptr.py | 28 + tools/binman/etype/u_boot_ucode.py | 84 +++ tools/binman/etype/u_boot_with_ucode_ptr.py | 87 +++ tools/binman/etype/x86_start16.py | 17 + tools/binman/etype/x86_start16_spl.py | 17 + tools/binman/fdt_test.py | 48 ++ tools/binman/func_test.py | 822 +++++++++++++++++++++ tools/binman/image.py | 229 ++++++ tools/binman/test/01_invalid.dts | 5 + tools/binman/test/02_missing_node.dts | 6 + tools/binman/test/03_empty.dts | 9 + tools/binman/test/04_invalid_entry.dts | 11 + tools/binman/test/05_simple.dts | 11 + tools/binman/test/06_dual_image.dts | 22 + tools/binman/test/07_bad_align.dts | 12 + tools/binman/test/08_pack.dts | 30 + tools/binman/test/09_pack_extra.dts | 35 + tools/binman/test/10_pack_align_power2.dts | 12 + tools/binman/test/11_pack_align_size_power2.dts | 12 + tools/binman/test/12_pack_inv_align.dts | 13 + tools/binman/test/13_pack_inv_size_align.dts | 13 + tools/binman/test/14_pack_overlap.dts | 16 + tools/binman/test/15_pack_overflow.dts | 12 + tools/binman/test/16_pack_image_overflow.dts | 13 + tools/binman/test/17_pack_image_size.dts | 13 + tools/binman/test/18_pack_image_align.dts | 13 + tools/binman/test/19_pack_inv_image_align.dts | 14 + .../binman/test/20_pack_inv_image_align_power2.dts | 13 + tools/binman/test/21_image_pad.dts | 16 + tools/binman/test/22_image_name.dts | 21 + tools/binman/test/23_blob.dts | 12 + tools/binman/test/24_sorted.dts | 17 + tools/binman/test/25_pack_zero_size.dts | 15 + tools/binman/test/26_pack_u_boot_dtb.dts | 14 + tools/binman/test/27_pack_4gb_no_size.dts | 18 + tools/binman/test/28_pack_4gb_outside.dts | 19 + tools/binman/test/29_x86-rom.dts | 19 + tools/binman/test/30_x86-rom-me-no-desc.dts | 15 + tools/binman/test/31_x86-rom-me.dts | 18 + tools/binman/test/32_intel-vga.dts | 13 + tools/binman/test/33_x86-start16.dts | 13 + tools/binman/test/34_x86_ucode.dts | 29 + tools/binman/test/35_x86_single_ucode.dts | 26 + tools/binman/test/36_u_boot_img.dts | 11 + tools/binman/test/37_x86_no_ucode.dts | 20 + tools/binman/test/38_x86_ucode_missing_node.dts | 26 + tools/binman/test/39_x86_ucode_missing_node2.dts | 23 + tools/binman/test/40_x86_ucode_not_in_image.dts | 28 + tools/binman/test/41_unknown_pos_size.dts | 11 + tools/binman/test/42_intel-fsp.dts | 13 + tools/binman/test/43_intel-cmc.dts | 13 + tools/binman/test/44_x86_optional_ucode.dts | 30 + tools/binman/test/descriptor.bin | Bin 0 -> 4096 bytes tools/binman/test/u_boot_no_ucode_ptr | Bin 0 -> 4182 bytes tools/binman/test/u_boot_no_ucode_ptr.c | 15 + tools/binman/test/u_boot_ucode_ptr | Bin 0 -> 4175 bytes tools/binman/test/u_boot_ucode_ptr.c | 15 + tools/binman/test/u_boot_ucode_ptr.lds | 18 + tools/ifdtool.c | 254 +------ 91 files changed, 3709 insertions(+), 300 deletions(-) create mode 100644 arch/arm/dts/sunxi-u-boot.dtsi create mode 100644 arch/arm/dts/tegra124-nyan-big-u-boot.dtsi create mode 100644 arch/arm/dts/tegra20-u-boot.dtsi create mode 100644 arch/x86/dts/emulation-u-boot.dtsi create mode 100644 arch/x86/dts/u-boot.dtsi create mode 100644 tools/binman/.gitignore create mode 100644 tools/binman/README create mode 120000 tools/binman/binman create mode 100755 tools/binman/binman.py create mode 100644 tools/binman/cmdline.py create mode 100644 tools/binman/control.py create mode 100644 tools/binman/entry_test.py create mode 100644 tools/binman/etype/_testing.py create mode 100644 tools/binman/etype/blob.py create mode 100644 tools/binman/etype/entry.py create mode 100644 tools/binman/etype/intel_cmc.py create mode 100644 tools/binman/etype/intel_descriptor.py create mode 100644 tools/binman/etype/intel_fsp.py create mode 100644 tools/binman/etype/intel_me.py create mode 100644 tools/binman/etype/intel_mrc.py create mode 100644 tools/binman/etype/intel_vga.py create mode 100644 tools/binman/etype/u_boot.py create mode 100644 tools/binman/etype/u_boot_dtb.py create mode 100644 tools/binman/etype/u_boot_dtb_with_ucode.py create mode 100644 tools/binman/etype/u_boot_img.py create mode 100644 tools/binman/etype/u_boot_nodtb.py create mode 100644 tools/binman/etype/u_boot_spl.py create mode 100644 tools/binman/etype/u_boot_spl_bss_pad.py create mode 100644 tools/binman/etype/u_boot_spl_with_ucode_ptr.py create mode 100644 tools/binman/etype/u_boot_ucode.py create mode 100644 tools/binman/etype/u_boot_with_ucode_ptr.py create mode 100644 tools/binman/etype/x86_start16.py create mode 100644 tools/binman/etype/x86_start16_spl.py create mode 100644 tools/binman/fdt_test.py create mode 100644 tools/binman/func_test.py create mode 100644 tools/binman/image.py create mode 100644 tools/binman/test/01_invalid.dts create mode 100644 tools/binman/test/02_missing_node.dts create mode 100644 tools/binman/test/03_empty.dts create mode 100644 tools/binman/test/04_invalid_entry.dts create mode 100644 tools/binman/test/05_simple.dts create mode 100644 tools/binman/test/06_dual_image.dts create mode 100644 tools/binman/test/07_bad_align.dts create mode 100644 tools/binman/test/08_pack.dts create mode 100644 tools/binman/test/09_pack_extra.dts create mode 100644 tools/binman/test/10_pack_align_power2.dts create mode 100644 tools/binman/test/11_pack_align_size_power2.dts create mode 100644 tools/binman/test/12_pack_inv_align.dts create mode 100644 tools/binman/test/13_pack_inv_size_align.dts create mode 100644 tools/binman/test/14_pack_overlap.dts create mode 100644 tools/binman/test/15_pack_overflow.dts create mode 100644 tools/binman/test/16_pack_image_overflow.dts create mode 100644 tools/binman/test/17_pack_image_size.dts create mode 100644 tools/binman/test/18_pack_image_align.dts create mode 100644 tools/binman/test/19_pack_inv_image_align.dts create mode 100644 tools/binman/test/20_pack_inv_image_align_power2.dts create mode 100644 tools/binman/test/21_image_pad.dts create mode 100644 tools/binman/test/22_image_name.dts create mode 100644 tools/binman/test/23_blob.dts create mode 100644 tools/binman/test/24_sorted.dts create mode 100644 tools/binman/test/25_pack_zero_size.dts create mode 100644 tools/binman/test/26_pack_u_boot_dtb.dts create mode 100644 tools/binman/test/27_pack_4gb_no_size.dts create mode 100644 tools/binman/test/28_pack_4gb_outside.dts create mode 100644 tools/binman/test/29_x86-rom.dts create mode 100644 tools/binman/test/30_x86-rom-me-no-desc.dts create mode 100644 tools/binman/test/31_x86-rom-me.dts create mode 100644 tools/binman/test/32_intel-vga.dts create mode 100644 tools/binman/test/33_x86-start16.dts create mode 100644 tools/binman/test/34_x86_ucode.dts create mode 100644 tools/binman/test/35_x86_single_ucode.dts create mode 100644 tools/binman/test/36_u_boot_img.dts create mode 100644 tools/binman/test/37_x86_no_ucode.dts create mode 100644 tools/binman/test/38_x86_ucode_missing_node.dts create mode 100644 tools/binman/test/39_x86_ucode_missing_node2.dts create mode 100644 tools/binman/test/40_x86_ucode_not_in_image.dts create mode 100644 tools/binman/test/41_unknown_pos_size.dts create mode 100644 tools/binman/test/42_intel-fsp.dts create mode 100644 tools/binman/test/43_intel-cmc.dts create mode 100644 tools/binman/test/44_x86_optional_ucode.dts create mode 100644 tools/binman/test/descriptor.bin create mode 100755 tools/binman/test/u_boot_no_ucode_ptr create mode 100644 tools/binman/test/u_boot_no_ucode_ptr.c create mode 100755 tools/binman/test/u_boot_ucode_ptr create mode 100644 tools/binman/test/u_boot_ucode_ptr.c create mode 100644 tools/binman/test/u_boot_ucode_ptr.lds -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH] armv8/layerscape: remove unnecessary function declares
by Minghuan Lian 19 Jan '17

19 Jan '17

For the function alloc_stream_ids() append_mmu_masters() and fdt_fixup_smmu_pcie() there are no related definitions and they are never called. So the patch removes the unnecessary declares. Signed-off-by: Minghuan Lian <Minghuan.Lian(a)nxp.com> --- arch/arm/include/asm/arch-fsl-layerscape/fdt.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h index 099563e..537486d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h @@ -7,9 +7,5 @@ #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ #define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ -void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt); -void append_mmu_masters(void *blob, const char *smmu_path, - const char *master_name, u32 *stream_ids, int count); -void fdt_fixup_smmu_pcie(void *blob); void fdt_fixup_board_enet(void *fdt); #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */ -- 1.9.1

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[U-Boot] [PATCH] armv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20
by Priyanka Jain 19 Jan '17

19 Jan '17

It is recommended to set forced-order mode in RNI-6, RNI-20 for performance optimization in LS2088A. Both LS2080A, LS2088A families has CONFIG_LS2080A define. As above update is required only for LS2088A, skip this for LS2080A SoC family Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index d7440ac..7d741b8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -28,6 +28,26 @@ ENTRY(lowlevel_init) ldr x0, =CCI_AUX_CONTROL_BASE(20) ldr x1, =0x00000010 bl ccn504_set_aux + + /* + * Set forced-order mode in RNI-6, RNI-20 + * This is required for performance optimization on LS2088A + * LS2080A family does not support setting forced-order mode, + * so skip this operation for LS2080A family + */ + bl get_svr + lsr w0, w0, #16 + ldr w1, =SVR_DEV_LS2080A + cmp w0, w1 + b.eq 1f + + ldr x0, =CCI_AUX_CONTROL_BASE(6) + ldr x1, =0x00000020 + bl ccn504_set_aux + ldr x0, =CCI_AUX_CONTROL_BASE(20) + ldr x1, =0x00000020 + bl ccn504_set_aux +1: #endif /* Add fully-coherent masters to DVM domain */ -- 1.7.4.1

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[U-Boot] [PATCH] fsl/usb: enable usb feature for ls1046ardb
by jerry.huang＠nxp.com 19 Jan '17

19 Jan '17

Enable usb feature for ls1046ardb Signed-off-by: Changming Huang <jerry.huang(a)nxp.com> --- include/configs/ls1046ardb.h | 12 ++++++++++++ include/linux/usb/xhci-fsl.h | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 2fe8fc1..f0719ad 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -211,6 +211,18 @@ #define CONFIG_SPI_FLASH_BAR #endif +/* USB */ +#define CONFIG_HAS_FSL_XHCI_USB +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_HCD +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 15cac40..1fa3161 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -62,7 +62,7 @@ struct fsl_xhci { #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS1043A) +#elif defined(CONFIG_LS1043A) || defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR -- 1.7.9.5

2 1

[U-Boot] [PATCH v3 0/9] ARM: stm32: add network and qspi driver support to stm32f746-disco board
by Michael Kurz 18 Jan '17

18 Jan '17

This series adds support for the network and the qspi devices found on the stm32f746 controller and enables those devices on the stm32f746-disco board. Changes in v3: - Split pin control files of from device tree patch - Add Acked-by tag to 'add stm32f746 device tree pin control files' - Split pin control files of from device tree patch - Add Acked-by tag to 'add stm32f746-disco device tree files' - Removed 'prefix all constants with STM32_' - Reverted move of header into source file (rcc.h -> clock.c) - Split clock setup changes of from cleanup patch - Add Acked-by tag to 'add designware mac glue code for stm32' - Moved qspi rcc bits into rcc header - Drop 'add missing flag to micron/stm N25Q128 flash chips' patch Changes in v2: - Add cleanup patch - Replaced bit shifts and masks with BIT() and GENMASK() macro - Moved STM32_SYSCFG_BASE into stm32.h header - Add Acked-by tag to 'net: phy: add SMSC LAN8742 phy' - Replaced bit shifts and masks with BIT() and GENMASK() macro Michael Kurz (9): ARM: DTS: stm32: add stm32f746 device tree pin control files ARM: DTS: stm32: add stm32f746-disco device tree files ARM: stm32: cleanup stm32f7 files ARM: stm32: fix stm32f7 sdram fmc base address ARM: stm32: use clock setup function defined in clock.c net: stm32: add designware mac glue code for stm32 net: phy: add SMSC LAN8742 phy ARM: stm32: enable support for smsc phy on stm32f746-disco board ARM: SPI: stm32: add stm32f746 qspi driver arch/arm/dts/Makefile | 2 + arch/arm/dts/armv7-m.dtsi | 24 + arch/arm/dts/stm32f746-disco.dts | 154 +++ arch/arm/dts/stm32f746.dtsi | 397 +++++++ arch/arm/include/asm/arch-stm32f7/fmc.h | 9 +- arch/arm/include/asm/arch-stm32f7/gpt.h | 6 +- arch/arm/include/asm/arch-stm32f7/rcc.h | 77 +- arch/arm/include/asm/arch-stm32f7/stm32.h | 10 +- arch/arm/include/asm/arch-stm32f7/stm32_periph.h | 10 +- arch/arm/include/asm/arch-stm32f7/syscfg.h | 38 + arch/arm/mach-stm32/stm32f7/clock.c | 171 ++- arch/arm/mach-stm32/stm32f7/timer.c | 4 +- board/st/stm32f746-disco/stm32f746-disco.c | 124 +- configs/stm32f746-disco_defconfig | 23 +- drivers/net/designware.c | 1 + drivers/net/phy/smsc.c | 12 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/stm32_qspi.c | 628 ++++++++++ include/configs/stm32f746-disco.h | 10 +- include/dt-bindings/pinctrl/stm32f746-pinfunc.h | 1324 ++++++++++++++++++++++ 21 files changed, 2872 insertions(+), 161 deletions(-) create mode 100644 arch/arm/dts/armv7-m.dtsi create mode 100644 arch/arm/dts/stm32f746-disco.dts create mode 100644 arch/arm/dts/stm32f746.dtsi create mode 100644 arch/arm/include/asm/arch-stm32f7/syscfg.h create mode 100644 drivers/spi/stm32_qspi.c create mode 100644 include/dt-bindings/pinctrl/stm32f746-pinfunc.h -- 2.1.4

5 36

[U-Boot] [PATCH] video: cfb_console: fix hang if splashimage file is missing
by Anatolij Gustschin 13 Jan '17

13 Jan '17

If the splash file doesn't exist, the booting stops bricking the boards. Check return value of prepare function and stop decoding the logo data if splash prepare stage failed. Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- drivers/video/cfb_console.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index c0b1b8d..a4cbc44 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1861,14 +1861,16 @@ static void *video_logo(void) __maybe_unused int y_off = 0; __maybe_unused ulong addr; __maybe_unused char *s; - __maybe_unused int len, space; + __maybe_unused int len, ret, space; splash_get_pos(&video_logo_xpos, &video_logo_ypos); #ifdef CONFIG_SPLASH_SCREEN s = getenv("splashimage"); if (s != NULL) { - splash_screen_prepare(); + ret = splash_screen_prepare(); + if (ret < 0) + return video_fb_address; addr = simple_strtoul(s, NULL, 16); if (video_display_bitmap(addr, -- 2.7.4

1 1

[U-Boot] [PATCH v8 0/3] armv8: Support loading 32-bit OS in AArch32 execution state
by Alison Wang 12 Jan '17

12 Jan '17

This series is to support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. PSCI method can also be used for secondary cores to load 32-bit OS. As PSCI and secure monitor firmware framework are enabled, loading 32-bit OS is supported in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. --------------------------------------- Changes in v8: - Fix the issue when U-Boot is running in EL2 or EL1. - Support loading 32-bit OS with PSCI enabled. Changes in v7: - Move the call for armv8_switch_to_el2_m into the first patch. Changes in v6: - Modified armv8_switch_to_el1(). It will always jump to ep when switching to AArch64 or AArch32 modes. - Make other platforms compatible with the new armv8_switch_to_el2() and armv8_switch_to_el1(). - Make secondary_switch_to_el1() always jump to ep when switching to AArch64 or AArch32 modes. Changes in v5: - Modified armv8_switch_to_el2(). It will always jump to ep when switching to AArch64 or AArch32 modes. - Make secondary_switch_to_el2() always jump to ep when switching to AArch64 or AArch32 modes. Changes in v4: - Correct config ARM64_SUPPORT_AARCH32. - Omit arch and ftaddr arguments. - Rename "xreg5" to "tmp". - Use xxx_RES1 to combine all RES1 fields in xxx register. - Use an immediate cmp directly. - Use #ifdef for CONFIG_ARM64_SUPPORT_AARCH32. Changes in v3: - Comments the functions and the arguments. - Rename the real parameters. - Use the macros instead of the magic values. - Remove the redundant codes. - Clean up all of the mess in boot_jump_linux(). - Add CONFIG_ARM64_SUPPORT_AARCH32 to detect for some ARM64 system doesn't support AArch32 state. - Adjust the arguments for armv8_switch_to_el2_m and armv8_switch_to_el1_m. Changes in v2: - armv8_switch_to_el2_aarch32() is removed. armv8_switch_to_el2_m is used to switch to AArch64 EL2 or AArch32 Hyp. - armv8_switch_to_el1_aarch32() is removed. armv8_switch_to_el1_m is used to switch to AArch64 EL1 or AArch32 SVC. - Support to call armv8_switch_to_el2_m and armv8_switch_to_el1_m. ---------------------------------------------------------------- Alison Wang (3): armv8: Support loading 32-bit OS in AArch32 execution state armv8: fsl-layerscape: SMP support for loading 32-bit OS armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabled arch/arm/Kconfig | 6 ++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 61 +++++++++++++++++++++++++------ arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 ++++++ arch/arm/cpu/armv8/sec_firmware_asm.S | 23 ++++++++++++ arch/arm/cpu/armv8/start.S | 8 +++++ arch/arm/cpu/armv8/transition.S | 35 ++++++++++++++---- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++++ arch/arm/include/asm/macro.h | 176 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++---------------------- arch/arm/include/asm/system.h | 121 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- arch/arm/lib/bootm.c | 45 ++++++++++++++++++++--- arch/arm/mach-rmobile/lowlevel_init_gen3.S | 9 ++++- common/image-fit.c | 19 +++++++++- 12 files changed, 451 insertions(+), 68 deletions(-)

5 20

[U-Boot] [PATCH] mx6sx: Add initial support for UDOO Neo Board
by Breno Lima 10 Jan '17

10 Jan '17

UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte(a)gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed57496… Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima(a)nxp.com> --- arch/arm/cpu/armv7/mx6/Kconfig | 5 + board/udoo/neo/Kconfig | 12 ++ board/udoo/neo/MAINTAINERS | 7 + board/udoo/neo/Makefile | 6 + board/udoo/neo/neo.c | 441 +++++++++++++++++++++++++++++++++++++++++ configs/udoo_neo_defconfig | 30 +++ include/configs/udoo_neo.h | 94 +++++++++ 7 files changed, 595 insertions(+) create mode 100644 board/udoo/neo/Kconfig create mode 100644 board/udoo/neo/MAINTAINERS create mode 100644 board/udoo/neo/Makefile create mode 100644 board/udoo/neo/neo.c create mode 100644 configs/udoo_neo_defconfig create mode 100644 include/configs/udoo_neo.h diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 762a581..ea8b693 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -192,6 +192,10 @@ config TARGET_UDOO bool "udoo" select SUPPORT_SPL +config TARGET_UDOO_NEO + bool "UDOO Neo" + select SUPPORT_SPL + config TARGET_WANDBOARD bool "wandboard" select SUPPORT_SPL @@ -253,6 +257,7 @@ source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/udoo/Kconfig" +source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig new file mode 100644 index 0000000..8f474df --- /dev/null +++ b/board/udoo/neo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_UDOO_NEO + +config SYS_VENDOR + default "udoo" + +config SYS_BOARD + default "neo" + +config SYS_CONFIG_NAME + default "udoo_neo" + +endif diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS new file mode 100644 index 0000000..743fe33 --- /dev/null +++ b/board/udoo/neo/MAINTAINERS @@ -0,0 +1,7 @@ +UDOO NEO BOARD +M: Breno Lima <breno.lima(a)nxp.com> +M: Francesco Montefoschi <francesco.montefoschi(a)udoo.org> +S: Maintained +F: board/udoo/neo/ +F: include/configs/udoo_neo.h +F: configs/udoo_neo_defconfig diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile new file mode 100644 index 0000000..150cbc1 --- /dev/null +++ b/board/udoo/neo/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 UDOO Team +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := neo.o diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c new file mode 100644 index 0000000..7f17469 --- /dev/null +++ b/board/udoo/neo/neo.c @@ -0,0 +1,441 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright (C) Jasbir Matharu + * Copyright (C) UDOO Team + * + * Author: Breno Lima <breno.lima(a)nxp.com> + * Author: Francesco Montefoschi <francesco.monte(a)gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> +#include <linux/sizes.h> +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + UDOO_NEO_TYPE_BASIC, + UDOO_NEO_TYPE_BASIC_KS, + UDOO_NEO_TYPE_FULL, + UDOO_NEO_TYPE_EXTENDED, +}; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) +#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ + MUX_MODE_SION) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD pin */ + MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Power */ + MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const board_recognition_pads[] = { + /*Connected to R184*/ + MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, + /*Connected to R185*/ + MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + /* Configured for WLAN */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_b_pad = { + MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const peri_3v3_pads[] = { + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + */ + imx_iomux_v3_setup_pad(wdog_b_pad); + + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ + imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, + ARRAY_SIZE(peri_3v3_pads)); + + /* Active high for ncp692 */ + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + + return 0; +} + +static int get_board_value(void) +{ + int r184, r185; + + imx_iomux_v3_setup_multiple_pads(board_recognition_pads, + ARRAY_SIZE(board_recognition_pads)); + + gpio_direction_input(IMX_GPIO_NR(4, 13)); + gpio_direction_input(IMX_GPIO_NR(4, 0)); + + r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); + r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); + + /* + * Machine selection - + * Machine r184, r185 + * --------------------------------- + * Basic 0 0 + * Basic Ks 0 1 + * Full 1 0 + * Extended 1 1 + */ + + return (r184 << 1) + r185; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) +#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers\ + (%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning:\ + failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +#else + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} + +char *board_string(void) +{ + switch (get_board_value()) { + case UDOO_NEO_TYPE_BASIC: + return "BASIC"; + case UDOO_NEO_TYPE_BASIC_KS: + return "BASICKS"; + case UDOO_NEO_TYPE_FULL: + return "FULL"; + case UDOO_NEO_TYPE_EXTENDED: + return "EXTENDED"; + } + return "UNDEFINED"; +} + +int checkboard(void) +{ + printf("Board: UDOO Neo %s\n", board_string()); + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", board_string()); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +#include <libfdt.h> +#include <asm/arch/mx6-ddr.h> + +static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000020, + .dram_cas = 0x00000020, + .dram_odt0 = 0x00000020, + .dram_odt1 = 0x00000020, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000020, +}; + +static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000020, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ctlds = 0x00000020, + .grp_ddr_type = 0x000c0000, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, +}; + +static const struct mx6_mmdc_calibration neo_mmcd_calib = { + .p0_mpwldectrl0 = 0x000E000B, + .p0_mpwldectrl1 = 0x000E0010, + .p0_mpdgctrl0 = 0x41600158, + .p0_mpdgctrl1 = 0x01500140, + .p0_mprddlctl = 0x3A383E3E, + .p0_mpwrdlctl = 0x3A383C38, +}; + +static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { + .p0_mpwldectrl0 = 0x001E0022, + .p0_mpwldectrl1 = 0x001C0019, + .p0_mpdgctrl0 = 0x41540150, + .p0_mpdgctrl1 = 0x01440138, + .p0_mprddlctl = 0x403E4644, + .p0_mpwrdlctl = 0x3C3A4038, +}; + +/* MT41K256M16 */ +static struct mx6_ddr3_cfg neo_mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* MT41K128M16 */ +static struct mx6_ddr3_cfg neo_basic_mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + int board = get_board_value(); + + struct mx6_ddr_sysinfo sysinfo = { + .dsize = 1, /* width of data bus: 1 = 32 bits */ + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); + if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS) + mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, + &neo_basic_mem_ddr); + else + mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +#endif diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig new file mode 100644 index 0000000..3304afb --- /dev/null +++ b/configs/udoo_neo_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_UDOO_NEO=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_DHCP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h new file mode 100644 index 0000000..81e0481 --- /dev/null +++ b/include/configs/udoo_neo.h @@ -0,0 +1,94 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Copyright Jasbir Matharu + * Copyright 2015 UDOO Team + * + * Configuration settings for the UDOO NEO board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config_distro_defaults.h> +#include "mx6_common.h" + +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_UART + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* Command definition */ +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ + +/* Linux only */ +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4\0" \ + "mmcautodetect=no\0" \ + "findfdt="\ + "if test $board_name = BASIC; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = BASICKS; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = FULL; then " \ + "setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \ + "if test $board_name = EXTENDED; then " \ + "setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \ + "if test $fdt_file = UNDEFINED; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + +#include <config_distro_bootcmd.h> + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC + +#endif /* __CONFIG_H */ -- 2.7.4

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