November 2016 - U-Boot

[U-Boot] [PATCHv4] Retrieve MAC address from EEPROM
by Olliver Schinagl 10 Apr '17

10 Apr '17

This patch-series introduces methods to retrieve the MAC address from an onboard EEPROM. The series does a few small cleanups at the start, as either I ran into them while doing this series and fixed them along the way or actually depended on them. If you want to split the smaller ones off into a smaller series I understand, but again, I do somewhat depend on them. A manufacturer wants to produce boards and may even have MAC addresses for boards. Maintaining unique environments on a per-board basis however is horrible. Also this data should be very persistent, and not easily deletable by simply wiping the environment or device tree. Finally there are chips available on the market with a pre-programmed MAC address chips (proms) that a board manufacturer wants to use. Because of this, the MAC needs to be stored be able to read from such an 'external' source. The current idea of the eeprom layout, is to skip the first 8 bytes, so that other information can be stored there if needed, for example a header with some magic to identify the EEPROM. Or equivalent purposes. After those 8 bytes the MAC address follows the first macaddress. The macaddress is appended by a CRC8 byte and then padded to make for nice 8 bytes. Following the first macaddress one can store a second, or a third etc etc mac address. The CRC8 is optional (via a define) but is strongly recommended to have. It helps preventing user error and more importantly, checks if the bytes read are actually a user inserted address. E.g. only writing 1 macaddress into the eeprom but trying to consume 2. For the added tools, I explicitly did not use the wiser eth_validate_ethaddr_str(), eth_parse_enetaddr() and the ARP_HLEN define as it was quite painful (dependancies) to get these functions into the tools. I would suggest to merge as is, and if someone wants to improve these simple tools to use these functions to happily do so. These patches where tested on Olimex OLinuXino Lime1 (A10/A20), Lime2 (NAND and eMMC) and A20-OLinuXino-MICRO-4G variants and have been in use internally on our production systems since v2 of this patch set. To be able to replicate these tests the second series (which will be separate from this set) are needed. Left TODO: If U-Boot configures eth0 and eth1 it inserts these values into the environment. If the fdt then has an ethernet alias for ethernet0, with a MAC address for a different device, lets say eth2) things will not work at so well. I guess that leaves some discussion with a separated improvement patch as a reliable way is needed to match actual u-boot detected devices, with fdt described devices. E.g. is dev->name the same name to the fdt? Can we blindly match here? ======= Changes since v3: * Split off board specific stuff and only modify the generic functions * Make reading of an eeprom available to every board. By default this is unconfigure and thus should just fall through * Clean some minor bits up (ARP_HLEN) and use it more generically * Update the gen_ethaddr_crc as suggested by simon * Let the fixup_ethernet from fdt_common insert mac addresses to the environment for unconfigured devices. There is a small caveat here however as described in the TODO above. * Print the mac address that u-boot assigned to each device. Changes since v2: * Drop the id byte altogether and just mark it as reserved. The 'index' can be used to indicate the interface instead * Addopt the read_rom_hwaddr hooks * Renamed crc8 tool to gen_ethaddr_crc * Improved the layout EEPROM example * Made a function out of the hwaddress writing function in sunxi_emac so it can be re-used as the write_hwaddr net_ops hook. * No longer handle fdt parameters in board.c Changes since v1: * Do not CRC the id byte, move it just after the crc byte. One of the reasons I decided to move it after the crc8 was mostly due to mass generation of MAC + CRC combo's where the ID is still unknown. Also not crc-ing the ID means that it is much easier for a user to change it (via the u-boot i2c cmd line or from within linux) without having to worry about the crc. * Add a generator to convert a MAC address from the input to a MAC + CRC8 on the output.

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Re: [U-Boot] Loading kernel from SD card slow on MinnowBoard Turbot since v2016.09
by Raschen Josef 09 Apr '17

09 Apr '17

Hi, > From my tests it should be somewhere between these two commits: > 1c62d999528da1f052cb4b07cbb540b148c52537 OK > ceec08f50b66df0c988033842ec057a32658cfe0 NOK I did some more tests and it looks like commit 14bed52d276afd36b9674ee7aa2c2ad9d2f4e59e introduced the issue. From the code I would guess that the max clock of the mmc controller is not set up correctly for the x86/BayTrail platform (minnowmax_defconfig in my case). Thanks, Josef

2 1

[U-Boot] [PATCH v3 1/2] mx6sabresd: Make SPL DDR configuration to match the DCD table
by Fabio Estevam 05 Apr '17

05 Apr '17

From: Fabio Estevam <fabio.estevam(a)nxp.com> When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. This causes stability issues like the ones reported at 7dbda25ecd6d7c ("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also: http://lists.denx.de/pipermail/u-boot/2016-September/266355.html . As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Retrieved the DCD tables from: board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg and board/freescale/mx6sabresd/mx6qp.cfg (NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga) This method makes it easier for people converting from non-SPL to SPL code. Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v1: - Use the correct mx6qp dcd table - Create ddr_init() to write the DCD values - Specify where the DCD tables come from board/freescale/mx6sabresd/mx6sabresd.c | 351 ++++++++++++++++++-------------- 1 file changed, 197 insertions(+), 154 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index f836ecb..3c36395 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -682,125 +682,6 @@ int checkboard(void) #include <spl.h> #include <libfdt.h> -const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = { - .dram_sdclk_0 = 0x00000030, - .dram_sdclk_1 = 0x00000030, - .dram_cas = 0x00000030, - .dram_ras = 0x00000030, - .dram_reset = 0x00000030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_dqm2 = 0x00000030, - .dram_dqm3 = 0x00000030, - .dram_dqm4 = 0x00000030, - .dram_dqm5 = 0x00000030, - .dram_dqm6 = 0x00000030, - .dram_dqm7 = 0x00000030, -}; - -const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { - .grp_ddr_type = 0x000C0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x001F001F, - .p0_mpwldectrl1 = 0x001F001F, - .p1_mpwldectrl0 = 0x00440044, - .p1_mpwldectrl1 = 0x00440044, - .p0_mpdgctrl0 = 0x434B0350, - .p0_mpdgctrl1 = 0x034C0359, - .p1_mpdgctrl0 = 0x434B0350, - .p1_mpdgctrl1 = 0x03650348, - .p0_mprddlctl = 0x4436383B, - .p1_mprddlctl = 0x39393341, - .p0_mpwrdlctl = 0x35373933, - .p1_mpwrdlctl = 0x48254A36, -}; - -const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = { - .p0_mpwldectrl0 = 0x001B001E, - .p0_mpwldectrl1 = 0x002E0029, - .p1_mpwldectrl0 = 0x001B002A, - .p1_mpwldectrl1 = 0x0019002C, - .p0_mpdgctrl0 = 0x43240334, - .p0_mpdgctrl1 = 0x0324031A, - .p1_mpdgctrl0 = 0x43340344, - .p1_mpdgctrl1 = 0x03280276, - .p0_mprddlctl = 0x44383A3E, - .p1_mprddlctl = 0x3C3C3846, - .p0_mpwrdlctl = 0x2E303230, - .p1_mpwrdlctl = 0x38283E34, -}; - -/* MT41K128M16JT-125 */ -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -831,44 +712,209 @@ static void gpr_init(void) } } -/* - * This section requires the differentiation between iMX6 Sabre boards, but - * for now, it will configure only for the mx6q variant. - */ -static void spl_dram_init(void) +static int mx6q_dcd_table[] = { + 0x020e0798, 0x000C0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001F001F, + 0x021b0810, 0x001F001F, + 0x021b480c, 0x001F001F, + 0x021b4810, 0x001F001F, + 0x021b083c, 0x43270338, + 0x021b0840, 0x03200314, + 0x021b483c, 0x431A032F, + 0x021b4840, 0x03200263, + 0x021b0848, 0x4B434748, + 0x021b4848, 0x4445404C, + 0x021b0850, 0x38444542, + 0x021b4850, 0x4935493A, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x09444040, + 0x021b000c, 0x555A7975, + 0x021b0010, 0xFF538F64, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x005A1023, + 0x021b0040, 0x00000027, + 0x021b0000, 0x831A0000, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static int mx6qp_dcd_table[] = { + 0x020e0798, 0x000c0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001b001e, + 0x021b0810, 0x002e0029, + 0x021b480c, 0x001b002a, + 0x021b4810, 0x0019002c, + 0x021b083c, 0x43240334, + 0x021b0840, 0x0324031a, + 0x021b483c, 0x43340344, + 0x021b4840, 0x03280276, + 0x021b0848, 0x44383A3E, + 0x021b4848, 0x3C3C3846, + 0x021b0850, 0x2e303230, + 0x021b4850, 0x38283E34, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08c0, 0x24912249, + 0x021b48c0, 0x24914289, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x24444040, + 0x021b000c, 0x555A7955, + 0x021b0010, 0xFF320F64, + 0x021b0014, 0x01ff00db, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x005A1023, + 0x021b0040, 0x00000027, + 0x021b0400, 0x14420000, + 0x021b0000, 0x831A0000, + 0x021b0890, 0x00400C58, + 0x00bb0008, 0x00000000, + 0x00bb000c, 0x2891E41A, + 0x00bb0038, 0x00000564, + 0x00bb0014, 0x00000040, + 0x00bb0028, 0x00000020, + 0x00bb002c, 0x00000020, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static void ddr_init(int *table, int size) { - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; + int i; - if (is_mx6dqp()) { - mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr); - } else { - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); - } + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + if (is_mx6dq()) + ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); + else if (is_mx6dqp()) + ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); } void board_init_f(ulong dummy) { + /* DDR initialization */ + spl_dram_init(); + /* setup AIPS and disable watchdog */ arch_cpu_init(); @@ -884,9 +930,6 @@ void board_init_f(ulong dummy) /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); - /* DDR initialization */ - spl_dram_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); -- 2.7.4

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[U-Boot] [PATCH 00/10] sunxi: Add basic PSCI support to enable SMP on the A80's first cluster
by Chen-Yu Tsai 03 Apr '17

03 Apr '17

Hi everyone, This series adds basic PSCI support for the A80 to enable SMP on the first cluster. This at least allows people to use more than one core. The term "basic" is used because the series does not add support for multi-cluster cache and power management. The PSCI code is based on existing code for all the single cluster SoCs, and the kernel patches for MCPM SMP I did some time ago. Unfortunately only SMP works at this time. The last patch does not actually work. While the system is indeed booted non-secure, tested by trying to write to secure SRAM and the results not sticking, reads from the GIC CPU interface shows that it's still returning the secure copy of registers, and since we use a secure monitor FIQ to do core power down, the FIQ gets passed to the kernel. The patch is included so people with in-depth ARM knowledge could probably help work out what is wrong. Regards ChenYu Chen-Yu Tsai (10): ARM: PSCI: Set ARMV7_PSCI_NR_CPUS default to 8 for sun9i/A80 sunxi: Add CCI-400 and CPUCFG registers base address for sun9i/A80 sunxi: Add base address of secure SRAM B for sun9i/A80 sunxi: Use secure SRAM B for secure RAM for sun9i/A80 sunxi: Add PRCM register definition for sun9i/A80 sunxi: Add CPUCFG register definitions for sun9i/A80 sunxi: Add support for TZPC on sun9i/A80 sunxi: Add basic PSCI implementation for A80 sunxi: Enable PSCI on sun9i/A80 sunxi: Add PSCI core power off support for A80's first cluster arch/arm/cpu/armv7/Kconfig | 1 + arch/arm/cpu/armv7/sunxi/Makefile | 5 + arch/arm/cpu/armv7/sunxi/psci-mcpm.c | 322 +++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/tzpc.c | 6 + arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 5 + arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h | 51 ++++ arch/arm/include/asm/arch-sunxi/prcm_sun9i.h | 55 +++++ arch/arm/include/asm/arch-sunxi/tzpc.h | 4 + arch/arm/mach-sunxi/board.c | 3 +- board/sunxi/Kconfig | 4 + include/configs/sun9i.h | 4 + 11 files changed, 459 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/sunxi/psci-mcpm.c create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun9i.h create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun9i.h -- 2.10.2

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[U-Boot] [PATCH] ARM: dts: uniphier: move aliases node up to make fdtgrep happy
by Masahiro Yamada 03 Apr '17

03 Apr '17

Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb and uniphier-ph1-ld11-ref.dtb unless the aliases node comes the first in the root node. $ make -s uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref [snip] LDS spl/u-boot-spl.lds LD spl/u-boot-spl OBJCOPY spl/u-boot-spl-nodtb.bin FDTGREP spl/u-boot-spl.dtb Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT /aliases node must come before all other nodes Error: FDT_ERR_BADMAGIC make[1]: *** [spl/u-boot-spl.dtb] Error 1 make: *** [spl/u-boot-spl] Error 2 This commit moves the aliases node as the error message from the fdtgrep tool suggests, although this requirement does not sound reasonable to me. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- Simon, I'd like to avoid this patch if possible. Not figured out the root cause of the problem yet? arch/arm/dts/uniphier-ph1-ld11-ref.dts | 18 +++++++++--------- arch/arm/dts/uniphier-ph1-ld20-ref.dts | 18 +++++++++--------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts index a624a49..88e7f53 100644 --- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts @@ -14,15 +14,6 @@ model = "UniPhier PH1-LD11 Reference Board"; compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11"; - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { serial0 = &serial0; serial1 = &serial1; @@ -35,6 +26,15 @@ i2c4 = &i2c4; i2c5 = &i2c5; }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ethsc { diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts index 108adeb..a55d90c 100644 --- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts @@ -14,15 +14,6 @@ model = "UniPhier PH1-LD20 Reference Board"; compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20"; - memory { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { serial0 = &serial0; serial1 = &serial1; @@ -35,6 +26,15 @@ i2c4 = &i2c4; i2c5 = &i2c5; }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0xc0000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; }; &ethsc { -- 1.9.1

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[U-Boot] [PATCH v2 00/63] x86: Add initial support for 64-bit U-Boot
by Simon Glass 03 Apr '17

03 Apr '17

At present U-Boot runs entirely in 32-bit mode on x86, except for the initial switch from 16-bit mode. On 64-bit machines it is possible to run in 64-bit mode. This series starts the process of adding this support. The main benefit of 64-bit mode for a boot loader is direct access to all available memory. There are also more registers, but this makes very little difference. This feature is implemented by putting all of the 32-bit code in an SPL build. SPL then runs through all the init that has to be done in 32-bit mode, changes to 64-bit mode and then jumps to U-Boot proper. Typically the total code size increases slightly. For example, on link in 32-bit mode, U-Boot has around 480KB of code (admittedly with a large number of features enabled). In 64-bit mode, U-Boot falls to around 460KB, but SPL adds another 60KB, for a net increase of 40KB. Partly this is due to code duplication and partly it is due to the worse code density of 64-bit code on x86. Many major features are not implemented yet, for example: - SDRAM sizing - Booting linux - FSP support - EFI support - SCSI device init - Running video ROMs Still, this is a big step forward towards full 64-bit support. To enable it, select CONFIG_X86_RUN_64BIT. This series is available at u-boot-x86/64-working Changes in v2: - Show the error value in spl_spi_load_image() - Move table-related changes from a later patch - Rebase to mainline - Drop the write_smbios_table_wrapper() function - Drop change to gma.c - Output error code values in debug() statements - Fix cast in bd82x6x_video_probe() also - Fix cast in get_guid_hob_data() also - Move table-related changes to an earlier patch - Add the 'val' parameter to longjmp() - Drop patch 'video: Use ulong for video frame buffer address' - Add a new 64-bit link config instead of changing the existing one Simon Glass (63): console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL spl: spi: Add a debug message if loading fails spl: Makefile: Define SPL_ earlier spl: Allow CPU drivers to be used in SPL spl: Allow PCI drivers to be used in SPL spl: Allow RTC drivers to be used in SPL spl: Allow timer drivers to be used in SPL spl: Allow PCH drivers to be used in SPL spl: Don't create a BSS padding when it is separate x86: Use unsigned long for address in table generation WIP: x86: Update mpspec to build on 64-bit machines x86: Add basic support for U-Boot as a 64-bit EFI application x86: ivybridge: Declare global data where it is used x86: ivybridge: Add more debugging for failures x86: ivybridge: Fix types for 64-bit compilation x86: dts: Mark serial as needed before relocation x86: fsp: Fix cast for 64-bit compilation x86: lib: Fix types and casts for 64-bit compilation x86: Add Kconfig options to build 64-bit U-Boot x86: Kconfig: Add location options for 16/32-bit init x86: Use X86_16BIT_INIT instead of X86_RESET_VECTOR x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR x86: ivybridge: Allow 32-bit init to move to SPL x86: Add 64-bit start-up code x86: board_f: Update init sequence for 64-bit startup x86: board_r: Set the global data pointer after relocation x86: Do relocation before clearing BSS x86: Refactor relocation to prepare for 64-bit x86: Add support for 64-bit relocation x86: Tidy up use of size_t in relocation x86: Add an SPL implementation x86: Move the i386 code into its own directory x86: Add cpu code for x86_64 x86: Support global_data on x86_64 x86: Fix up CONFIG_X86_64 check x86: Add a link script for 64-bit x86 x86: Add a link script for SPL x86: Add SPL build rules for start-up code x86: Fix up byteorder.h for x86_64 x86: Drop flag_is_changable() on x86_64 x86: Fix up type sizes for 64-bit x86: Mention the MRC region in the README x86: ivybridge: Skipt SATA init in SPL x86: ivybridge: Provide a dummy SDRAM init for 64-bit x86: Don't try to run the VGA BIOS in 64-bit mode x86: Don't build call64 and setjmp on 64-bit x86: Don't build cpu files which are not supported on 64-bit x86: Don't build 32-bit efi files on x86_64 x86: Don't try to boot Linux from SPL x86: Drop interrupt support in 64-bit mode x86: Support jumping from SPL to U-Boot x86: Move pirq_routing_table to global_data x86: Move turbo_state to global_data x86: Change irq_already_routed to a local variable x86: Move call64 to the i386 directory x86: Move setjmp to the i386 directory x86: Add a dummy setjmp implementation for x86_64 x86: link: Add a text base for 64-bit U-Boot x86: link: Add SPL declarations to the binman image x86: link: Set up device tree for SPL x86: link: Add build options for SPL x86: Update compile/link flags to support 64-bit U-Boot x86: link: Add a config for 64-bit U-Boot Makefile | 7 +- arch/x86/Kconfig | 85 ++++ arch/x86/Makefile | 9 +- arch/x86/config.mk | 30 +- arch/x86/cpu/Makefile | 24 +- arch/x86/cpu/config.mk | 8 +- arch/x86/cpu/cpu.c | 504 -------------------- arch/x86/cpu/i386/Makefile | 9 + arch/x86/cpu/{ => i386}/call64.S | 3 + arch/x86/cpu/i386/cpu.c | 599 ++++++++++++++++++++++++ arch/x86/cpu/{interrupts.c => i386/interrupt.c} | 6 +- arch/x86/cpu/{ => i386}/setjmp.S | 0 arch/x86/cpu/intel_common/Makefile | 10 +- arch/x86/cpu/irq.c | 14 +- arch/x86/cpu/ivybridge/Makefile | 9 +- arch/x86/cpu/ivybridge/bd82x6x.c | 2 + arch/x86/cpu/ivybridge/cpu.c | 4 +- arch/x86/cpu/ivybridge/lpc.c | 2 + arch/x86/cpu/ivybridge/model_206ax.c | 2 + arch/x86/cpu/ivybridge/northbridge.c | 2 + arch/x86/cpu/ivybridge/sata.c | 4 +- arch/x86/cpu/ivybridge/sdram.c | 37 +- arch/x86/cpu/ivybridge/sdram_nop.c | 29 ++ arch/x86/cpu/start64.S | 39 ++ arch/x86/cpu/turbo.c | 8 +- arch/x86/cpu/u-boot-64.lds | 76 +++ arch/x86/cpu/u-boot-spl.lds | 74 +++ arch/x86/cpu/u-boot.lds | 2 +- arch/x86/cpu/x86_64/Makefile | 6 + arch/x86/cpu/x86_64/cpu.c | 48 ++ arch/x86/cpu/x86_64/interrupts.c | 30 ++ arch/x86/cpu/x86_64/setjmp.c | 20 + arch/x86/dts/chromebook_link.dts | 15 +- arch/x86/dts/serial.dtsi | 1 + arch/x86/dts/u-boot.dtsi | 19 + arch/x86/include/asm/acpi_table.h | 2 +- arch/x86/include/asm/byteorder.h | 17 +- arch/x86/include/asm/cpu.h | 12 + arch/x86/include/asm/fsp/fsp_hob.h | 4 +- arch/x86/include/asm/global_data.h | 8 +- arch/x86/include/asm/mp.h | 3 + arch/x86/include/asm/mpspec.h | 10 +- arch/x86/include/asm/posix_types.h | 5 + arch/x86/include/asm/sfi.h | 2 +- arch/x86/include/asm/spl.h | 8 + arch/x86/include/asm/tables.h | 2 +- arch/x86/include/asm/types.h | 5 + arch/x86/lib/Makefile | 11 + arch/x86/lib/acpi_table.c | 4 +- arch/x86/lib/bios.c | 4 +- arch/x86/lib/bootm.c | 2 + arch/x86/lib/elf_x86_64_efi.lds | 3 + arch/x86/lib/init_helpers.c | 2 +- arch/x86/lib/interrupts.c | 5 + arch/x86/lib/mpspec.c | 14 +- arch/x86/lib/pinctrl_ich6.c | 2 +- arch/x86/lib/pirq_routing.c | 14 +- arch/x86/lib/reloc_x86_64.c | 90 ++++ arch/x86/lib/relocate.c | 102 +++- arch/x86/lib/sfi.c | 6 +- arch/x86/lib/spl.c | 149 ++++++ arch/x86/lib/tables.c | 11 +- arch/x86/lib/zimage.c | 2 +- board/google/Kconfig | 7 + board/google/chromebook_link/Kconfig | 5 +- board/google/chromebook_link/MAINTAINERS | 7 + common/board_f.c | 14 +- common/board_r.c | 5 + common/console.c | 30 +- common/spl/Kconfig | 47 ++ common/spl/spl_spi.c | 5 +- configs/chromebook_link64_defconfig | 94 ++++ configs/chromebook_link_defconfig | 23 +- doc/README.x86 | 1 + drivers/Makefile | 5 + drivers/misc/qfw.c | 4 +- drivers/pci/pci_rom.c | 2 +- drivers/video/ivybridge_igd.c | 6 +- include/configs/chromebook_link.h | 9 + include/smbios.h | 4 +- lib/smbios.c | 22 +- scripts/Makefile.spl | 18 +- 82 files changed, 1871 insertions(+), 673 deletions(-) create mode 100644 arch/x86/cpu/i386/Makefile rename arch/x86/cpu/{ => i386}/call64.S (98%) create mode 100644 arch/x86/cpu/i386/cpu.c rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%) rename arch/x86/cpu/{ => i386}/setjmp.S (100%) create mode 100644 arch/x86/cpu/ivybridge/sdram_nop.c create mode 100644 arch/x86/cpu/start64.S create mode 100644 arch/x86/cpu/u-boot-64.lds create mode 100644 arch/x86/cpu/u-boot-spl.lds create mode 100644 arch/x86/cpu/x86_64/Makefile create mode 100644 arch/x86/cpu/x86_64/cpu.c create mode 100644 arch/x86/cpu/x86_64/interrupts.c create mode 100644 arch/x86/cpu/x86_64/setjmp.c create mode 100644 arch/x86/include/asm/spl.h create mode 100644 arch/x86/lib/reloc_x86_64.c create mode 100644 arch/x86/lib/spl.c create mode 100644 configs/chromebook_link64_defconfig -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH v3] arm: use common instructions applicable to armv7m & other arm archs
by Vikas Manocha 18 Mar '17

18 Mar '17

This patch cleans the code by using instructions allowed for armv7m as well as other Arm archs. Signed-off-by: Vikas Manocha <vikas.manocha(a)st.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> Reviewed-by: Heiko Schocher <hs(a)denx.de> --- Changes in v3: moved the comment to right location. Changes in v2: reword message commit. Removed info regarding BIC instruction on SP, was creating confusion. arch/arm/lib/crt0.S | 25 +++++++------------------ 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 2f4c14e..d9078aa 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -71,18 +71,12 @@ ENTRY(_main) */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr sp, =(CONFIG_SPL_STACK) + ldr r0, =(CONFIG_SPL_STACK) #else - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0, =(CONFIG_SYS_INIT_SP_ADDR) #endif -#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ - mov r3, sp - bic r3, r3, #7 - mov sp, r3 -#else - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#endif - mov r0, sp + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 bl board_init_f_alloc_reserve mov sp, r0 /* set up gd here, outside any C code */ @@ -100,14 +94,9 @@ ENTRY(_main) * 'here' but relocated. */ - ldr sp, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ -#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */ - mov r3, sp - bic r3, r3, #7 - mov sp, r3 -#else - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ -#endif + ldr r0, [r9, #GD_START_ADDR_SP] /* sp = gd->start_addr_sp */ + bic r0, r0, #7 /* 8-byte alignment for ABI compliance */ + mov sp, r0 ldr r9, [r9, #GD_BD] /* r9 = gd->bd */ sub r9, r9, #GD_SIZE /* new GD is below bd */ -- 1.9.1

3 2

[U-Boot] [PATCH] usb gadget: increase envstr size in cb_getvar
by Nicolas le bayon 10 Mar '17

10 Mar '17

Hi, I propose you this patch in order to take into account strings larger than actual size (32). I recently faced to 'fastboot.partition-type:userdata' (it was in Android context) but this could be the case for other purposes. I propose to simply double the size. Is it ok for you? Regards --- drivers/usb/gadget/f_fastboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 2160b1c..84e22e4 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -432,7 +432,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) else strcpy(response, "FAILValue not set"); } else { - char envstr[32]; + char envstr[64]; snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd); s = getenv(envstr); -- 1.9.1

3 6

[U-Boot] [RFC] odroid: Add support for the ODROID-X board variant
by Siarhei Siamashka 07 Mar '17

07 Mar '17

ODROID-X uses a slightly older revision of the same base board as the ODROID-X2. But the CPU module in ODROID-X uses an older 1.4GHz revision of Exynos4412 SoC and less RAM (1GiB instead of 2GiB). The current U-Boot code deadlocks on ODROID-X when probing the RAM size via get_ram_size() function. Reducing CONFIG_NR_DRAM_BANKS from 8 to 4 can fix this problem. But this constant is used in a lot of places in U-Boot, while SDRAM_BANK_SIZE can be easily replaced with the code which relies on runtime detection of the board type. So we change 4 or 8 banks of 256MiB with just one fake bank of 2GiB or 1GiB. The runtime detection check tries to read the PRO_ID register in the hope that it might be different between Exynos4412 and Exynos4412 Prime and enough to detect the difference between X and X2 board variants. Signed-off-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> --- I'm assuming that the X and X2 hardware is nearly identical and can be supported with a common code in U-Boot, based on the changelog of PCB revisions: http://com.odroid.com/sigong/blog/blog_list.php?bid=132 This is an RFC patch because I don't have an X2 board and can't test if checking the PRO_ID register is good enough. If it does not work, then maybe some other method could be tried (probe the DRAM controller registers?). Also does the number of DRAM banks have any special meaning on this platform in U-Boot and Linux (after the proprietary blob has already initialized the DRAM controller)? If this approach is wrong, then what would be the best way to add support for the ODROID-X board? Thanks. board/samsung/common/board.c | 21 +++++++++++++++++---- board/samsung/odroid/odroid.c | 14 ++++++++++---- include/configs/odroid.h | 10 ++++++---- 3 files changed, 33 insertions(+), 12 deletions(-) diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index d32c75d..ac3ed4c 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -94,14 +94,26 @@ int board_init(void) return exynos_init(); } +static u32 get_sdram_bank_size(void) +{ + u32 sdram_bank_size = SDRAM_BANK_SIZE; +#ifdef CONFIG_BOARD_TYPES + if (strcmp(CONFIG_SYS_BOARD, "odroid") == 0 && + strcmp(get_board_type(), "x") == 0) + sdram_bank_size = SDRAM_BANK_SIZE_ODROIDX; +#endif + return sdram_bank_size; +} + int dram_init(void) { unsigned int i; u32 addr; + u32 sdram_bank_size = get_sdram_bank_size(); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); + addr = CONFIG_SYS_SDRAM_BASE + (i * sdram_bank_size); + gd->ram_size += get_ram_size((long *)addr, sdram_bank_size); } return 0; } @@ -110,10 +122,11 @@ void dram_init_banksize(void) { unsigned int i; u32 addr, size; + u32 sdram_bank_size = get_sdram_bank_size(); for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); - size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); + addr = CONFIG_SYS_SDRAM_BASE + (i * sdram_bank_size); + size = get_ram_size((long *)addr, sdram_bank_size); gd->bd->bi_dram[i].start = addr; gd->bd->bi_dram[i].size = size; diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 32155f1..e98e3be 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; enum { ODROID_TYPE_U3, ODROID_TYPE_X2, + ODROID_TYPE_X, ODROID_TYPES, }; @@ -56,15 +57,20 @@ void set_board_type(void) sdelay(200000); /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */ - if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN)) - gd->board_type = ODROID_TYPE_X2; - else + if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN)) { + /* Check the SoC product information ID */ + if (readl(EXYNOS4_PRO_ID) == 0xE4412211) + gd->board_type = ODROID_TYPE_X; + else + gd->board_type = ODROID_TYPE_X2; + } else { gd->board_type = ODROID_TYPE_U3; + } } const char *get_board_type(void) { - const char *board_type[] = {"u3", "x2"}; + const char *board_type[] = {"u3", "x2", "x"}; return board_type[gd->board_type]; } diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 4c85e85..ae1b2b4 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -22,9 +22,10 @@ #define CONFIG_MACH_TYPE 4289 -#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +#define SDRAM_BANK_SIZE ((8 * 256) << 20) /* 8 * 256 MB */ +#define SDRAM_BANK_SIZE_ODROIDX ((4 * 256) << 20) /* 4 * 256 MB */ #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* Reserve the last 1 MiB for the secure firmware */ #define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) @@ -75,6 +76,7 @@ "uInitrd fat 0 1;" \ "exynos4412-odroidu3.dtb fat 0 1;" \ "exynos4412-odroidx2.dtb fat 0 1;" \ + "exynos4412-odroidx.dtb fat 0 1;" \ ""PARTS_BOOT" part 0 1;" \ ""PARTS_ROOT" part 0 2\0" \ @@ -209,8 +211,8 @@ #define CONFIG_USB_ETHER_SMSC95XX /* - * Supported Odroid boards: X3, U3 - * TODO: Add Odroid X support + * Supported Odroid boards: X, X2, U3 + * TODO: Add Odroid U2 support */ #define CONFIG_MISC_COMMON #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -- 2.4.9

2 2

[U-Boot] [PATCH] fastboot: avoid printing invalid data
by John Keeping 05 Mar '17

05 Mar '17

There is no guarantee that commands are null-terminated in the USB request buffer, so limit the length of data that is printed. Signed-off-by: John Keeping <john(a)metanate.com> --- drivers/usb/gadget/f_fastboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 2160b1c..a020b7d 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -710,7 +710,7 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) } if (!func_cb) { - error("unknown command: %s", cmdbuf); + error("unknown command: %.*s", req->actual, cmdbuf); fastboot_tx_write_str("FAILunknown command"); } else { if (req->actual < req->length) { -- 2.9.3.728.g30b24b4.dirty

3 2