November 2016 - U-Boot

[U-Boot] [PATCH v7 0/2] armv8: Support loading 32-bit OS in AArch32 execution state
by Alison Wang 10 Nov '16

10 Nov '16

This series is to support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. --------------------------------------- Changes in v7: - Move the call for armv8_switch_to_el2_m into the first patch. Changes in v6: - Modified armv8_switch_to_el1(). It will always jump to ep when switching to AArch64 or AArch32 modes. - Make other platforms compatible with the new armv8_switch_to_el2() and armv8_switch_to_el1(). - Make secondary_switch_to_el1() always jump to ep when switching to AArch64 or AArch32 modes. Changes in v5: - Modified armv8_switch_to_el2(). It will always jump to ep when switching to AArch64 or AArch32 modes. - Make secondary_switch_to_el2() always jump to ep when switching to AArch64 or AArch32 modes. Changes in v4: - Correct config ARM64_SUPPORT_AARCH32. - Omit arch and ftaddr arguments. - Rename "xreg5" to "tmp". - Use xxx_RES1 to combine all RES1 fields in xxx register. - Use an immediate cmp directly. - Use #ifdef for CONFIG_ARM64_SUPPORT_AARCH32. Changes in v3: - Comments the functions and the arguments. - Rename the real parameters. - Use the macros instead of the magic values. - Remove the redundant codes. - Clean up all of the mess in boot_jump_linux(). - Add CONFIG_ARM64_SUPPORT_AARCH32 to detect for some ARM64 system doesn't support AArch32 state. - Adjust the arguments for armv8_switch_to_el2_m and armv8_switch_to_el1_m. Changes in v2: - armv8_switch_to_el2_aarch32() is removed. armv8_switch_to_el2_m is used to switch to AArch64 EL2 or AArch32 Hyp. - armv8_switch_to_el1_aarch32() is removed. armv8_switch_to_el1_m is used to switch to AArch64 EL1 or AArch32 SVC. - Support to call armv8_switch_to_el2_m and armv8_switch_to_el1_m. ---------------------------------------------------------------- Alison Wang (2): armv8: Support loading 32-bit OS in AArch32 execution state armv8: fsl-layerscape: SMP support for loading 32-bit OS arch/arm/Kconfig | 6 +++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 61 +++++++++++++++++++++----- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 +++++ arch/arm/cpu/armv8/start.S | 8 ++++ arch/arm/cpu/armv8/transition.S | 8 ++-- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 +++ arch/arm/include/asm/macro.h | 176 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------- arch/arm/include/asm/system.h | 119 ++++++++++++++++++++++++++++++++++++++++++++++++++- arch/arm/lib/bootm.c | 45 ++++++++++++++++--- arch/arm/mach-rmobile/lowlevel_init_gen3.S | 9 +++- common/image-fit.c | 19 +++++++- 11 files changed, 401 insertions(+), 66 deletions(-)

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[U-Boot] Encryption of FIT image
by Zvi Vered 10 Nov '16

10 Nov '16

Hello, Can you tell if this is possible ? How ? Thank you, Zvika Vered

1 0

[U-Boot] [PATCH 1/3] fsl/ddr: Revise erratum a009942 and clean related erratum
by Shengzhou Liu 09 Nov '16

09 Nov '16

- add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +- arch/powerpc/include/asm/config_mpc85xx.h | 2 - board/freescale/ls1021aqds/ls1021aqds.c | 6 +- drivers/ddr/fsl/ctrl_regs.c | 104 +++++++++++++++++++++++++++++- drivers/ddr/fsl/fsl_ddr_gen4.c | 23 ------- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 3 - include/fsl_ddr.h | 2 + include/fsl_ddr_sdram.h | 3 +- 9 files changed, 121 insertions(+), 35 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index b7a2e0c..19de15e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -25,6 +25,9 @@ #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT #include <asm/armv8/sec_firmware.h> #endif +#ifdef CONFIG_SYS_FSL_DDR +#include <fsl_ddr.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -400,7 +403,9 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 erratum_a009635(); #endif - +#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR) + erratum_a009942_check_cpo(); +#endif #ifdef CONFIG_MP #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI) /* Check the psci version to determine if the psci is supported */ diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 53b3729..c1dbd9c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -45,7 +45,7 @@ #include <nand.h> #include <errno.h> #endif - +#include <fsl_ddr.h> #include "../../../../drivers/block/fsl_sata.h" #ifdef CONFIG_U_QE #include <fsl_qe.h> @@ -947,6 +947,10 @@ int cpu_init_r(void) #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + erratum_a009942_check_cpo(); +#endif + #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 6d845e8..1e62a9c 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -681,7 +681,6 @@ #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A004468 -#define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A007186 @@ -720,7 +719,6 @@ #define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_FSL_ERRATUM_A006379 #define CONFIG_SYS_FSL_ERRATUM_A007186 diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 4eb38a7..79078d2 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -22,7 +22,7 @@ #include <spl.h> #include <fsl_devdis.h> #include <fsl_validate.h> - +#include <fsl_ddr.h> #include "../common/sleep.h" #include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -433,7 +433,9 @@ int board_init(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); #endif - +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + erratum_a009942_check_cpo(); +#endif major = get_soc_major_rev(); if (major == SOC_MAJOR_VER_1_0) { /* Set CCI-400 control override register to diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 24fd366..656de2c 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -5,14 +5,14 @@ */ /* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller. * Based on code from spd_sdram.c * Author: James Yang [at freescale.com] */ #include <common.h> #include <fsl_ddr_sdram.h> - +#include <fsl_errata.h> #include <fsl_ddr.h> #include <fsl_immap.h> #include <asm/io.h> @@ -2305,6 +2305,9 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, unsigned int wrlvl_en; unsigned int ip_rev = 0; unsigned int unq_mrs_en = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + unsigned int ddr_freq; +#endif int cs_en = 1; memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); @@ -2526,5 +2529,102 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, ddr->debug[2] |= 0x00000200; /* set bit 22 */ #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4) + /* Erratum applies when accumulated ECC is used, or DBI is enabled */ +#define IS_ACC_ECC_EN(v) ((v) & 0x4) +#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) + if (has_erratum_a008378()) { + if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) || + IS_DBI(ddr->ddr_sdram_cfg_3)) + ddr->debug[28] |= (0x9 << 20); + } +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + /* the POR value of debug_29 register is zero */ + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + if (ddr_freq <= 1333) + ddr->debug[28] |= 0x0080006a; + else if (ddr_freq <= 1600) + ddr->debug[28] |= 0x0070006f; + else if (ddr_freq <= 1867) + ddr->debug[28] |= 0x00700076; + else if (ddr_freq <= 2133) + ddr->debug[28] |= 0x0060007b; + if (popts->cpo_sample) + ddr->debug[28] = (ddr->debug[28] & 0xffffff00) | + popts->cpo_sample; +#endif + return check_fsl_memctl_config_regs(ddr); } + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 +/* + * This additional workaround of A009942 checks the condition to determine if + * the CPO value set by the existing A009942 workaround needs to be updated. + * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with + * expected optimal value, the optimal value is highly board dependent. + */ +void erratum_a009942_check_cpo(void) +{ + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal; + u32 min_cpo = 0, max_cpo = 0; + u32 sdram_cfg, i, tmp, lanes, ddr_type; + bool update_cpo = false, has_ecc = false; + + sdram_cfg = ddr_in32(&ddr->sdram_cfg); + if (sdram_cfg & SDRAM_CFG_32_BE) + lanes = 4; + else if (sdram_cfg & SDRAM_CFG_16_BE) + lanes = 2; + else + lanes = 8; + + if (sdram_cfg & SDRAM_CFG_ECC_EN) + has_ecc = true; + + /* determine the maximum and minimum CPO values */ + for (i = 9; i < 9 + lanes / 2; i++) { + cpo = ddr_in32(&ddr->debug[i]); + cpo_e = cpo >> 24; + cpo_o = (cpo >> 8) & 0xff; + tmp = min(cpo_e, cpo_o); + if (tmp < min_cpo) + min_cpo = tmp; + tmp = max(cpo_e, cpo_o); + if (tmp > max_cpo) + max_cpo = tmp; + } + + if (has_ecc) { + cpo = ddr_in32(&ddr->debug[13]); + cpo = cpo >> 24; + if (cpo << min_cpo) + min_cpo = cpo; + if (cpo > max_cpo) + max_cpo = cpo; + } + + cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; + cpo_optimal = ((max_cpo + min_cpo) >> 1) + 0x27; + debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal, + cpo_target); + debug("max_cpo = 0x%x, min_cpo = 0x%x\n", max_cpo, min_cpo); + + ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> + SDRAM_CFG_SDRAM_TYPE_SHIFT; + if (ddr_type == SDRAM_TYPE_DDR4) + update_cpo = (min_cpo + 0x3b) < cpo_target ? true : false; + else if (ddr_type == SDRAM_TYPE_DDR3) + update_cpo = (min_cpo + 0x3f) < cpo_target ? true : false; + + if (update_cpo) { + printf("WARN: This board needs to optimize debug_29, pls set "); + printf("\'popts->cpo_sample = 0x%x\' in <board>/ddr.c\n", + cpo_optimal); + } +} +#endif diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 042af09..2a5066a 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -230,16 +230,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[i], regs->debug[i]); } } -#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 - /* Erratum applies when accumulated ECC is used, or DBI is enabled */ -#define IS_ACC_ECC_EN(v) ((v) & 0x4) -#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) - if (has_erratum_a008378()) { - if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || - IS_DBI(regs->ddr_sdram_cfg_3)) - ddr_setbits32(&ddr->debug[28], 0x9 << 20); - } -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A008511 /* Part 1 of 2 */ @@ -277,19 +267,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[25], temp32); #endif -#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 - ddr_freq = get_ddr_freq(ctrl_num) / 1000000; - tmp = ddr_in32(&ddr->debug[28]); - if (ddr_freq <= 1333) - ddr_out32(&ddr->debug[28], tmp | 0x0080006a); - else if (ddr_freq <= 1600) - ddr_out32(&ddr->debug[28], tmp | 0x0070006f); - else if (ddr_freq <= 1867) - ddr_out32(&ddr->debug[28], tmp | 0x00700076); - else if (ddr_freq <= 2133) - ddr_out32(&ddr->debug[28], tmp | 0x0060007b); -#endif - #ifdef CONFIG_SYS_FSL_ERRATUM_A010165 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; if ((ddr_freq > 1900) && (ddr_freq < 2300)) { diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 653b7f0..1bfb9d4 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -174,9 +174,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->debug[i], regs->debug[i]); } } -#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 - out_be32(&ddr->debug[28], 0x30003000); -#endif #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 out_be32(&ddr->debug[12], 0x00000015); diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 3351acd..0c3be0e 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -138,4 +138,6 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, void update_spd_address(unsigned int ctrl_num, unsigned int slot, unsigned int *addr); + +void erratum_a009942_check_cpo(void); #endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 36bd9d7..1404c57 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -374,7 +374,8 @@ typedef struct memctl_options_s { unsigned int additive_latency_override_value; unsigned int clk_adjust; /* */ - unsigned int cpo_override; + unsigned int cpo_override; /* override timing_cfg_2[CPO]*/ + unsigned int cpo_sample; /* optimize debug_29[24:31] */ unsigned int write_data_delay; /* DQS adjust */ unsigned int cswl_override; -- 2.1.0.27.g96db324

3 9

[U-Boot] [PATCH] driver: net: fsl-mc: Use aligned address for MC FW load
by Priyanka Jain 09 Nov '16

09 Nov '16

Firmware of Management Complex (MC) should be loaded at 512MB aligned address. So use aligned address for firmware load. Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> --- drivers/net/fsl-mc/mc.c | 62 ++++++++++++++++++++++++++-------------------- 1 files changed, 35 insertions(+), 27 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 1811b0f..c66340b 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; static int mc_boot_status = -1; static int mc_dpl_applied = -1; +static u64 mc_ram_aligned_base_addr; #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET static int mc_aiop_applied = -1; #endif @@ -87,12 +88,15 @@ void dump_mc_ccsr_regs(struct mc_ccsr_registers __iomem *mc_ccsr_regs) /** * Copying MC firmware or DPL image to DDR */ -static int mc_copy_image(const char *title, - u64 image_addr, u32 image_size, u64 mc_ram_addr) +static int mc_copy_image(const char *title, u64 image_addr, + u32 image_size, u64 mc_ram_aligned_base_addr) { - debug("%s copied to address %p\n", title, (void *)mc_ram_addr); - memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); - flush_dcache_range(mc_ram_addr, mc_ram_addr + image_size); + debug("%s copied to address %p\n", title, + (void *)mc_ram_aligned_base_addr); + memcpy((void *)mc_ram_aligned_base_addr, + (void *)image_addr, image_size); + flush_dcache_range(mc_ram_aligned_base_addr, + mc_ram_aligned_base_addr + image_size); return 0; } @@ -224,7 +228,8 @@ static int mc_fixup_dpc(u64 dpc_addr) return 0; } -static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) +static int load_mc_dpc(u64 mc_ram_aligned_base_addr, size_t mc_ram_size, + u64 mc_dpc_addr) { u64 mc_dpc_offset; #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR @@ -246,7 +251,8 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) * Load the MC DPC blob in the MC private DRAM block: */ #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR - printf("MC DPC is preloaded to %#llx\n", mc_ram_addr + mc_dpc_offset); + printf("MC DPC is preloaded to %#llx\n", + mc_ram_aligned_base_addr + mc_dpc_offset); #else /* * Get address and size of the DPC blob stored in flash: @@ -270,18 +276,20 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) return -EINVAL; } - mc_copy_image("MC DPC blob", - (u64)dpc_fdt_hdr, dpc_size, mc_ram_addr + mc_dpc_offset); + mc_copy_image("MC DPC blob", (u64)dpc_fdt_hdr, dpc_size, + mc_ram_aligned_base_addr + mc_dpc_offset); #endif /* not defined CONFIG_SYS_LS_MC_DPC_IN_DDR */ - if (mc_fixup_dpc(mc_ram_addr + mc_dpc_offset)) + if (mc_fixup_dpc(mc_ram_aligned_base_addr + mc_dpc_offset)) return -EINVAL; - dump_ram_words("DPC", (void *)(mc_ram_addr + mc_dpc_offset)); + dump_ram_words("DPC", + (void *)(mc_ram_aligned_base_addr + mc_dpc_offset)); return 0; } -static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) +static int load_mc_dpl(u64 mc_ram_aligned_base_addr, size_t mc_ram_size, + u64 mc_dpl_addr) { u64 mc_dpl_offset; #ifndef CONFIG_SYS_LS_MC_DPL_IN_DDR @@ -303,7 +311,8 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) * Load the MC DPL blob in the MC private DRAM block: */ #ifdef CONFIG_SYS_LS_MC_DPL_IN_DDR - printf("MC DPL is preloaded to %#llx\n", mc_ram_addr + mc_dpl_offset); + printf("MC DPL is preloaded to %#llx\n", + mc_ram_aligned_base_addr + mc_dpl_offset); #else /* * Get address and size of the DPL blob stored in flash: @@ -323,11 +332,12 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) return -EINVAL; } - mc_copy_image("MC DPL blob", - (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset); + mc_copy_image("MC DPL blob", (u64)dpl_fdt_hdr, dpl_size, + mc_ram_aligned_base_addr + mc_dpl_offset); #endif /* not defined CONFIG_SYS_LS_MC_DPL_IN_DDR */ - dump_ram_words("DPL", (void *)(mc_ram_addr + mc_dpl_offset)); + dump_ram_words("DPL", + (void *)(mc_ram_aligned_base_addr + mc_dpl_offset)); return 0; } @@ -364,7 +374,6 @@ __weak bool soc_has_aiop(void) static int load_mc_aiop_img(u64 aiop_fw_addr) { - u64 mc_ram_addr = mc_get_dram_addr(); #ifndef CONFIG_SYS_LS_MC_DPC_IN_DDR void *aiop_img; #endif @@ -377,13 +386,14 @@ static int load_mc_aiop_img(u64 aiop_fw_addr) */ #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR - printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr + + printf("MC AIOP is preloaded to %#llx\n", mc_ram_aligned_base_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); #else aiop_img = (void *)aiop_fw_addr; mc_copy_image("MC AIOP image", (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, - mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); + mc_ram_aligned_base_addr + + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); #endif mc_aiop_applied = 0; @@ -450,7 +460,6 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) size_t raw_image_size = 0; #endif struct mc_version mc_ver_info; - u64 mc_ram_aligned_base_addr; u8 mc_ram_num_256mb_blocks; size_t mc_ram_size = mc_get_dram_block_size(); @@ -478,7 +487,7 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) dmb(); #ifdef CONFIG_SYS_LS_MC_FW_IN_DDR - printf("MC firmware is preloaded to %#llx\n", mc_ram_addr); + printf("MC firmware is preloaded to %#llx\n", mc_ram_aligned_base_addr); #else error = parse_mc_firmware_fit_image(mc_fw_addr, &raw_image_addr, &raw_image_size); @@ -487,12 +496,12 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) /* * Load the MC FW at the beginning of the MC private DRAM block: */ - mc_copy_image("MC Firmware", - (u64)raw_image_addr, raw_image_size, mc_ram_addr); + mc_copy_image("MC Firmware", (u64)raw_image_addr, raw_image_size, + mc_ram_aligned_base_addr); #endif - dump_ram_words("firmware", (void *)mc_ram_addr); + dump_ram_words("firmware", (void *)mc_ram_aligned_base_addr); - error = load_mc_dpc(mc_ram_addr, mc_ram_size, mc_dpc_addr); + error = load_mc_dpc(mc_ram_aligned_base_addr, mc_ram_size, mc_dpc_addr); if (error != 0) goto out; @@ -569,10 +578,9 @@ int mc_apply_dpl(u64 mc_dpl_addr) struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; int error = 0; u32 reg_gsr; - u64 mc_ram_addr = mc_get_dram_addr(); size_t mc_ram_size = mc_get_dram_block_size(); - error = load_mc_dpl(mc_ram_addr, mc_ram_size, mc_dpl_addr); + error = load_mc_dpl(mc_ram_aligned_base_addr, mc_ram_size, mc_dpl_addr); if (error != 0) return error; -- 1.7.4.1

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[U-Boot] [PATCH v2 0/4] serial: pxa: kconfig and optional driver model integration
by Marcel Ziswiler 09 Nov '16

09 Nov '16

This series integrates both Kconfig as well as optional driver model support for the PXA serial driver. As I do not have any of the other hardware available for testing for now I only transitioned the Colibri PXA270 to actually make use of DM_SERIAL. As space on this mostly NOR based hardware is rather constrained I decided against also integrating device tree support for now but rather use olde platform data. Your input on this is more than welcome. Changes in v2: - Introduce new patch saving more precious space. - Drop baudrate checks. - Use panic instead of just hang() to more gracefully handle failure case. - Drop superfluous parenthesis around plat->base. - Capitalise header file gating macro. - Replace tab with space after #define. Marcel Ziswiler (4): serial: pxa: use kconfig for serial configuration serial: pxa: integrate optional driver model handling colibri_pxa270: drop edit, elf, fpga, hush, regex et al. for space reason colibri_pxa270: transition to driver model for serial board/toradex/colibri_pxa270/colibri_pxa270.c | 18 ++- configs/colibri_pxa270_defconfig | 9 +- configs/h2200_defconfig | 1 + configs/zipitz2_defconfig | 1 + drivers/serial/Kconfig | 6 + drivers/serial/serial_pxa.c | 184 ++++++++++++++++---------- include/configs/colibri_pxa270.h | 7 +- include/configs/h2200.h | 2 - include/configs/zipitz2.h | 1 - include/dm/platform_data/serial_pxa.h | 56 ++++++++ scripts/config_whitelist.txt | 1 - 11 files changed, 204 insertions(+), 82 deletions(-) create mode 100644 include/dm/platform_data/serial_pxa.h -- 2.5.5

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[U-Boot] [PATCH v2 0/7] imx6: Add Engicam GEAM6UL/i.CoreM6 RQS board support
by Jagan Teki 09 Nov '16

09 Nov '16

From: Jagan Teki <jagan(a)amarulasolutions.com> Changes for v2: - Add 'Acked-by' from Joe - Add new i.CoreM6 RQS patches Jagan Teki (7): arm: dts: Add devicetree for i.MX6UL arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support dm: net: fec: Add .read_rom_hwaddr net: fec: Zap local mac variable arm: imx6q: Add Engicam i.CoreM6 Quad/Dual RQS Starter Kit initial support arm: imx6q: Add Engicam i.CoreM6 Solo/Duallite RQS Starter Kit initial support imx6: icorem6: Rename engicam icorem6 defconfig files arch/arm/cpu/armv7/mx6/Kconfig | 22 + arch/arm/dts/Makefile | 5 +- arch/arm/dts/imx6dl-icore-rqs.dts | 50 ++ arch/arm/dts/imx6q-icore-rqs.dts | 50 ++ arch/arm/dts/imx6qdl-icore-rqs.dtsi | 101 +++ arch/arm/dts/imx6ul-geam-kit.dts | 119 +++ arch/arm/dts/imx6ul.dtsi | 942 +++++++++++++++++++++ board/engicam/geam6ul/Kconfig | 12 + board/engicam/geam6ul/MAINTAINERS | 6 + board/engicam/geam6ul/Makefile | 6 + board/engicam/geam6ul/README | 28 + board/engicam/geam6ul/geam6ul.c | 246 ++++++ board/engicam/icorem6/MAINTAINERS | 6 +- board/engicam/icorem6/README | 19 +- board/engicam/icorem6_rqs/Kconfig | 12 + board/engicam/icorem6_rqs/MAINTAINERS | 7 + board/engicam/icorem6_rqs/Makefile | 6 + board/engicam/icorem6_rqs/README | 33 + board/engicam/icorem6_rqs/icorem6_rqs.c | 402 +++++++++ ...re_mmc_defconfig => imx6dl_icore_mmc_defconfig} | 0 ..._nand_defconfig => imx6dl_icore_nand_defconfig} | 0 configs/imx6dl_icore_rqs_mmc_defconfig | 38 + configs/imx6q_icore_mmc_defconfig | 46 + configs/imx6q_icore_nand_defconfig | 41 + configs/imx6q_icore_rqs_mmc_defconfig | 38 + configs/imx6ul_geam_mmc_defconfig | 39 + drivers/net/fec_mxc.c | 50 +- include/configs/imx6qdl_icore_rqs.h | 124 +++ include/configs/imx6ul_geam.h | 125 +++ include/dt-bindings/clock/imx6ul-clock.h | 1 + 30 files changed, 2532 insertions(+), 42 deletions(-) create mode 100644 arch/arm/dts/imx6dl-icore-rqs.dts create mode 100644 arch/arm/dts/imx6q-icore-rqs.dts create mode 100644 arch/arm/dts/imx6qdl-icore-rqs.dtsi create mode 100644 arch/arm/dts/imx6ul-geam-kit.dts create mode 100644 arch/arm/dts/imx6ul.dtsi create mode 100644 board/engicam/geam6ul/Kconfig create mode 100644 board/engicam/geam6ul/MAINTAINERS create mode 100644 board/engicam/geam6ul/Makefile create mode 100644 board/engicam/geam6ul/README create mode 100644 board/engicam/geam6ul/geam6ul.c create mode 100644 board/engicam/icorem6_rqs/Kconfig create mode 100644 board/engicam/icorem6_rqs/MAINTAINERS create mode 100644 board/engicam/icorem6_rqs/Makefile create mode 100644 board/engicam/icorem6_rqs/README create mode 100644 board/engicam/icorem6_rqs/icorem6_rqs.c rename configs/{imx6qdl_icore_mmc_defconfig => imx6dl_icore_mmc_defconfig} (100%) rename configs/{imx6qdl_icore_nand_defconfig => imx6dl_icore_nand_defconfig} (100%) create mode 100644 configs/imx6dl_icore_rqs_mmc_defconfig create mode 100644 configs/imx6q_icore_mmc_defconfig create mode 100644 configs/imx6q_icore_nand_defconfig create mode 100644 configs/imx6q_icore_rqs_mmc_defconfig create mode 100644 configs/imx6ul_geam_mmc_defconfig create mode 100644 include/configs/imx6qdl_icore_rqs.h create mode 100644 include/configs/imx6ul_geam.h -- 1.9.1

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[U-Boot] [PATCH v2] armv8: fsl-layerscape: Add Readme for deploy QSPI image
by Yuan Yao 09 Nov '16

09 Nov '16

From: Yuan Yao <yao.yuan(a)nxp.com> Signed-off-by: Yuan Yao <yao.yuan(a)nxp.com> --- Changed in v2: Move the readme for QSPI deploy out of only for ls2080aqds. --- .../arm/cpu/armv8/fsl-layerscape/doc/README.deploy | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy new file mode 100644 index 0000000..25813b3 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.deploy @@ -0,0 +1,44 @@ +Boot source support Overview +------------------- + 1. LS1043A + LS1043AQDS:QSPI, SD, NOR, NAND + LS1043ARDB:SD, NOR, NAND + 2. LS2080A + LS2080AQDS:QSPI, SD, NOR, NAND + LS2080ARDB:NOR, NAND + 3. LS1012A + LS1012AQDS:QSPI + LS1012ARDB:QSPI + 4. LS1046A + LS1046AQDS:QSPI, SD, NOR, NAND + LS1046ARDB:QSPI, SD + +Booting from QSPI +------------------- +Booting from QSPI requires two images, RCW and u-boot-dtb.bin. +The difference between QSPI boot RCW image and NOR boot image is the PBI +command sequence for setting the boot location pointer. It's should point +to the address for u-boot in QSPI flash. + +RCW image should be written to the beginning of QSPI flash device. +Example of using u-boot command + +=> sf probe 0:0 +SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB +=> sf erase 0 +<size of rcw image> +SF: 65536 bytes @ 0x0 Erased: OK +=> sf write <rcw image in memory> 0 <size of rcw image> +SF: 164 bytes @ 0x0 Written: OK + +To get the QSPI image, build u-boot with QSPI config, for example, +<board_name>_qspi_defconfig. The image needed is u-boot-dtb.bin. +The u-boot image should be written to 0x10000(but 0x1000 for LS1043A, LS2080A). + +=> sf probe 0:0 +SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB +=> sf erase 10000 +<size of u-boot image> +SF: 589824 bytes @ 0x10000 Erased: OK +=> sf write <u-boot image in memory> 10000 <size of u-boot image> +SF: 580966 bytes @ 0x10000 Written: OK + +With these two images in QSPI flash device, the board can boot from QSPI. -- 2.1.0.27.g96db324

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[U-Boot] Issues coupling am335x with VSC8601 PHY
by Alex 09 Nov '16

09 Nov '16

Hi, I'm trying to enable ethernet on a custom board with an am335x soc, and a VSC8601 connected through RGMII. The plan is to use u-boot as a first stage loader to load a proprietary application (called "the app"). The app already has its own ethernet stack and drivers, and can successfully do network talk. I started with the am3355x config, and with a few trivial hacks, [1], [2], and [3], I was able to get the PHY recognized in u-boot. Auto-negotiation works correctly on 100Mbit link. The issue is that while packets seem to get transmitted when doing DHCP queries (light on the switch blinks), they aren't legible. I tried hooking up the board to an ethernet port with static IPs, and watching traffic with wireshark, but did not observe any packets. I also probed the RGMII link and it seems the TX clock is running at 10 MHz, instead of 25MHz, when the app is running. At this point I suspect either a gross misconfiguration on my part, or a bug in the cpsw code. I was hoping someone here might have an idea what to do to get ethernet working. Thanks, Alex [1] diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ec70b72..63a5b29 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -433,6 +433,7 @@ #define CONFIG_PHY_SMSC /* Enable Atheros phy driver */ #define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_VITESSE /* * NOR Size = 16 MiB [2] diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts index c1a53e2..153a06f 100644 --- a/arch/arm/dts/am335x-evm.dts +++ b/arch/arm/dts/am335x-evm.dts @@ -585,8 +585,8 @@ }; &cpsw_emac0 { - phy_id = <&davinci_mdio>, <0>; - phy-mode = "rgmii-txid"; + phy_id = <&davinci_mdio>, <8>; + phy-mode = "rgmii"; }; &cpsw_emac1 { [3] diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 27979bd..e758429 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -341,7 +341,7 @@ static unsigned short detect_daughter_board_profile(void) void enable_board_pin_mux(void) { /* Do board-specific muxes. */ - if (board_is_bone()) { + if (0 && board_is_bone()) { /* Beaglebone pinmux */ configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); @@ -352,7 +352,7 @@ void enable_board_pin_mux(void) #else configure_module_pin_mux(mmc1_pin_mux); #endif - } else if (board_is_gp_evm()) { + } else if (1 || board_is_gp_evm()) { /* General Purpose EVM */ unsigned short profile = detect_daughter_board_profile(); configure_module_pin_mux(rgmii1_pin_mux);

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[U-Boot] Pull request, u-boot-tegra/master
by Tom Warren 08 Nov '16

08 Nov '16

Tom, Please pull u-boot-tegra/master into U-Boot/master. Thanks! All Tegra builds are OK, and Stephen's automated test system reports that all tests pass. The following changes since commit 4b6035da482cccda06aeb419634f99937c9fc783: mx6sabresd: Make Ethernet functional again (2016-11-06 06:59:27 -0500) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to a8d0526133e542ea93a741fd18833e571e817775: ARM: tegra186: call secure monitor for all cache-wide ops (2016-11-07 14:36:29 -0800) ---------------------------------------------------------------- Stephen Warren (4): ARM: tegra: ensure nvtboot_boot_x0 alignment ARM: tegra: translate __asm_flush_l3_cache to assembly armv8: add hooks for all cache-wide operations ARM: tegra186: call secure monitor for all cache-wide ops arch/arm/cpu/armv8/cache.S | 18 ++++++++++-- arch/arm/cpu/armv8/cache_v8.c | 8 ++++-- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 +-- arch/arm/include/asm/system.h | 4 ++- arch/arm/mach-tegra/tegra186/cache.S | 43 ++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra186/cache.c | 23 --------------- arch/arm/mach-tegra/tegra186/nvtboot_ll.S | 1 + 7 files changed, 69 insertions(+), 32 deletions(-) create mode 100644 arch/arm/mach-tegra/tegra186/cache.S delete mode 100644 arch/arm/mach-tegra/tegra186/cache.c

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[U-Boot] Pull request: u-boot-net.git master
by Joe Hershberger 08 Nov '16

08 Nov '16

Hi Tom, The following changes since commit 4b6035da482cccda06aeb419634f99937c9fc783: mx6sabresd: Make Ethernet functional again (2016-11-06 06:59:27 -0500) are available in the git repository at: git://git.denx.de/u-boot-net.git master for you to fetch changes up to aa555fe9f07a21b3bbdab15aea594f3869e5ab22: net: use random ethernet address if invalid and not zero (2016-11-07 11:28:16 -0600) ---------------------------------------------------------------- Ash Charles (1): net: phy: micrel: center FLP burst timing at 16ms Chris Packham (1): net: mvgbe: Fix build error with CONFIG_PHYLIB Siva Durga Prasad Paladugu (1): net: use random ethernet address if invalid and not zero Stephen Warren (6): dt: net: add DWC EQoS binding net: add driver for Synopsys Ethernet QoS device ARM: tegra: add SoC-level hook for board_late_init() ARM: tegra: configure Ethernet address on Tegra186 ARM: tegra: add DWC EQoS (ethernet) to Tegra186 DT ARM: tegra: enable Ethernet on p2771-0000 arch/arm/dts/tegra186-p2771-0000.dtsi | 5 + arch/arm/dts/tegra186.dtsi | 20 + arch/arm/mach-tegra/board186.c | 7 +- arch/arm/mach-tegra/tegra186/Makefile | 1 + arch/arm/mach-tegra/tegra186/nvtboot_board.c | 54 + configs/p2771-0000-000_defconfig | 1 + configs/p2771-0000-500_defconfig | 1 + .../net/snps,dwc-qos-ethernet.txt | 166 +++ drivers/net/Kconfig | 11 + drivers/net/Makefile | 1 + drivers/net/dwc_eth_qos.c | 1552 ++++++++++++++++++++ drivers/net/mvgbe.c | 25 +- drivers/net/phy/micrel.c | 23 + include/micrel.h | 3 + net/eth-uclass.c | 3 +- 15 files changed, 1849 insertions(+), 24 deletions(-) create mode 100644 arch/arm/mach-tegra/tegra186/nvtboot_board.c create mode 100644 doc/device-tree-bindings/net/snps,dwc-qos-ethernet.txt create mode 100644 drivers/net/dwc_eth_qos.c Thanks! -Joe

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