November 2016 - U-Boot

[U-Boot] [PATCH v2 0/4] buildman: Threading and output improvements
by Simon Glass 13 Nov '16

13 Nov '16

This series includes a few minor improvements to buildman: - Cleaner output and updates on what buildman is doing at the start - a way to generate only the CONFIG options in a build, for speed (-D) - a fix for pressing Ctrl-C during a build (so that it exits cleanly). (all but the second is now applied) Changes in v2: - Rebase to mainline with Masahiro's changes - Fix failure to reconfigure when needed - Drop patches previously applied Simon Glass (4): Makefile: Add a target to create the .cfg files buildman: Add an option to just create the config buildman: Add documentation for CONFIG checking buildman: Squash useless output from -K Makefile | 3 +++ tools/buildman/README | 49 +++++++++++++++++++++++++++++++++++++++++ tools/buildman/builder.py | 37 +++++++++++++++++++++---------- tools/buildman/builderthread.py | 14 +++++++----- tools/buildman/cmdline.py | 4 ++++ tools/buildman/control.py | 4 +++- 6 files changed, 93 insertions(+), 18 deletions(-) -- 2.8.0.rc3.226.g39d4020

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[U-Boot] [PATCH] rockchip: Add support for veyron-minnie (ASUS Chromebook Flip)
by Simon Glass 13 Nov '16

13 Nov '16

This adds support for the Asus Chromebook Flip, an RK3288-based clamshell device which can flip into 'tablet' mode. The device tree file comes from Linux v4.8. The SDRAM parameters are for 4GB Samsung LPDDR3. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3288-veyron-minnie.dts | 301 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +- arch/arm/mach-rockchip/rk3288/Kconfig | 10 + board/google/veyron/Kconfig | 16 ++ board/google/veyron/MAINTAINERS | 7 + configs/chromebook_minnie_defconfig | 82 ++++++++ 7 files changed, 419 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-veyron-minnie.dts create mode 100644 configs/chromebook_minnie_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5723c1b..46329d9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ + rk3288-veyron-minnie.dtb \ rk3288-rock2-square.dtb \ rk3288-evb.dtb \ rk3288-fennec.dtb \ diff --git a/arch/arm/dts/rk3288-veyron-minnie.dts b/arch/arm/dts/rk3288-veyron-minnie.dts new file mode 100644 index 0000000..0a2915f --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-minnie.dts @@ -0,0 +1,301 @@ +/* + * Google Veyron Minnie Rev 0+ board device tree source + * + * Copyright 2015 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" + +/ { + model = "Google Minnie"; + compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3", + "google,veyron-minnie-rev2", "google,veyron-minnie-rev1", + "google,veyron-minnie-rev0", "google,veyron-minnie", + "google,veyron", "rockchip,rk3288"; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + startup-delay-us = <100000>; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; +}; + +&backlight { + /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ + brightness-levels = < + 0 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + power-supply = <&backlight_regulator>; +}; + +&dmc { + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x1>; + rockchip,sdram-params = <0x20d266a4 0x5b6 6 533000000 6 13 0>; +}; + +&emmc { + /delete-property/mmc-hs200-1_8v; +}; + +&gpio_keys { + pinctrl-0 = <&pwr_key_h &ap_lid_int_l &volum_down_l &volum_up_l>; + + volum_down { + label = "Volum_down"; + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <100>; + }; + + volum_up { + label = "Volum_up"; + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <100>; + }; +}; + +&i2c_tunnel { + battery: bq27500@55 { + compatible = "ti,bq27500"; + reg = <0x55>; + }; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int &touch_rst>; + reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + vcc33-supply = <&vcc33_touch>; + vccio-supply = <&vcc33_touch>; + }; +}; + +&panel { + compatible = "auo,b101ean01", "simple-panel"; + power-supply= <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + + regulators { + vcc33_touch: LDO_REG2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v_touch: SWITCH_REG2 { + regulator-name = "vcc5v_touch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdmmc { + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + volum_down_l: volum-down-l { + rockchip,pins = <5 11 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + volum_up_l: volum-up-l { + rockchip,pins = <5 10 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + prochot { + gpio_prochot: gpio-prochot { + rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen { + touch_int: touch-int { + rockchip,pins = <2 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <2 15 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 03ac0b4..930939a 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -65,7 +65,8 @@ u32 spl_boot_device(void) fallback: #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \ - defined(CONFIG_TARGET_CHROMEBIT_MICKEY) + defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \ + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) return BOOT_DEVICE_SPI; #endif return BOOT_DEVICE_MMC1; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 204c1c7..223ae41 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -58,6 +58,16 @@ config TARGET_CHROMEBIT_MICKEY Typically a USB hub or wireless keyboard/touchpad is used to get keyboard and mouse access. +config TARGET_CHROMEBOOK_MINNIE + bool "Google/Rockchip Veyron-Minnie Chromebook" + help + Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0 + ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, + HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS + EC (Cortex-M3) to provide access to the keyboard and battery + functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of + internal MMC. The product name is ASUS Chromebook Flip. + config TARGET_ROCK2 bool "Radxa Rock 2" help diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig index a99190f..770e9aa 100644 --- a/board/google/veyron/Kconfig +++ b/board/google/veyron/Kconfig @@ -29,3 +29,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y endif + +if TARGET_CHROMEBOOK_MINNIE + +config SYS_BOARD + default "veyron" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "veyron" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/veyron/MAINTAINERS b/board/google/veyron/MAINTAINERS index e44e1a9..d582cb0 100644 --- a/board/google/veyron/MAINTAINERS +++ b/board/google/veyron/MAINTAINERS @@ -11,3 +11,10 @@ S: Maintained F: board/google/veyron/ F: include/configs/veyron.h F: configs/chromebit_mickey_defconfig + +CHROMEBIT MINNIE BOARD +M: Simon Glass <sjg(a)chromium.org> +S: Maintained +F: board/google/veyron/ +F: include/configs/veyron.h +F: configs/chromebit_minnie_defconfig diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig new file mode 100644 index 0000000..6aced14 --- /dev/null +++ b/configs/chromebook_minnie_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +# CONFIG_SPL_MMC_SUPPORT is not set +CONFIG_ROCKCHIP_RK3288=y +CONFIG_TARGET_CHROMEBOOK_MINNIE=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie" +CONFIG_SILENT_CONSOLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEYBOARD=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_PWRSEQ=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_RK808=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK808=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_CONSOLE_SCROLL_LINES=10 +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y +CONFIG_SPL_OF_PLATDATA=y +# CONFIG_SPL_OF_LIBFDT is not set -- 2.8.0.rc3.226.g39d4020

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[U-Boot] Please pull: u-boot-video/master
by Anatolij Gustschin 13 Nov '16

13 Nov '16

Hi Tom, The following changes since commit 38cacdab3b5a6d8efd16a4b2620f7ab72144a624: Merge branch 'master' of git://git.denx.de/u-boot-tegra (2016-11-08 10:36:57 -0500) are available in the git repository at: git://git.denx.de/u-boot-video.git master for you to fetch changes up to 9f6ce7defeb3786739bb55eabb9bb20f5b50cd0f: video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabled (2016-11-12 21:03:11 +0100) ---------------------------------------------------------------- Stefan Roese (1): video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabled drivers/video/video_bmp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Please pull. Thanks! Anatolij

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[U-Boot] [PATCH] mx6ull_14x14_evk: Add README file
by Diego Dorta 13 Nov '16

13 Nov '16

Add a README file to help users getting started with the board. Signed-off-by: Diego Dorta <diego.dorta(a)nxp.com> --- board/freescale/mx6ullevk/README | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 board/freescale/mx6ullevk/README diff --git a/board/freescale/mx6ullevk/README b/board/freescale/mx6ullevk/README new file mode 100644 index 0000000..d5c8770 --- /dev/null +++ b/board/freescale/mx6ullevk/README @@ -0,0 +1,36 @@ +How to use U-Boot on Freescale MX6ULL 14x14 EVK +---------------------------------------------- + +- First make sure you have installed the dtc package (device tree compiler): + +$ sudo apt-get install device-tree-compiler + +- Build U-Boot for MX6ULL 14x14 EVK: + +$ make mrproper +$ make mx6ull_14x14_evk_defconfig +$ make + +This generates the u-boot-dtb.imx image in the current directory. + +- Flash the u-boot-dtb.imx image into the micro SD card: + +$ sudo dd if=u-boot-dtb.imx of=/dev/sdb bs=1K seek=1 && sync + +- Jumper settings: + +SW601: 0 0 1 0 +Sw602: 1 0 + +Where 0 means bottom position and 1 means top position (from the switch label +numbers reference). + +Connect the USB cable between the EVK and the PC for the console. +(The USB console connector is the one close the push buttons) + +Insert the micro SD card in the board, power it up and U-Boot messages should +come up. + +The link for the board: http://www.nxp.com/products/microcontrollers-and- \ +processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/ \ +i.mx6qp/evaluation-kit-for-the-i.mx-6ull-applications-processor:MCIMX6ULL-EVK -- 2.7.4

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[U-Boot] [PATCH] davinci: omapl138_lcdk: keep booting even when MAC address is invalid
by Fabien Parent 13 Nov '16

13 Nov '16

If the MAC address specified on the EEPROM is invalid (multicast or zero address), then u-boot fails to boot. Having a bad MAC address in the EEPROM should not prevent the system from booting. This commit changes the error path to just print an error messages in case of bad MAC address. Signed-off-by: Fabien Parent <fparent(a)baylibre.com> --- board/davinci/da8xxevm/omapl138_lcdk.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index 9783b2a..9c1a483 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -333,15 +333,17 @@ int misc_init_r(void) get_mac_addr(addr); } - if (is_multicast_ethaddr(addr) || is_zero_ethaddr(addr)) { + if (!is_multicast_ethaddr(addr) && !is_zero_ethaddr(addr)) { + sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", + addr[0], addr[1], addr[2], addr[3], addr[4], + addr[5]); + + setenv("ethaddr", (char *)tmp); + } else { printf("Invalid MAC address read.\n"); - return -EINVAL; } - sprintf((char *)tmp, "%02x:%02x:%02x:%02x:%02x:%02x", addr[0], - addr[1], addr[2], addr[3], addr[4], addr[5]); - - setenv("ethaddr", (char *)tmp); } + #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII /* Select RMII fucntion through the expander */ if (rmii_hw_init()) -- 2.10.2

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[U-Boot] [PATCH] board: am335x/mux: Do not hang when encountering a bad EEPROM
by Alexandru Gagniuc 13 Nov '16

13 Nov '16

In most cases, the SPL and u-boot.img will be on the same boot media. Since the SPL was loaded by the boot rom, the pinmux will already have been configured for this media. This, the board will still be able to boot successfully, or at least reach the u-boot console, where more recovery options are available. I've encountered this on a beaglebone black with a corrupted EEPROM. Removing this check allowed the board to boot successfully. I've also seen this on EVM-based boards with an unprogrammed EEPROM. On those boards, for some reason there were no UART messages. This made it look as if the SOC was dead. Remove the hang(), as it is not a fatal error. Also reformat the error message to be clearer as to the cause. The original message made it appear as if the wrong binary was being loaded. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- board/ti/am335x/mux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 8afa5f9..ad85b3a 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -397,7 +397,7 @@ void enable_board_pin_mux(void) configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(spi0_pin_mux); } else { - puts("Unknown board, cannot configure pinmux."); - hang(); + /* Unknown board. We might still be able to boot. */ + puts("Bad EEPROM or unknown board, cannot configure pinmux."); } } -- 2.7.4

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[U-Boot] [PATCH 1/3] igep00x0: disable CONFIG_DISPLAY_BOARDINFO
by Ladislav Michl 13 Nov '16

13 Nov '16

As a single U-Boot binary can now run on various board modifications, drop CONFIG_DISPLAY_BOARDINFO as there's no known way to distinguish between them. Also saves few bytes as a bonus. Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- board/isee/igep00x0/igep00x0.c | 18 ------------------ include/configs/omap3_igep00x0.h | 5 +---- 2 files changed, 1 insertion(+), 22 deletions(-) diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 808955e..71688cc 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -27,24 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -const omap3_sysinfo sysinfo = { - DDR_STACKED, -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) - "IGEPv2", -#endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) - "IGEP COM MODULE/ELECTRON", -#endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) - "IGEP COM PROTON", -#endif -#if defined(CONFIG_ENV_IS_IN_ONENAND) - "ONENAND", -#else - "NAND", -#endif -}; - static const struct ns16550_platdata igep_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 1f30710..2ae9737 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -23,11 +23,8 @@ #undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 -/* - * Display CPU and Board information - */ +/* Display CPU information */ #define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_MISC_INIT_R -- 2.1.4

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[U-Boot] [PATCH] ARM: k2g: Update PLL Multiplier and divider values
by Lokesh Vutla 13 Nov '16

13 Nov '16

Only a certain set of PLLM/D values are recommended to configure the DDR at the required speeds for a given clock input frequency. Updating these values as specified in Data Sheet[1] Table 5-18 [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- board/ti/ks2_evm/board_k2g.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c index 8f16845..40edbaa 100644 --- a/board/ti/ks2_evm/board_k2g.c +++ b/board/ti/ks2_evm/board_k2g.c @@ -66,7 +66,7 @@ static struct pll_init_data tetris_pll_config[NUM_SPDS] = { static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; -static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10}; +static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16}; struct pll_init_data *get_pll_init_data(int pll) { -- 2.10.1

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[U-Boot] [PATCH] ARM: keystone2: PLL: Enable glitch free initialization sequence
by Lokesh Vutla 13 Nov '16

13 Nov '16

Update the PLL initialization sequence to avoid glitches while programming. User guide for the same is available at[1]. [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf Signed-off-by: Lokesh Vutla <lokeshvutla(a)ti.com> --- arch/arm/mach-keystone/clock.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index d8804724..68f8980 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -163,15 +163,15 @@ void configure_secondary_pll(const struct pll_init_data *data) { int pllod = data->pll_od - 1; + /* Enable Glitch free bypass for ARM PLL */ + if (cpu_is_k2hk() && data->pll == TETRIS_PLL) + clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); + /* Enable Bypass mode */ setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK); setbits_le32(keystone_pll_regs[data->pll].reg0, CFG_PLLCTL0_BYPASS_MASK); - /* Enable Glitch free bypass for ARM PLL */ - if (cpu_is_k2hk() && data->pll == TETRIS_PLL) - clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); - configure_mult_div(data); /* Program Output Divider */ @@ -189,10 +189,6 @@ void configure_secondary_pll(const struct pll_init_data *data) if (data->pll == PASS_PLL && cpu_is_k2hk()) pll_pa_clk_sel(); - /* Select the Output of ARM PLL as input to ARM */ - if (data->pll == TETRIS_PLL) - setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); - clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK); /* Wait for 500 * REFCLK cucles * (PLLD + 1) */ sdelay(105000); @@ -200,6 +196,10 @@ void configure_secondary_pll(const struct pll_init_data *data) /* Switch to PLL mode */ clrbits_le32(keystone_pll_regs[data->pll].reg0, CFG_PLLCTL0_BYPASS_MASK); + + /* Select the Output of ARM PLL as input to ARM */ + if (cpu_is_k2hk() && data->pll == TETRIS_PLL) + setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN); } void init_pll(const struct pll_init_data *data) -- 2.10.1

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[U-Boot] [PATCH v2 1/2] arm: print the cache config option in hex instead of decimal
by Keerthy 13 Nov '16

13 Nov '16

Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- arch/arm/lib/cache-cp15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 70e94f0..e9f9fc9 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -71,7 +71,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; start = start >> MMU_SECTION_SHIFT; - debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size, + debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option); -- 1.9.1

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