January 2016 - U-Boot

[U-Boot] [PATCH v2 10/13] drivers: gpio: add driver for Microchip PIC32 GPIO controller.
by Purna Chandra Mandal 06 Jan '16

06 Jan '16

PIC32 has ten independently programmable ports and each with multiple pins. These pins can be configured and used as GPIO, if not use by any other peripherals. Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- Changes in v2: None drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 2 +- drivers/gpio/pic32_gpio.c | 164 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 172 insertions(+), 1 deletion(-) create mode 100644 drivers/gpio/pic32_gpio.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e60e9fd..13e9a6a 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -83,4 +83,11 @@ config VYBRID_GPIO help Say yes here to support Vybrid vf610 GPIOs. +config PIC32_GPIO + bool "Microchip PIC32 GPIO driver" + depends on DM_GPIO + default y if MACH_PIC32 + help + Say yes here to support Microchip PIC32 GPIOs. + endmenu diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index fb4fd25..845a6d4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -46,4 +46,4 @@ obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o - +obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o diff --git a/drivers/gpio/pic32_gpio.c b/drivers/gpio/pic32_gpio.c new file mode 100644 index 0000000..69e3620 --- /dev/null +++ b/drivers/gpio/pic32_gpio.c @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2015 Microchip Technology Inc + * Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/compat.h> +#include <dt-bindings/gpio/gpio.h> +#include <mach/pic32.h> + +/* Peripheral Pin Control */ +struct pic32_gpio_regs { + struct pic32_reg_atomic ansel; + struct pic32_reg_atomic tris; + struct pic32_reg_atomic port; + struct pic32_reg_atomic lat; + struct pic32_reg_atomic open_drain; + struct pic32_reg_atomic cnpu; + struct pic32_reg_atomic cnpd; + struct pic32_reg_atomic cncon; +}; + +enum { + MICROCHIP_GPIO_DIR_OUT, + MICROCHIP_GPIO_DIR_IN, + MICROCHIP_GPIOS_PER_BANK = 16, +}; + +struct pic32_gpio_priv { + struct pic32_gpio_regs *regs; + char name[2]; +}; + +static int pic32_gpio_get_value(struct udevice *dev, unsigned offset) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + + return !!(readl(&priv->regs->port.raw) & BIT(offset)); +} + +static int pic32_gpio_set_value(struct udevice *dev, unsigned offset, + int value) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + int mask = BIT(offset); + + if (value) + writel(mask, &priv->regs->port.set); + else + writel(mask, &priv->regs->port.clr); + + return 0; +} + +static int pic32_gpio_direction(struct udevice *dev, unsigned offset) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + + if (readl(&priv->regs->ansel.raw) & BIT(offset)) + return -1; + + if (readl(&priv->regs->tris.raw) & BIT(offset)) + return MICROCHIP_GPIO_DIR_IN; + else + return MICROCHIP_GPIO_DIR_OUT; +} + +static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + int mask = BIT(offset); + + writel(mask, &priv->regs->ansel.clr); + writel(mask, &priv->regs->tris.set); + + return 0; +} + +static int pic32_gpio_direction_output(struct udevice *dev, + unsigned offset, int value) +{ + struct pic32_gpio_priv *priv = dev_get_priv(dev); + int mask = BIT(offset); + + writel(mask, &priv->regs->ansel.clr); + writel(mask, &priv->regs->tris.clr); + + pic32_gpio_set_value(dev, offset, value); + return 0; +} + +static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + desc->offset = args->args[0]; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + +static int pic32_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct pic32_gpio_priv *priv = dev_get_priv(dev); + char *end; + int bank; + + priv->regs = pic32_ioremap(dev_get_addr(dev)); + uc_priv->gpio_count = MICROCHIP_GPIOS_PER_BANK; + end = strrchr(dev->name, '@'); + bank = trailing_strtoln(dev->name, end); + priv->name[0] = 'A' + bank; + uc_priv->bank_name = priv->name; + + return 0; +} + +static int pic32_gpio_get_function(struct udevice *dev, unsigned offset) +{ + int ret = GPIOF_UNUSED; + + switch (pic32_gpio_direction(dev, offset)) { + case MICROCHIP_GPIO_DIR_OUT: + ret = GPIOF_OUTPUT; + break; + case MICROCHIP_GPIO_DIR_IN: + ret = GPIOF_INPUT; + break; + default: + ret = GPIOF_UNUSED; + break; + } + return ret; +} + +static const struct dm_gpio_ops gpio_pic32_ops = { + .direction_input = pic32_gpio_direction_input, + .direction_output = pic32_gpio_direction_output, + .get_value = pic32_gpio_get_value, + .set_value = pic32_gpio_set_value, + .get_function = pic32_gpio_get_function, + .xlate = pic32_gpio_xlate, +}; + +static const struct udevice_id pic32_gpio_ids[] = { + { .compatible = "microchip,pic32mzda-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_pic32) = { + .name = "gpio_pic32", + .id = UCLASS_GPIO, + .of_match = pic32_gpio_ids, + .ops = &gpio_pic32_ops, + .probe = pic32_gpio_probe, + .priv_auto_alloc_size = sizeof(struct pic32_gpio_priv), +}; -- 1.8.3.1

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[U-Boot] [PATCH v2 08/13] drivers: mmc: add driver for Microchip PIC32 SDHCI controller.
by Purna Chandra Mandal 06 Jan '16

06 Jan '16

PIC32 architecture has in-built SDHCI controller. This driver implements platform specific glue to use common SDHCI functionality. Signed-off-by: Andrei Pistirica <andrei.pistirica(a)microchip.com> Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun(a)microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- Changes in v2: - drop SDHCI shared bus configuration (for shared interrupt-and-clock pins) drivers/mmc/Kconfig | 6 +++++ drivers/mmc/Makefile | 2 +- drivers/mmc/pic32_sdhci.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/mmc/sdhci.c | 12 +++++++++ 4 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/pic32_sdhci.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index ceae7bc..0b6f54b 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -31,4 +31,10 @@ config SH_SDHI help Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform +config PIC32_SDHCI + bool "Microchip PIC32 on-chip SDHCI support" + depends on DM_MMC && MACH_PIC32 + help + Support for the on-chip SDHCI support on Microchip PIC32 platforms. + endmenu diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 5d35705..c9c3e3e 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -48,4 +48,4 @@ obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o else obj-$(CONFIG_GENERIC_MMC) += mmc_write.o endif - +obj-$(CONFIG_PIC32_SDHCI) += pic32_sdhci.o diff --git a/drivers/mmc/pic32_sdhci.c b/drivers/mmc/pic32_sdhci.c new file mode 100644 index 0000000..9eb603e --- /dev/null +++ b/drivers/mmc/pic32_sdhci.c @@ -0,0 +1,63 @@ +/* + * Support of SDHCI for Microchip PIC32 SoC. + * + * Copyright (C) 2015 Microchip Technology Inc. + * Andrei Pistirica <andrei.pistirica(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <common.h> +#include <sdhci.h> +#include <asm/errno.h> +#include <mach/pic32.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int pic32_sdhci_probe(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + u32 f_min_max[2]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "clock-freq-min-max", f_min_max, 2); + if (ret) { + printf("sdhci: clock-freq-min-max not found\n"); + return ret; + } + + return add_sdhci(host, f_min_max[1], f_min_max[0]); +} + +static int pic32_sdhci_ofdata_to_platdata(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + fdt_addr_t addr; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + host->name = (char *)dev->name; + host->ioaddr = pic32_ioremap(addr); + host->quirks = SDHCI_QUIRK_NO_HISPD_BIT; + host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); + return 0; +} + +static const struct udevice_id pic32_sdhci_ids[] = { + { .compatible = "microchip,pic32mzda-sdhci" }, + { } +}; + +U_BOOT_DRIVER(pic32_sdhci_drv) = { + .name = "pic32_sdhci", + .id = UCLASS_MMC, + .of_match = pic32_sdhci_ids, + .probe = pic32_sdhci_probe, + .ofdata_to_platdata = pic32_sdhci_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct sdhci_host), +}; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 02d71b9..f32fe67 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -424,6 +424,18 @@ static void sdhci_set_ios(struct mmc *mmc) if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ctrl &= ~SDHCI_CTRL_HISPD; +#if defined(CONFIG_PIC32_SDHCI) + /* + * In PIC32MZ[DA] due to h/w bug SDHCI fails detecting card when JTAG + * is not connected. + * To work-around this problem: + * - set Card_Detect_Signal_Selection bit in SDHCI_Host_Control register + * - clear Card_Detect_Test_Level bit in SDHCI_Host_Control register + */ + ctrl |= SDHCI_CTRL_CD_TEST; + ctrl &= ~SDHCI_CTRL_CD_TEST_INS; +#endif + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); } -- 1.8.3.1

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[U-Boot] [PATCH v2 07/13] board: Add Microchip PIC32MZ[DA]-Starter-Kit board.
by Purna Chandra Mandal 06 Jan '16

06 Jan '16

This adds support for Microchip PIC32MZ[DA] Starter Kit board based on a PIC32MZ[DA] family of microcontroller. Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- Changes in v2: - move CONFIG_SYS_TEXT_BASE (from board/<>/config.mk) to include/configs/<board>.h arch/mips/dts/Makefile | 2 +- arch/mips/dts/pic32mzda_sk.dts | 38 +++++++++++++ arch/mips/mach-pic32/Kconfig | 7 +++ board/microchip/pic32mzda/Kconfig | 13 +++++ board/microchip/pic32mzda/MAINTAINERS | 6 ++ board/microchip/pic32mzda/Makefile | 7 +++ board/microchip/pic32mzda/README | 22 ++++++++ board/microchip/pic32mzda/pic32mzda.c | 31 +++++++++++ configs/pic32mzdask_defconfig | 21 +++++++ include/configs/pic32mzdask.h | 100 ++++++++++++++++++++++++++++++++++ 10 files changed, 246 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/pic32mzda_sk.dts create mode 100644 board/microchip/pic32mzda/Kconfig create mode 100644 board/microchip/pic32mzda/MAINTAINERS create mode 100644 board/microchip/pic32mzda/Makefile create mode 100644 board/microchip/pic32mzda/README create mode 100644 board/microchip/pic32mzda/pic32mzda.c create mode 100644 configs/pic32mzdask_defconfig create mode 100644 include/configs/pic32mzdask.h diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 47b6eb5..b513918 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -2,7 +2,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-y += +dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb targets += $(dtb-y) diff --git a/arch/mips/dts/pic32mzda_sk.dts b/arch/mips/dts/pic32mzda_sk.dts new file mode 100644 index 0000000..99e7f64 --- /dev/null +++ b/arch/mips/dts/pic32mzda_sk.dts @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2015 Purna Chandra Mandal, purna.mandal(a)microchip.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "pic32mzda.dtsi" + +/ { + model = "Microchip PIC32MZDASK"; + compatible = "microchip,pic32mzdask", "microchip,pic32mzda"; + + aliases { + console = &uart2; + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&clock { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&uart2 { + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig index a394791..f357fc6 100644 --- a/arch/mips/mach-pic32/Kconfig +++ b/arch/mips/mach-pic32/Kconfig @@ -26,6 +26,13 @@ endchoice choice prompt "Board select" +config TARGET_PIC32MZDASK + bool "Microchip PIC32MZ[DA] Starter Kit" + depends on SOC_PIC32MZDA + help + This supports Microchip PIC32MZ[DA] Starter Kit. + endchoice +source "board/microchip/pic32mzda/Kconfig" endmenu diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig new file mode 100644 index 0000000..8acb393 --- /dev/null +++ b/board/microchip/pic32mzda/Kconfig @@ -0,0 +1,13 @@ + +if TARGET_PIC32MZDASK + +config SYS_BOARD + default "pic32mzda" + +config SYS_VENDOR + default "microchip" + +config SYS_CONFIG_NAME + default "pic32mzdask" + +endif diff --git a/board/microchip/pic32mzda/MAINTAINERS b/board/microchip/pic32mzda/MAINTAINERS new file mode 100644 index 0000000..c934f1a --- /dev/null +++ b/board/microchip/pic32mzda/MAINTAINERS @@ -0,0 +1,6 @@ +PIC32MZDASK BOARD +M: Purna Chandra Mandal <purna.mandal(a)microchip.com> +S: Maintained +F: board/microchip/pic32mzda/ +F: include/configs/pic32mzdask.h +F: configs/pic32mzdask_defconfig diff --git a/board/microchip/pic32mzda/Makefile b/board/microchip/pic32mzda/Makefile new file mode 100644 index 0000000..3629530 --- /dev/null +++ b/board/microchip/pic32mzda/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 +# Purna Chandra Mandal, purna.mandal(a)microchip.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y := pic32mzda.o diff --git a/board/microchip/pic32mzda/README b/board/microchip/pic32mzda/README new file mode 100644 index 0000000..91d16ab --- /dev/null +++ b/board/microchip/pic32mzda/README @@ -0,0 +1,22 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal(a)microchip.com> + */ + +PIC32MZ[DA] Starter Kit +---------------------------------------- +PIC32MZ[DA] Starter Kit is based on PIC32MZ[DA] family of micro-controller. +This family is powered by MIPS M14KEC 32bit general purpose core and has +advanced microcontroller features and peripherals. + +This processor boots with proprietary stage1 bootloader running from internal +boot-flash. Stage1 bootloader inturns locates and jumps to U-Boot programmed +on internal program-flash. Finally U-Boot loads OS image (along with other +required files for booting) from either uSD card, or ethernet, or from USB +storage. + +To boot Linux following three files are mandatory - uEnv.txt (custom U-Boot +environment file), uImage, *.dtb (platform device-tree-blob file). + +U-Boot jumps to Linux using UHI specification. + +Visit http://microchip.com for details. diff --git a/board/microchip/pic32mzda/pic32mzda.c b/board/microchip/pic32mzda/pic32mzda.c new file mode 100644 index 0000000..afe2ab8 --- /dev/null +++ b/board/microchip/pic32mzda/pic32mzda.c @@ -0,0 +1,31 @@ +/* + * Microchip PIC32MZ[DA] Starter Kit board + * + * Copyright (C) 2015, Microchip Technology Inc. + * Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <mach/pic32.h> + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + ulong rate = 0; + struct udevice *dev; + + printf("Core: %s\n", get_core_name()); + + if (!uclass_get_device(UCLASS_CLK, 0, &dev)) { + rate = clk_get_rate(dev); + printf("CPU Speed: %lu MHz\n", rate / 1000000); + } + + return 0; +} +#endif diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig new file mode 100644 index 0000000..13760e6 --- /dev/null +++ b/configs/pic32mzdask_defconfig @@ -0,0 +1,21 @@ +CONFIG_MIPS=y +CONFIG_MACH_PIC32=y +CONFIG_SOC_PIC32MZDA=y +CONFIG_TARGET_PIC32MZDASK=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_HUSH_PARSER=y +CONFIG_SYS_PROMPT="dask # " +CONFIG_CMD_TIME=y +# CONFIG_CMD_IMLS is not set +CONFIG_SUPPORT_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk" +CONFIG_DM=y +CONFIG_CMD_DM=y +CONFIG_DM_SERIAL=y +CONFIG_PIC32_SERIAL=y +CONFIG_CLK=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_FULL is not set +CONFIG_PIC32_PINCTRL=y diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h new file mode 100644 index 0000000..3624107 --- /dev/null +++ b/include/configs/pic32mzdask.h @@ -0,0 +1,100 @@ +/* + * (c) 2015 Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Microchip PIC32MZ[DA] Starter Kit. + */ + +#ifndef __PIC32MZDASK_CONFIG_H +#define __PIC32MZDASK_CONFIG_H + +/* System Configuration */ +#define CONFIG_SYS_TEXT_BASE 0x9d004000 /* .text */ +#define CONFIG_DISPLAY_BOARDINFO + +/*-------------------------------------------- + * CPU configuration + */ +/* CPU Timer rate */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000 + +/* Cache Configuration */ +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/*---------------------------------------------------------------------- + * Memory Layout + */ +#define CONFIG_SYS_SRAM_BASE 0x80000000 +#define CONFIG_SYS_SRAM_SIZE 0x00080000 /* 512K */ + +/* Initial RAM for temporary stack, global data */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CONFIG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* SDRAM Configuration (for final code, data, stack, heap) */ +#define CONFIG_SYS_SDRAM_BASE 0x88000000 +#define CONFIG_SYS_MALLOC_LEN (256 << 10) +#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) +#define CONFIG_STACKSIZE (4 << 10) /* regular stack */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (192 << 10) + +#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */ +#define CONFIG_SYS_ENV_ADDR 0x88300000 + +/* Memory Test */ +#define CONFIG_SYS_MEMTEST_START 0x88000000 +#define CONFIG_SYS_MEMTEST_END 0x88080000 + +/*---------------------------------------------------------------------- + * Commands + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMD_CLK +#define CONFIG_CMD_MEMTEST +#define CONFIG_CMD_MEMINFO + +/*------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_SYS_NO_FLASH + +/*------------------------------------------------------------ + * Console Configuration + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Handover flattened device tree (dtb file) to Linux kernel + */ +#define CONFIG_OF_LIBFDT 1 + +/* ------------------------------------------------- + * Environment + */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x4000 + +/* --------------------------------------------------------------------- + * Board boot configuration + */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_BOOTDELAY 5 /* autoboot after X seconds */ +#undef CONFIG_BOOTARGS + +#endif /* __PIC32MZDASK_CONFIG_H */ -- 1.8.3.1

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[U-Boot] Pull request: u-boot-spi/next
by Jagan Teki 06 Jan '16

06 Jan '16

Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit 312db9f75f50b339310474d72c8524cef2bd7931: armv7: omap-common: Rework SPL board_mmc_init() (2015-12-14 13:42:54 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 25aade812e40f2e869575199c64e35ebcdf5554b: defconfig: am437x_sk_evm: enable spi driver model (2015-12-29 13:27:46 +0530) ---------------------------------------------------------------- Jagan Teki (24): sf: Get spi locally from spi_flash spi: make mode visible to both dm and non-dm spi: Use mode instead of op_mode_tx spi: Rename SPI_TX_BP|QPP to SPI_TX_BYTE|QUAD sf: Move spi_read_cmds_array locally sf: Rename spi_flash_set_* functions sf: Rename bank_end to bar_end in read_bar sf: Remove spi_flash_remove sf: Minor cleanup sf: Use BIT macro sf: Fix quad bit set for micron devices sf: Read back and check once spansion quad bit set sf: Read back and check once macronix quad bit set sf: Write quad bit along with read status spi: Remove SPI_OPM_RX_EXTN spi: Remove SPI_OPM_RX_DIO|QIOF spi: Rename SPI_OPM_RX_* to SPI_RX_* spi: Rename op_mode_rx to mode_rx spi: Move flags macro's to spi_slave{} members spi: Fix bit assignment with flags spi: Use BIT macro spi: Minor cleanup sf: Make IO modes at last in read modes spi: Add SPI_TX_DUAL mode Mugunthan V N (17): drivers: spi: ti_qspi: do not hard code chip select for memory map configuration drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model conversion drivers: spi: ti_qspi: prepare driver for DM conversion dm: core: Add a new api to get indexed device address spi: Add support for dual and quad mode dra7xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl dts: dra7: add spi alias for qspi drivers: spi: ti_qspi: convert driver to adopt device driver model arm: dts: dra7: add qspi register maps for memory map and control module arm: dts: am437x-gp-evm: add spi-flash comaptible for flash arm: dts: dra7-evm: add spi-flash comaptible for flash arm: dts: dra72-evm: add spi-flash comaptible for flash defconfig: dra72_evm: enable spi driver model defconfig: dra74_evm: enable spi driver model am43xx_evm: qspi: do not define DM_SPI and DM_SPI_FLASH for spl arm: dts: am4372: add qspi register maps for memory map defconfig: am437x_sk_evm: enable spi driver model arch/arm/dts/am4372.dtsi | 5 +- arch/arm/dts/am437x-sk-evm.dts | 2 +- arch/arm/dts/dra7-evm.dts | 2 +- arch/arm/dts/dra7.dtsi | 8 +- arch/arm/dts/dra72-evm.dts | 2 +- configs/am437x_sk_evm_defconfig | 3 + configs/dra72_evm_defconfig | 2 + configs/dra74_evm_defconfig | 2 + drivers/core/device.c | 31 ++- drivers/mtd/spi/sf-uclass.c | 7 +- drivers/mtd/spi/sf_internal.h | 55 +++-- drivers/mtd/spi/sf_probe.c | 2 +- drivers/mtd/spi/spi_flash.c | 185 +++++++++----- drivers/spi/ich.c | 4 +- drivers/spi/spi-uclass.c | 38 ++- drivers/spi/ti_qspi.c | 524 ++++++++++++++++++++++++++++------------ include/configs/am43xx_evm.h | 2 + include/configs/dra7xx_evm.h | 5 + include/dm/device.h | 11 + include/spi.h | 75 +++--- include/spi_flash.h | 2 - 21 files changed, 667 insertions(+), 300 deletions(-)

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[U-Boot] Building SPL version of u-boot (imx6 Sabre Lite)
by Vincent 06 Jan '16

06 Jan '16

Hi, I am currently experimenting with Trustzone on Freescale boards, having Android/Linux in the normal world (NW) and a custom baremetal mini-os in the secure world (SW). My first board was a sabre imx6Q-SDP [1]. In order to boot both OS, we used the mx6sabresd_spl_defconfig configuration (with a few patches to support our system) so the SPL (in Secure mode) loads u-boot/Linux and our OS in memory, gives control to our OS, which at some point makes a switch to NW and start the second u-boot (which will start Linux). I am now trying to port our work to another imx6 board [2] based on a imx6Q-lite, using Boundary Devices clone of u-boot [3]. In this setting, u-boot starts a Linux in the SW. I made a few attempts at patching u-boot to start Linux in NW, but I failed. Since neither in the mainline u-boot nor their patched version provides a "SPL" configuration for the sabre lite, I am looking for a way to build it myself. Is there a roadmap to build a "SPL" configuration from a "normal" configuration in u-boot ? Or is there a way to configure u-boot so that Linux is started in the NW instead of the SW ? Best regards, Vincent [1]: http://www.nxp.com/products/microcontrollers-and-processors/arm-processors/… [2]: https://boundarydevices.com/product/sabre-lite-imx6-sbc/ [3]: https://github.com/boundarydevices/u-boot-imx6 nitrogen6q_defconfig

1 0

[U-Boot] [PATCH 2/2] armv8: ls2085a: Remove phy configuration from QDS and RDB
by Prabhakar Kushwaha 06 Jan '16

06 Jan '16

As phy_connect and phy_config are being called from DPAA2 driver. Remove calling of mentioned function from board file. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- board/freescale/ls2080aqds/eth.c | 25 ------------------- board/freescale/ls2080ardb/eth_ls2080rdb.c | 39 ------------------------------ 2 files changed, 64 deletions(-) diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 0637ecf..5b9c2d1 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -548,12 +548,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 2: /* Slot housing a SGMII riser card? */ @@ -562,12 +556,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT2; bus = mii_dev_for_muxval(EMI1_SLOT2); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 3: break; @@ -606,12 +594,6 @@ serdes2: dpmac_info[dpmac_id].board_mux = EMI1_SLOT4; bus = mii_dev_for_muxval(EMI1_SLOT4); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 5: break; @@ -679,13 +661,6 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - - phy_config(dpmac_info[dpmac_id].phydev); break; case 3: break; diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index db50e4e..58ea746 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -20,42 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; -int load_firmware_cortina(struct phy_device *phy_dev) -{ - if (phy_dev->drv->config) - return phy_dev->drv->config(phy_dev); - - return 0; -} - -void load_phy_firmware(void) -{ - int i; - u8 phy_addr; - struct phy_device *phy_dev; - struct mii_dev *dev; - phy_interface_t interface; - - /*Initialize and upload firmware for all the PHYs*/ - for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) { - interface = wriop_get_enet_if(i); - if (interface == PHY_INTERFACE_MODE_XGMII) { - dev = wriop_get_mdio(i); - phy_addr = wriop_get_phy_address(i); - phy_dev = phy_find_by_mask(dev, 1 << phy_addr, - interface); - if (!phy_dev) { - printf("No phydev for phyaddr %d\n", phy_addr); - continue; - } - - /*Flash firmware for All CS4340 PHYS */ - if (phy_dev->phy_id == PHY_UID_CS4340) - load_firmware_cortina(phy_dev); - } - } -} - int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) @@ -125,9 +89,6 @@ int board_eth_init(bd_t *bis) } } - /* Load CORTINA CS4340 PHY firmware */ - load_phy_firmware(); - cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ -- 1.9.1

1 0

[U-Boot] [PATCH 1/2] driver: net: ldpaa_eth: Add support of PHY framework
by Prabhakar Kushwaha 06 Jan '16

06 Jan '16

This patch integrate DPAA2 ethernet driver existing PHY framework. Call phy_connect and phy_config as per available DPMAC id defined in SerDes Protcol. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- drivers/net/ldpaa_eth/ldpaa_eth.c | 42 ++++++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 69530b1..2e76cc5 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -14,12 +14,29 @@ #include <linux/compat.h> #include <fsl-mc/fsl_dpmac.h> +#include <fsl-mc/ldpaa_wriop.h> #include "ldpaa_eth.h" -#undef CONFIG_PHYLIB static int init_phy(struct eth_device *dev) { - /*TODO for external PHY */ + struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv; + struct phy_device *phydev = NULL; + struct mii_dev *bus; + + bus = wriop_get_mdio(priv->dpmac_id); + if (bus == NULL) + return 0; + + phydev = phy_connect(bus, wriop_get_phy_address(priv->dpmac_id), + dev, wriop_get_enet_if(priv->dpmac_id)); + if (!phydev) { + printf("Failed to connect\n"); + return -1; + } + + priv->phydev = phydev; + + phy_config(phydev); return 0; } @@ -349,7 +366,6 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) } #ifdef CONFIG_PHYLIB - /* TODO Check this path */ err = phy_startup(priv->phydev); if (err) { printf("%s: Could not initialize\n", priv->phydev->dev->name); @@ -367,9 +383,17 @@ static int ldpaa_eth_open(struct eth_device *net_dev, bd_t *bd) return err; } - dpmac_link_state.rate = SPEED_1000; - dpmac_link_state.options = DPMAC_LINK_OPT_AUTONEG; - dpmac_link_state.up = 1; + dpmac_link_state.rate = priv->phydev->speed; + + if (priv->phydev->autoneg == AUTONEG_DISABLE) + dpmac_link_state.options &= ~DPMAC_LINK_OPT_AUTONEG; + else + dpmac_link_state.options |= DPMAC_LINK_OPT_AUTONEG; + + if (priv->phydev->duplex == DUPLEX_HALF) + dpmac_link_state.options |= DPMAC_LINK_OPT_HALF_DUPLEX; + + dpmac_link_state.up = priv->phydev->link; err = dpmac_set_link_state(dflt_mc_io, MC_CMD_NO_FLAGS, priv->dpmac_handle, &dpmac_link_state); if (err < 0) { @@ -798,12 +822,6 @@ static int ldpaa_eth_netdev_init(struct eth_device *net_dev, net_dev->halt = ldpaa_eth_stop; net_dev->send = ldpaa_eth_tx; net_dev->recv = ldpaa_eth_pull_dequeue_rx; -/* - TODO: PHY MDIO information - priv->bus = info->bus; - priv->phyaddr = info->phy_addr; - priv->enet_if = info->enet_if; -*/ if (init_phy(net_dev)) return 0; -- 1.9.1

1 0

[U-Boot] [PATCH v2 04/13] drivers: serial: add driver for Microchip PIC32 UART controller.
by Purna Chandra Mandal 06 Jan '16

06 Jan '16

Signed-off-by: Paul Thacker <paul.thacker(a)microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- Changes in v2: - fix missing or corrupted chars during baud rate change - remove loop until any new char is available in _getc() .../serial/microchip,pic32-uart.txt | 5 + drivers/serial/Kconfig | 13 ++ drivers/serial/Makefile | 1 + drivers/serial/serial_pic32.c | 230 +++++++++++++++++++++ 4 files changed, 249 insertions(+) create mode 100644 doc/device-tree-bindings/serial/microchip,pic32-uart.txt create mode 100644 drivers/serial/serial_pic32.c diff --git a/doc/device-tree-bindings/serial/microchip,pic32-uart.txt b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt new file mode 100644 index 0000000..f00e215 --- /dev/null +++ b/doc/device-tree-bindings/serial/microchip,pic32-uart.txt @@ -0,0 +1,5 @@ +* Microchip PIC32 serial UART + +Required properties: +- compatible: must be "microchip,pic32mzda-uart". +- reg: exactly one register range. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 1fc287e..9763ea1 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -107,6 +107,14 @@ config DEBUG_UART_APBUART will need to provide parameters to make this work. The driver will be available until the real driver model serial is running. +config DEBUG_UART_PIC32 + bool "Microchip PIC32" + help + Select this to enable a debug UART using the serial_pic32 driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver model serial is running. + + endchoice config DEBUG_UART_BASE @@ -223,4 +231,9 @@ config UNIPHIER_SERIAL If you have a UniPhier based board and want to use the on-chip serial ports, say Y to this option. If unsure, say N. +config PIC32_SERIAL + bool "Support for Microchip PIC32 on-chip UART" + help + Support for the UART found on Microchip PIC32 SoC's. + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..57cd38b 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o +obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_pic32.c b/drivers/serial/serial_pic32.c new file mode 100644 index 0000000..3eddb57 --- /dev/null +++ b/drivers/serial/serial_pic32.c @@ -0,0 +1,230 @@ +/* + * (c) 2015 Paul Thacker <paul.thacker(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include <common.h> +#include <config.h> +#include <dm.h> +#include <clk.h> +#include <serial.h> +#include <wait_bit.h> +#include <mach/pic32.h> +#include <dt-bindings/clock/microchip,clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* UART Control Registers */ +#define U_MOD 0x00 +#define U_MODCLR (U_MOD + _CLR_OFFSET) +#define U_MODSET (U_MOD + _SET_OFFSET) +#define U_STA 0x10 +#define U_STACLR (U_STA + _CLR_OFFSET) +#define U_STASET (U_STA + _SET_OFFSET) +#define U_TXR 0x20 +#define U_RXR 0x30 +#define U_BRG 0x40 + +/* U_MOD bits */ +#define UART_ENABLE BIT(15) + +/* U_STA bits */ +#define UART_RX_ENABLE BIT(12) +#define UART_TX_BRK BIT(11) +#define UART_TX_ENABLE BIT(10) +#define UART_TX_FULL BIT(9) +#define UART_TX_EMPTY BIT(8) +#define UART_RX_OERR BIT(1) +#define UART_RX_DATA_AVAIL BIT(0) + +struct pic32_uart_priv { + void __iomem *base; + ulong uartclk; +}; + +static void pic32_serial_setbrg(void __iomem *base, ulong uart_clk, u32 baud) +{ + writel(0, base + U_BRG); + writel((uart_clk / baud / 16) - 1, base + U_BRG); +} + +/* + * Initialize the serial port with the given baudrate. + * The settings are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate) +{ + /* wait for TX FIFO to empty */ + wait_for_bit(__func__, base + U_STA, UART_TX_EMPTY, + true, CONFIG_SYS_HZ, false); + + /* send break */ + writel(UART_TX_BRK, base + U_STASET); + + /* disable and clear mode */ + writel(0, base + U_MOD); + writel(0, base + U_STA); + + /* set baud rate generator */ + pic32_serial_setbrg(base, clk, baudrate); + + /* enable the UART for TX and RX */ + writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET); + + /* enable the UART */ + writel(UART_ENABLE, base + U_MODSET); + return 0; +} + +/* Output a single byte to the serial port */ +static void pic32_serial_putc(void __iomem *base, const char c) +{ + /* if \n, then add a \r */ + if (c == '\n') + pic32_serial_putc(base, '\r'); + + /* Wait for Tx FIFO not full */ + wait_for_bit(__func__, base + U_STA, UART_TX_FULL, + false, CONFIG_SYS_HZ, false); + + /* stuff the tx buffer with the character */ + writel(c, base + U_TXR); +} + +/* Check number of characters in RX fifo */ +static int pic32_serial_tstc(void __iomem *base) +{ + /* check if rx buffer overrun error has occurred */ + if (readl(base + U_STA) & UART_RX_OERR) { + readl(base + U_RXR); + + /* clear OERR to keep receiving */ + writel(UART_RX_OERR, base + U_STACLR); + } + + return readl(base + U_STA) & UART_RX_DATA_AVAIL; +} + +/* + * Read a single byte from rx fifo. + * Blocking: waits until a character is received, then returns. + * Return the character read directly from the UART's receive register. + */ +static int pic32_serial_getc(void __iomem *base) +{ + /* return error until data is available */ + if (!pic32_serial_tstc(base)) + return -EAGAIN; + + /* read the character from rx buffer */ + return readl(base + U_RXR) & 0xff; +} + +static int pic32_uart_pending(struct udevice *dev, bool input) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + if (input) + return pic32_serial_tstc(priv->base); + + return !(readl(priv->base + U_STA) & UART_TX_EMPTY); +} + +static int pic32_uart_setbrg(struct udevice *dev, int baudrate) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_init(priv->base, priv->uartclk, baudrate); + return 0; +} + +static int pic32_uart_putc(struct udevice *dev, const char ch) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_putc(priv->base, ch); + return 0; +} + +static int pic32_uart_getc(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + return pic32_serial_getc(priv->base); +} + +static int pic32_uart_probe(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + + pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); + return 0; +} + +static int pic32_uart_ofdata_to_platdata(struct udevice *dev) +{ + struct pic32_uart_priv *priv = dev_get_platdata(dev); + struct udevice *clkdev; + fdt_addr_t addr; + int ret; + + /* get address */ + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = pic32_ioremap(addr); + + /* get clock rate */ + ret = uclass_get_device(UCLASS_CLK, 0, &clkdev); + if (ret) { + printf("clk class not found, %d\n", ret); + return ret; + } + + priv->uartclk = clk_get_periph_rate(clkdev, PB2CLK); + + return 0; +} + +static const struct dm_serial_ops pic32_uart_ops = { + .putc = pic32_uart_putc, + .pending = pic32_uart_pending, + .getc = pic32_uart_getc, + .setbrg = pic32_uart_setbrg, +}; + +static const struct udevice_id pic32_uart_ids[] = { + { .compatible = "microchip,pic32mzda-uart" }, + {} +}; + +U_BOOT_DRIVER(pic32_serial) = { + .name = "pic32-uart", + .id = UCLASS_SERIAL, + .of_match = pic32_uart_ids, + .probe = pic32_uart_probe, + .ops = &pic32_uart_ops, + .flags = DM_FLAG_PRE_RELOC, + .ofdata_to_platdata = pic32_uart_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct pic32_uart_priv), +}; + +#ifdef CONFIG_DEBUG_UART_PIC32 +#include <debug_uart.h> + +static inline void _debug_uart_init(void) +{ + void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE; + + pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +} + +static inline void _debug_uart_putc(int ch) +{ + writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR); +} + +DEBUG_UART_FUNCS +#endif -- 1.8.3.1

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[U-Boot] [PATCH v2 01/13] MIPS: initial infrastructure for Microchip PIC32 architecture
by Purna Chandra Mandal 06 Jan '16

06 Jan '16

Signed-off-by: Purna Chandra Mandal <purna.mandal(a)microchip.com> --- Changes in v2: - move PIC32 specific headers to arch/mips/mach-pic32/include/mach/ - define register-base as physical address in header file - add trivial ioremap support to convert physical address to MIPS KSEG1 address - drop CONFIG_PIC32_SUPPORTS_FDT_BOOT as not required arch/mips/Kconfig | 6 +++ arch/mips/Makefile | 1 + arch/mips/mach-pic32/Kconfig | 17 +++++++ arch/mips/mach-pic32/Makefile | 7 +++ arch/mips/mach-pic32/cpu.c | 13 +++++ arch/mips/mach-pic32/include/mach/pic32.h | 79 +++++++++++++++++++++++++++++++ 6 files changed, 123 insertions(+) create mode 100644 arch/mips/mach-pic32/Kconfig create mode 100644 arch/mips/mach-pic32/Makefile create mode 100644 arch/mips/mach-pic32/cpu.c create mode 100644 arch/mips/mach-pic32/include/mach/pic32.h diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 388e4c0..4b8174c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -53,6 +53,11 @@ config TARGET_PB1X00 select SYS_MIPS_CACHE_INIT_RAM_LOAD select MIPS_TUNE_4KC +config MACH_PIC32 + bool "Support Microchip PIC32" + select OF_CONTROL + select DM + endchoice source "board/dbau1x00/Kconfig" @@ -60,6 +65,7 @@ source "board/imgtec/malta/Kconfig" source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" +source "arch/mips/mach-pic32/Kconfig" if MIPS diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 90cd590..5c9da3a 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -8,6 +8,7 @@ libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ machine-$(CONFIG_SOC_AU1X00) += au1x00 +machine-$(CONFIG_MACH_PIC32) += pic32 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig new file mode 100644 index 0000000..98b0b88 --- /dev/null +++ b/arch/mips/mach-pic32/Kconfig @@ -0,0 +1,17 @@ +menu "Microchip PIC32 platforms" + depends on MACH_PIC32 + +config SYS_SOC + default "none" + +choice + prompt "PIC32 SoC select" + +endchoice + +choice + prompt "Board select" + +endchoice + +endmenu diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile new file mode 100644 index 0000000..cb42607 --- /dev/null +++ b/arch/mips/mach-pic32/Makefile @@ -0,0 +1,7 @@ +# (C) Copyright 2015 +# Purna Chandra Mandal, purna.mandal(a)microchip.com. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c new file mode 100644 index 0000000..58fd3ab --- /dev/null +++ b/arch/mips/mach-pic32/cpu.c @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2015 + * Purna Chandra Mandal <purna.mandal(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include <common.h> + +phys_size_t initdram(int board_type) +{ + return 0; +} diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h new file mode 100644 index 0000000..f618697 --- /dev/null +++ b/arch/mips/mach-pic32/include/mach/pic32.h @@ -0,0 +1,79 @@ +/* + * (c) 2015 Paul Thacker <paul.thacker(a)microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __PIC32_REGS_H__ +#define __PIC32_REGS_H__ + +#include <asm/io.h> + +/* System Configuration */ +#define PIC32_CFG_BASE 0x1f800000 + +/* System config register offsets */ +#define CFGCON 0x0000 +#define DEVID 0x0020 +#define SYSKEY 0x0030 +#define PMD1 0x0040 +#define PMD7 0x00a0 +#define CFGEBIA 0x00c0 +#define CFGEBIC 0x00d0 +#define CFGPG 0x00e0 +#define CFGMPLL 0x0100 + +/* Non Volatile Memory (NOR flash) */ +#define PIC32_NVM_BASE (PIC32_CFG_BASE + 0x0600) + +/* Oscillator Configuration */ +#define PIC32_OSC_BASE (PIC32_CFG_BASE + 0x1200) + +/* Peripheral Pin Select Input */ +#define PPS_IN_BASE 0x1f801400 +/* Peripheral Pin Select Output */ +#define PPS_OUT_BASE 0x1f801500 +/* Pin Config */ +#define PINCTRL_BASE 0x1f860000 + +/* USB Core */ +#define PIC32_USB_CORE_BASE 0x1f8e3000 +#define PIC32_USB_CTRL_BASE 0x1f884000 + +/* SPI1-SPI6 */ +#define PIC32_SPI1_BASE 0x1f821000 + +/* Prefetch Module */ +#define PREFETCH_BASE 0x1f8e0000 + +/* DDR2 Controller */ +#define PIC32_DDR2C_BASE 0x1f8e8000 + +/* DDR2 PHY */ +#define PIC32_DDR2P_BASE 0x1f8e9100 + +/* EBI */ +#define PIC32_EBI_BASE 0x1f8e1000 + +/* SQI */ +#define PIC32_SQI_BASE 0x1f8e2000 + +struct pic32_reg_atomic { + u32 raw; + u32 clr; + u32 set; + u32 inv; +}; + +#define _CLR_OFFSET 0x04 +#define _SET_OFFSET 0x08 +#define _INV_OFFSET 0x0c + +/* trival alternative of ioremap */ +static inline void __iomem *pic32_ioremap(phys_addr_t addr) +{ + return (void __iomem *)CKSEG1ADDR(addr); +} + +#endif /* __PIC32_REGS_H__ */ -- 1.8.3.1

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[U-Boot] [PATCH v2 0/6] add dma uclass implementation and adopt ti-edma3 to it
by Mugunthan V N 06 Jan '16

06 Jan '16

this patch series enables adds support for dma driver model and to adopt driver model. this has been tested on am437x-sk evms (logs [1]). also pushed a branch for testing [2] [1]: http://pastebin.ubuntu.com/14167595/ [2]: git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dm-dma-v2 changes from initial->v2: * changed config_dm_dma to config_dma. * removed un-wanted enums. * added dma_get_device(). * removed post_bind in uclass driver and added device_probe in dma_get_device() Mugunthan V N (6): dm: implement a DMA uclass dma: Kconfig: Add TI_EDMA3 entry sf: spi_flash: use dma to copy data from mmap region if platform supports spi: ti_qspi: compile out spi_flash_copy_mmap when CONFIG_DMA is defined drivers: dma: ti-edma3: convert driver to adopt driver model defconfig: am437x_sk_evm: enable dma driver model configs/am437x_sk_evm_defconfig | 1 + drivers/dma/Kconfig | 22 +++++++++++ drivers/dma/Makefile | 2 + drivers/dma/dma-uclass.c | 78 +++++++++++++++++++++++++++++++++++++++ drivers/dma/ti-edma3.c | 74 ++++++++++++++++++++++++++++++++++++- drivers/mtd/spi/spi_flash.c | 9 +++++ drivers/spi/ti_qspi.c | 2 +- include/dm/uclass-id.h | 1 + include/dma.h | 81 +++++++++++++++++++++++++++++++++++++++++ 9 files changed, 267 insertions(+), 3 deletions(-) create mode 100644 drivers/dma/dma-uclass.c create mode 100644 include/dma.h -- 2.7.0.rc1.5.gf3adf45

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