January 2016 - U-Boot

[U-Boot] [PATCH 0/3] Add LPDDR3 support for A83T
by Vishnu Patekar 08 Jan '16

08 Jan '16

This adds LPDDR3 support for A83T and support for Banana Pi M3 which has LPDDR3. These patches are based on u-boot-sunxi next branch. These patches tesed on Banana-pi M3. DCDC5 voltage is kept as 1.2V. Vishnu Patekar (3): sunxi: groundwork to support new dram type for A83T sunxi: add support for LPDDR3 for A83T sunxi: Add suport for A83T based Banana-pi M3 Board arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c | 67 +++++++++++++++++++---- arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts | 64 ++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h | 9 ++- board/sunxi/MAINTAINERS | 5 ++ configs/Bananapi_m3_defconfig | 25 +++++++++ 6 files changed, 159 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/sun8i-a83t-bananapi-m3-v1.2.dts create mode 100644 configs/Bananapi_m3_defconfig -- 1.9.1

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[U-Boot] [PATCH 1/3] pci: Add error values definitions from the kernel
by Fabio Estevam 08 Jan '16

08 Jan '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> Add PCI error values definitions from the kernel (include/linux/pci.h). Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- include/pci.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/pci.h b/include/pci.h index 2adca85..0ff3c6e 100644 --- a/include/pci.h +++ b/include/pci.h @@ -451,6 +451,15 @@ #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ +/* Error values that may be returned by PCI functions. */ +#define PCIBIOS_SUCCESSFUL 0x00 +#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 +#define PCIBIOS_BAD_VENDOR_ID 0x83 +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 +#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 +#define PCIBIOS_SET_FAILED 0x88 +#define PCIBIOS_BUFFER_TOO_SMALL 0x89 + /* Include the ID list */ #include <pci_ids.h> -- 1.9.1

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[U-Boot] [PATCH v2] mx6cuboxi: Fix the reset delay for the AR8035 PHY
by Fabio Estevam 07 Jan '16

07 Jan '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> Since commit 59370f3fcd1350 ("net: phy: delay only if reset handler is registered") Ethernet is no longer functional: Booting from net ... FEC Waiting for PHY auto negotiation to complete......... TIMEOUT ! BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 This commit does not have an issue in itself, but it revelead a problem with the Ethernet initialization. As per the AR8035 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and keep the reset low for 10ms. Also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros PHY can be loaded as per Troy Kisky's suggestion. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- Changes since v1: - Fix the issue in a single patch by adding an extra udelay(100) as suggested by Troy. board/solidrun/mx6cuboxi/mx6cuboxi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index fc37f1e..18b08d1 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -143,8 +143,9 @@ static void setup_iomux_enet(void) SETUP_IOMUX_PADS(enet_pads); gpio_direction_output(ETH_PHY_RESET, 0); - mdelay(2); + mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); + udelay(100); } int board_phy_config(struct phy_device *phydev) -- 1.9.1

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[U-Boot] [PATCH] net: Fix delay in net_retry test
by Joe Hershberger 07 Jan '16

07 Jan '16

Introduced in 45b4773 (net/arp: account for ARP delay, avoid duplicate packets on timeout) Check the arp timeout and adjust the timeout start time before the call to eth_recv() so that the sandbox driver has the opportunity to adjust the sandbox timer after the new start time has been recorded. Also, change the adjustment amount by 11 seconds instead of exactly the 10 seconds that the ping timout is expecting since the timeout check is looking for the time elapsed to be greater than but not equal to the specified delay. Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> --- drivers/net/sandbox.c | 2 +- net/net.c | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index 6763a24..d538d37 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -157,7 +157,7 @@ static int sb_eth_recv(struct udevice *dev, int flags, uchar **packetp) struct eth_sandbox_priv *priv = dev_get_priv(dev); if (skip_timeout) { - sandbox_timer_add_offset(10000UL); + sandbox_timer_add_offset(11000UL); skip_timeout = false; } diff --git a/net/net.c b/net/net.c index 4d5746a..fba111e 100644 --- a/net/net.c +++ b/net/net.c @@ -542,6 +542,9 @@ restart: #ifdef CONFIG_SHOW_ACTIVITY show_activity(1); #endif + if (arp_timeout_check() > 0) + time_start = get_timer(0); + /* * Check the ethernet for a new packet. The ethernet * receive routine will process it. @@ -570,10 +573,6 @@ restart: goto done; } - if (arp_timeout_check() > 0) { - time_start = get_timer(0); - } - /* * Check for a timeout, and run the timeout handler * if we have one. -- 2.5.0

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[U-Boot] [PATCH] cgtqmx6eval: README: Fix parameter of 'sf write' command
by Otavio Salvador 07 Jan '16

07 Jan '16

'sf command' should receive the length in sector boundaries, so fix it accordingly. Also, show the steps to set the server and board IP addresses for making the steps clearer. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- board/congatec/cgtqmx6eval/README | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/congatec/cgtqmx6eval/README b/board/congatec/cgtqmx6eval/README index 1d736dc..f2c9599 100644 --- a/board/congatec/cgtqmx6eval/README +++ b/board/congatec/cgtqmx6eval/README @@ -25,11 +25,15 @@ host PC (/tftpboot , for example). => sf probe +=> setenv serverip <server_ip_address> + +=> setenv ipaddr <board_ip_address> + => tftp 0x12000000 SPL => sf erase 0x0 0x10000 -=> sf write 0x12000000 0x400 0x100 +=> sf write 0x12000000 0x400 0x10000 => tftp 0x12000000 u-boot.img -- 1.9.1

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[U-Boot] [PATCH 1/3] arm: mxs: m28evk: Minor tweaks to the default env
by Marek Vasut 07 Jan '16

07 Jan '16

Polish the environment a bit, add two new variables so that the MMC boot and root partitions are not explicitly hard-coded in the env. Use one less if condition in the try_bootscript and handle possible mmc rescan failure there. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- include/configs/m28evk.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 8063a1e..7363b0c 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -165,6 +165,8 @@ "bootscript=boot.scr\0" \ "bootdev=/dev/mmcblk0p2\0" \ "rootdev=/dev/mmcblk0p3\0" \ + "bootpart=0:2\0" \ + "rootpart=0:3\0" \ "netdev=eth0\0" \ "hostname=m28evk\0" \ "rootpath=/opt/eldk-5.5/armv5te/rootfs-qte-sdk\0" \ @@ -229,7 +231,7 @@ "addargs=run addcons addmtd addmisc\0" \ "mmcload=" \ "mmc rescan ; " \ - "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ + "load mmc ${bootpart} ${kernel_addr_r} ${bootfile}\0" \ "ubiload=" \ "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ @@ -271,13 +273,12 @@ "run netload nfsargs addip addargs ; " \ "bootm ${kernel_addr_r}\0" \ "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:2 ${bootscript} ; then " \ - "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ + "if mmc rescan && " \ + "test -e mmc ${bootpart} ${bootscript} && " \ + "load mmc ${bootpart} ${kernel_addr_r} ${bootscript} ; "\ + "then " \ "echo Running bootscript... ; " \ "source ${kernel_addr_r} ; " \ - "fi ; " \ "fi\0" /* The rest of the configuration is shared */ -- 2.1.4

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[U-Boot] [PATCH] fdt: Allow fdt_translate_address() to work with buses
by Simon Glass 07 Jan '16

07 Jan '16

It is common for I2C and SPI buses to have a single-cell address and a size of 0. These produce a warning at present. For example on snow: __of_translate_address: Bad cell count for gpc4 __of_translate_address: Bad cell count for gpx0 __of_translate_address: Bad cell count for gpv2 __of_translate_address: Bad cell count for gpv4 One of the nodes in question looks like this in part: pinctrl_2: pinctrl@10d10000 { #address-cells = <1>; #size-cells = <0>; gpv2: gpv2 { reg = <0x060>; }; gpv4: gpv4 { reg = <0xc0>; }; }; This is clearly valid so it looks like the conversion to use fdt_translate_address() in dev_get_addr() is not currently a good move. Przemyslaw Marczak sent three patches to resolve this for exynos boards: https://patchwork.ozlabs.org/patch/557008/ https://patchwork.ozlabs.org/patch/557010/ https://patchwork.ozlabs.org/patch/557009/ But this involves creating a new function, and everyone will need to know when to use which one. Also the problem may affect other boards. Instead we can relax the contraint that there must be at least one size cell. This fixes the problem on snow and should not affect anything else, since the error check should not fire on normal device trees anyway. After the release we will have more time to come up with a better solution, if one exists. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- common/fdt_support.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 66464db..43c5fa8 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -952,8 +952,7 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 #define OF_BAD_ADDR FDT_ADDR_T_NONE -#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ - (ns) > 0) +#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) /* Debug utility */ #ifdef DEBUG -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] Pull request: u-boot-spi/master
by Jagan Teki 07 Jan '16

07 Jan '16

Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit 78680314c53a95c0bb25e942662979843b60d7b9: Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-12-27 09:15:57 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 8770413f380d07439bc9ad60c6b4d108d5a9adf0: spi: fsl_qspi: fix an error of using GENMASK (2016-01-07 20:29:33 +0530) ---------------------------------------------------------------- Fabio Estevam (1): spi: spi_flash: Fix the arguments of stm_is_locked_sr() Gong Qianyu (1): spi: fsl_qspi: fix an error of using GENMASK drivers/mtd/spi/spi_flash.c | 4 ++-- drivers/spi/fsl_qspi.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)

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[U-Boot] [PATCH] imx_watchdog: always set minimal timeout in reset_cpu
by Andrey Skvortsov 07 Jan '16

07 Jan '16

The problem is that timeout bits in WCR register were leaved unchanged. So previously set timeout value was applied and therefore 'reset' command takes any value up to two minutes, depending on previous watchdog settings, instead of minimal 0.5 seconds. Signed-off-by: Andrey Skvortsov <andrej.skvortzov(a)gmail.com> --- drivers/watchdog/imx_watchdog.c | 2 +- include/fsl_wdog.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 0d77595..f9f8175 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -43,7 +43,7 @@ void reset_cpu(ulong addr) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - clrsetbits_le16(&wdog->wcr, 0, WCR_WDE); + clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); writew(0x5555, &wdog->wsr); writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h index d15a70c..f698d4d 100644 --- a/include/fsl_wdog.h +++ b/include/fsl_wdog.h @@ -16,3 +16,4 @@ struct watchdog_regs { #define WCR_WDT 0x08 #define WCR_SRS 0x10 #define SET_WCR_WT(x) (x << 8) +#define WCR_WT_MSK SET_WCR_WT(0xFF) -- 2.6.4

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[U-Boot] [PATCH V3] imx: mx7: fix the temperature checking for Rev1.1
by Peng Fan 07 Jan '16

07 Jan '16

To TO1.0, we can not rely on finish bit to read temperature. But to TO1.1, the issue was fixed by IC, we can rely on finish bit for temperature reading for TO1.1. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Tim Harvey <tharvey(a)gateworks.com> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: Adrian Alonso <aalonso(a)freescale.com> --- Changes V3: Fix build warning. Changes V2: Discard reading register each time in the while loop for TO1.0. No need to do this. Discard udelay for TO1.1 when reading register. drivers/thermal/imx_thermal.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 09a3c52..6578271 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -130,7 +130,7 @@ static int read_cpu_temperature(struct udevice *dev) #elif defined(CONFIG_MX7) static int read_cpu_temperature(struct udevice *dev) { - unsigned int reg, tmp, start; + unsigned int reg, tmp; unsigned int raw_25c, te1; int temperature; unsigned int *priv = dev_get_priv(dev); @@ -169,18 +169,25 @@ static int read_cpu_temperature(struct udevice *dev) writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); - start = get_timer(0); - /* Wait max 100ms */ - do { + if (soc_rev() >= CHIP_REV_1_1) { + while ((readl(&ccm_anatop->tempsense1) & + TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0) + ; + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } else { /* - * Since we can not rely on finish bit, use 1ms delay to get - * temperature. From RM, 17us is enough to get data, but - * to gurantee to get the data, delay 100ms here. + * Since we can not rely on finish bit, use 10ms + * delay to get temperature. From RM, 17us is + * enough to get data, but to gurantee to get + * the data, delay 10ms here. */ + udelay(10000); reg = readl(&ccm_anatop->tempsense1); tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; - } while (get_timer(0) < (start + 100)); + } writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); -- 2.6.2

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