January 2016 - U-Boot

[U-Boot] [Patch V3] i2c: mxc: add a condition in case the parameter is NULL
by Gong Qianyu 03 Jan '16

03 Jan '16

This could avoid executing the code that only applies to i.MX platforms. The bus_i2c_init() is called before relocation and will assgin value to a static variable. If U-Boot is then still running in a flash device, it's theoretically not allowed to write data to flash without an erasing operation. For i.MX platforms, the U-Boot is always running in DDR. Actually it causes asynchronous error when the ARM64 system error report is enabled and the flash write protect is set. Signed-off-by: Gong Qianyu <Qianyu.Gong(a)freescale.com> --- V3: - Sorry..Remove an unrelated line in other file. drivers/i2c/mxc_i2c.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index fa4c82f..b2d15c9 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -581,8 +581,16 @@ void bus_i2c_init(int index, int speed, int unused, return; } - mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; - mxc_i2c_buses[index].idle_bus_data = idle_bus_data; + /* + * Warning: Be careful to allow the assignment to a static + * variable here. This function could be called while U-Boot is + * still running in flash memory. So such assignment is equal + * to write data to flash without erasing. + */ + if (idle_bus_fn) + mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; + if (idle_bus_data) + mxc_i2c_buses[index].idle_bus_data = idle_bus_data; ret = enable_i2c_clk(1, index); if (ret < 0) { -- 2.1.0.27.g96db324

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[U-Boot] [PATCH v3] ARM: mxs: allow boards to select DC-DC switching clock source
by Michael Heimpold 03 Jan '16

03 Jan '16

For some board designs, it might be useful to switch the DC-DC clock source to something else rather the default 24 MHz, e.g. for EMI reasons. For this, override the mxs_power_setup_dcdc_clocksource function in your board support files. Example: void mxs_power_setup_dcdc_clocksource(void) { mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ); } Signed-off-by: Michael Heimpold <mhei(a)heimpold.de> Cc: Marek Vasut <marex(a)denx.de> Cc: Otavio Salvador <otavio(a)ossystems.com.br> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes in v3: - fixed and improved kerneldoc - renamed mxs_power_select_dcdc_clocksource to mxs_power_switch_dcdc_clocksource to fit the comment Changes in v2: - use a weak function approach instead of ifdef'ery as suggested by Marek Vasut arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 34 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mxs/sys_proto.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 1972de8..1ec8e2b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -248,6 +248,39 @@ static void mxs_power_setup_5v_detect(void) } /** + * mxs_power_switch_dcdc_clocksource() - Switch PLL clock for DC-DC converters + * @freqsel: One of the POWER_MISC_FREQSEL_xxx defines to select the clock + * + * This function configures and then enables an alternative PLL clock source + * for the DC-DC converters. + */ +void mxs_power_switch_dcdc_clocksource(uint32_t freqsel) +{ + struct mxs_power_regs *power_regs = + (struct mxs_power_regs *)MXS_POWER_BASE; + + /* Select clocksource for DC-DC converters */ + clrsetbits_le32(&power_regs->hw_power_misc, + POWER_MISC_FREQSEL_MASK, + freqsel); + setbits_le32(&power_regs->hw_power_misc, + POWER_MISC_SEL_PLLCLK); +} + +/** + * mxs_power_setup_dcdc_clocksource() - Setup PLL clock source for DC-DC converters + * + * Normally, there is no need to switch DC-DC clocksource. This is the reason, + * why this function is a stub and does nothing. However, boards can implement + * this function when required and call mxs_power_switch_dcdc_clocksource() to + * switch to an alternative clock source. + */ +__weak void mxs_power_setup_dcdc_clocksource(void) +{ + debug("SPL: Using default DC-DC clocksource\n"); +} + +/** * mxs_src_power_init() - Preconfigure the power block * * This function configures reasonable values for the DC-DC control loop @@ -872,6 +905,7 @@ static void mxs_power_configure_power_source(void) debug("SPL: Configuring power source\n"); + mxs_power_setup_dcdc_clocksource(); mxs_src_power_init(); if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 20ff101..f2b075e 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -25,6 +25,8 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, const iomux_cfg_t *iomux_setup, const unsigned int iomux_size); + +void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); #endif struct mxs_pair { -- 2.5.0

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[U-Boot] [PATCH] cgtqmx6eval: fix pad configuration for SPI bus
by Michael Schanz 03 Jan '16

03 Jan '16

Use the macro SETUP_IOMUX_PAD(...) rather than imx_iomux_v3_setup_multiple_pads(...) in order to setup the pin configuration for ECSPI1. ARRAY_SIZE(pads) provides the wrong size for imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)) in case of MX6QDL. In the particular case, the content of GPR12 is overwritten and the IPG/AHB/ATB/ATP clocks are deactivated. Therefore, the connection to the system via JTAG is not possible anymore. Furthermore, kernel version 3.0.35 hangs during bootprocess in the function etm_init(). Signed-off-by: Michael Schanz <michael.schanz(a)congatec.com> --- board/congatec/cgtqmx6eval/cgtqmx6eval.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 5fd526d..225de7c 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -404,7 +404,7 @@ static void setup_iomux_uart(void) #ifdef CONFIG_MXC_SPI static void setup_spi(void) { - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + SETUP_IOMUX_PADS(ecspi1_pads); gpio_direction_output(IMX_GPIO_NR(3, 19), 0); } #endif -- 1.9.1

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[U-Boot] [PATCH 1/2] net: fec_mxc: configure MDIO hold time
by Mans Rullgard 03 Jan '16

03 Jan '16

If the host clock frequency is higher than 100 MHz, the MDIO hold time needs to be increased from its current setting of one cycle in order to meet the specified minium of 10 ns. Writing an appropriate value to the HOLDTIME field of the MII_SPEED register achieves this. Comment copied from Linux kernel. Signed-off-by: Mans Rullgard <mans(a)mansr.com> --- drivers/net/fec_mxc.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 79f6737..1250d2a 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -131,13 +131,25 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. + * + * The i.MX28 and i.MX6 types have another filed in the MSCR (aka + * MII_SPEED) register that defines the MDIO output hold time. Earlier + * versions are RAZ there, so just ignore the difference and write the + * register always. + * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. + * HOLDTIME + 1 is the number of clk cycles the fec is holding the + * output. + * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). + * Given that ceil(clkrate / 5000000) <= 64, the calculation for + * holdtime cannot result in a value greater than 3. */ - register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); + u32 pclk = imx_get_fecclk(); + u32 speed = DIV_ROUND_UP(pclk, 5000000); + u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; #ifdef FEC_QUIRK_ENET_MAC speed--; #endif - speed <<= 1; - writel(speed, &eth->mii_speed); + writel(speed << 1 | hold << 8, &eth->mii_speed); debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed)); } -- 2.6.3

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[U-Boot] [PATCH] serial_mxc: Fix setup of UARTx_UFCR register
by Maximilian Schwerin 03 Jan '16

03 Jan '16

This patch writes the default values for TXTL and RXTL to UARTx_UFCR. Without this patch some older kernel versions crash as UARTx_UFCR was not always correctly initialized. Signed-off-by: Maximilian Schwerin <maximilian.schwerin(a)tigris.de> --- drivers/serial/serial_mxc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index d6cf1d8..51485c0 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -75,6 +75,7 @@ #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ @@ -135,6 +136,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define TXTL 2 /* reset default */ +#define RXTL 1 /* reset default */ +#define RFDIV 4 /* divide input clock by 2 */ + static void mxc_serial_setbrg(void) { u32 clk = imx_get_uartclk(); @@ -142,7 +147,9 @@ static void mxc_serial_setbrg(void) if (!gd->baudrate) gd->baudrate = CONFIG_BAUDRATE; - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF) + | (TXTL << UFCR_TXTL_SHF) + | (RXTL << UFCR_RXTL_SHF); __REG(UART_PHYS + UBIR) = 0xf; __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); -- 1.9.1

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[U-Boot] [PATCH 0/4] igep00x0: Minor cleanups
by Ladislav Michl 03 Jan '16

03 Jan '16

This patch serie was created as a side product while working on UBIizing NAND flash space to improve system reliability. It is safe to apply for current release to start with clean land for adding new features. Ladislav Michl (4): igep00x0: Cleanup ethernet support igep00x0: Do not include config_distro_defaults.h igep00x0: Fix config header indentation igep00x0: Remove no-op macros from config header board/isee/igep00x0/igep00x0.c | 33 +++++++++++++++++++-------------- include/configs/omap3_igep00x0.h | 13 +++---------- 2 files changed, 22 insertions(+), 24 deletions(-)

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[U-Boot] [PATCH 1/4] igep00x0: Cleanup ethernet support
by Ladislav Michl 03 Jan '16

03 Jan '16

- move chip reset to separate function - use CONFIG_SMC911X_BASE instead of hardcoded value - remove unneeded local variable from board_eth_init. Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- board/isee/igep00x0/igep00x0.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 57b89e0..e2fce50 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -101,6 +101,19 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) #endif #if defined(CONFIG_CMD_NET) + +static void reset_net_chip(int gpio) +{ + if (!gpio_request(gpio, "eth nrst")) { + gpio_direction_output(gpio, 1); + udelay(1); + gpio_set_value(gpio, 0); + udelay(40); + gpio_set_value(gpio, 1); + mdelay(10); + } +} + /* * Routine: setup_net_chip * Description: Setting up the configuration GPMC registers specific to the @@ -110,8 +123,8 @@ static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; - enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, - GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); @@ -121,15 +134,7 @@ static void setup_net_chip(void) writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, &ctrl_base->gpmc_nadv_ale); - /* Make GPIO 64 as output pin and send a magic pulse through it */ - if (!gpio_request(64, "")) { - gpio_direction_output(64, 0); - gpio_set_value(64, 1); - udelay(1); - gpio_set_value(64, 0); - udelay(1); - gpio_set_value(64, 1); - } + reset_net_chip(64); } #else static inline void setup_net_chip(void) {} @@ -200,10 +205,10 @@ void set_muxconf_regs(void) #if defined(CONFIG_CMD_NET) int board_eth_init(bd_t *bis) { - int rc = 0; #ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#else + return 0; #endif - return rc; } #endif -- 2.1.4

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[U-Boot] [PATCH] igep00x0: Do not include config_distro_defaults.h directly
by Ladislav Michl 02 Jan '16

02 Jan '16

File is already included: omap3_igep00x0.h -> ti_omap3_common.h -> ti_armv7_omap.h -> ti_armv7_common.h -> config_distro_defaults.h Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> --- include/configs/omap3_igep00x0.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index cf2bc3e..a64b38f 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -43,7 +43,7 @@ #else #error "status LED not defined for this machine." #endif -#define RED_LED_DEV 0 +#define RED_LED_DEV 0 #define STATUS_LED_BIT RED_LED_GPIO #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) @@ -56,7 +56,7 @@ #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ /* USB */ -#define CONFIG_USB_MUSB_UDC 1 +#define CONFIG_USB_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 #define CONFIG_TWL4030_USB 1 @@ -81,12 +81,8 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING -/*#undef CONFIG_ENV_IS_NOWHERE*/ - #ifndef CONFIG_SPL_BUILD -#include <config_distro_defaults.h> - /* Environment */ #define ENV_DEVICE_SETTINGS \ "stdin=serial\0" \ @@ -138,7 +134,7 @@ #if defined(CONFIG_CMD_NET) #define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 +#define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ /* OneNAND boot config */ -- 2.1.4

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[U-Boot] Why is there no MEMORY { } part in u-boot.lds?
by Henry Choi 01 Jan '16

01 Jan '16

Dear U-Booters, First of all, I did not search the U-Boot mailing list archive with my question, because I did not see a way to do this on the U-Boot mailing list page <http://lists.denx.de/mailman/listinfo/u-boot>. I did search Google for "MEMORY u-boot.lds memcpy" but nothing obvious turned up. So please pardon me if this was explained before. Hopefully, you can just give me a link that explains everything. I have been compiling and running u-boot on the Emcraft stm32f7-som board (MCU is ARM Cortex M7). Their U-boot forked off the mainline 6+ years ago, so I tried to port the latest mainline, to teach myself u-boot. The most obvious difference I can see is the relocation code, but I do not think that explains my current problem, which is that my global variable(s) were placed in on-chip flash (where text is). In the working code (again, forked off 6+ years ago), _start() explicitly copies the .data and .bss section from the flash to SRAM, and zeroes out .bss in RAM. But I have not run into such code while single-stepping through in the debugger. The readelf -S shows that the .bss in the flash, whereas it was in the RAM. Even when I looked at the stm32f429-discovery port in the mainline, I could NOT understand why the "MEMORY" part is no longer in arch/arm/cpu/u-boot.lds. In u-boot.lds, there is a suggestion to read arch/arm/lib/bss.c--which seems to be missing in the mainline. I don't know what the OVERLAY keyword is doing for the .bss, and hope that I just need to read 1 key document to understand how this is supposed to work. Thank you very much for reading, and your understanding. w/ regards, Henry

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[U-Boot] U-boot running BBT create code in every reset
by Madhur Wani 01 Jan '16

01 Jan '16

Hi, Our board is based on Freescale P2041RDB. We're using same nand chip as that of the RDB. However we're facing a problem during nand erase/write/read command. On every reset when we issue these commands u-boot can't find bbt and it starts to create it. Only difference between P2041RDB & our board is we've lowered down the eLBC clock frequency. BBT will be created every time or just once? What if we remove NAND_BBT_CREATE option from bbt_main_descr & bbt_mirror_descr? Thanks, Madhur.

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