January 2016 - U-Boot

[U-Boot] [PATCH] fsl/ddr: Add workaround for ERRATUM_A00994
by Shengzhou Liu 06 Jan '16

06 Jan '16

During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 + drivers/ddr/fsl/fsl_ddr_gen4.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 49b113d..83a207c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -118,6 +118,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 #define CONFIG_SYS_FSL_ERRATUM_A009635 +#define CONFIG_SYS_FSL_ERRATUM_A009942 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3fca5c2..0d9dd0b 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -55,6 +55,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */ u32 *vref_seq = vref_seq1; #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ulong ddr_freq; + u32 tmp; +#endif #ifdef CONFIG_FSL_DDR_BIST u32 mtcr, err_detect, err_sbe; u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config; @@ -227,6 +231,20 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->debug[25], 0x9000); } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A009942 + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; + tmp = ddr_in32(&ddr->debug[28]); + if (ddr_freq <= 1333) + ddr_out32(&ddr->debug[28], tmp | 0x0080006a); + else if (ddr_freq <= 1600) + ddr_out32(&ddr->debug[28], tmp | 0x0070006f); + else if (ddr_freq <= 1867) + ddr_out32(&ddr->debug[28], tmp | 0x00700076); + else if (ddr_freq <= 2133) + ddr_out32(&ddr->debug[28], tmp | 0x0060007b); +#endif + /* * For RDIMMs, JEDEC spec requires clocks to be stable before reset is * deasserted. Clocks start when any chip select is enabled and clock -- 2.1.0.27.g96db324

1 0

[U-Boot] [PATCH v3 2/4] mips: ath79: add serial driver for ar933x SOC
by Wills Wang 06 Jan '16

06 Jan '16

Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v3: None Changes in v2: None drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 274 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 275 insertions(+) create mode 100644 drivers/serial/serial_ar933x.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dd87147..9a7ad89 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -17,6 +17,7 @@ endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o +obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o obj-$(CONFIG_ARM_DCC) += arm_dcc.o obj-$(CONFIG_ATMEL_USART) += atmel_usart.o obj-$(CONFIG_EFI_APP) += serial_efi.o diff --git a/drivers/serial/serial_ar933x.c b/drivers/serial/serial_ar933x.c new file mode 100644 index 0000000..6c0d726 --- /dev/null +++ b/drivers/serial/serial_ar933x.c @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2015 + * Wills Wang, <wills.wang(a)live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <serial.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ar71xx_regs.h> +#include <asm/arch/ar933x_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct ar933x_serial_baudrate{ + u32 baudrate; + u32 scale; + u32 step; +}; + +const struct ar933x_serial_baudrate baudrate_table_40mhz[] = { +/* baudrate, scale, step */ + {600, 255, 503}, + {1200, 249, 983}, + {2400, 167, 1321}, + {4800, 87, 1384}, + {9600, 45, 1447}, + {14400, 53, 2548}, + {19200, 22, 1447}, + {28800, 26, 2548}, + {38400, 28, 3649}, + {56000, 7, 1468}, + {57600, 34, 6606}, + {115200, 28, 10947}, + {128000, 6, 2936}, + {153600, 18, 9563}, + {230400, 16, 12834}, + {250000, 4, 4096}, + {256000, 6, 5872}, + {460800, 7, 12079}, + {576000, 4, 9437}, + {921600, 3, 12079}, + {1000000, 2, 9830}, + {1152000, 2, 11324}, + {1500000, 0, 4915}, + {2000000, 0, 6553}, + }; + +const struct ar933x_serial_baudrate baudrate_table_25mhz[] = { +/* baudrate, scale, step */ + {600, 255, 805}, + {1200, 209, 1321}, + {2400, 104, 1321}, + {4800, 54, 1384}, + {9600, 78, 3976}, + {14400, 98, 7474}, + {19200, 55, 5637}, + {28800, 77, 11777}, + {38400, 36, 7449}, + {56000, 4, 1468}, + {57600, 35, 10871}, + {115200, 20, 12683}, + {128000, 11, 8053}, + {153600, 9, 8053}, + {230400, 9, 12079}, + {250000, 6, 9175}, + {256000, 5, 8053}, + {460800, 4, 12079}, + {576000, 3, 12079}, + {921600, 1, 9663}, + {1000000, 1, 10485}, + {1152000, 1, 12079}, + {1500000, 0, 7864}, + {2000000, 0, 10485}, +}; + +static inline u32 ar933x_read(u32 base, u32 offset) +{ + return readl(KSEG1ADDR(base + offset)); +} + +static inline void ar933x_write(u32 base, u32 offset, u32 val) +{ + writel(val, KSEG1ADDR(base + offset)); +} + +static int ar933x_serial_init(void) +{ + u32 val; + + /* + * Set GPIO10 (UART_SO) as output and enable UART, + * BIT(15) in GPIO_FUNCTION_1 register must be written with 1 + */ + val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE); + val |= BIT(10); + ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val); + + val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC); + val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15)); + ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val); + + /* + * UART controller configuration: + * - no DMA + * - no interrupt + * - DCE mode + * - no flow control + * - set RX ready oride + * - set TX ready oride + */ + val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE + | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S); + ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val); + return 0; +} + +#ifdef CONFIG_DM_SERIAL +static int ar933x_serial_setbrg(struct udevice *dev, int baudrate) +{ +#else +static void ar933x_serial_setbrg(void) +{ + int baudrate = gd->baudrate; +#endif + u32 val, scale, step; + const struct ar933x_serial_baudrate *baudrate_table; + int i, baudrate_table_size; + + val = ar933x_read(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP); + if (val & AR933X_BOOTSTRAP_REF_CLK_40) { + baudrate_table = baudrate_table_40mhz; + baudrate_table_size = ARRAY_SIZE(baudrate_table_40mhz); + scale = (40000000 / (16 * baudrate)) - 1; + step = 8192; + } else { + baudrate_table = baudrate_table_25mhz; + baudrate_table_size = ARRAY_SIZE(baudrate_table_25mhz); + scale = (25000000 / (16 * baudrate)) - 1; + step = 8192; + } + + for (i = 0; i < baudrate_table_size; i++) { + if (baudrate_table[i].baudrate == gd->baudrate) { + scale = baudrate_table[i].scale; + step = baudrate_table[i].step; + } + } + + val = ((scale & AR933X_UART_CLOCK_SCALE_M) + << AR933X_UART_CLOCK_SCALE_S); + val |= ((step & AR933X_UART_CLOCK_STEP_M) + << AR933X_UART_CLOCK_STEP_S); + ar933x_write(AR933X_UART_BASE, AR933X_UART_CLOCK_REG, val); +#ifdef CONFIG_DM_SERIAL + return 0; +#endif +} + +#ifdef CONFIG_DM_SERIAL +static int ar933x_serial_putc(struct udevice *dev, const char c) +#else +static void ar933x_serial_putc(const char c) +#endif +{ + u32 data; + + if (c == '\n') +#ifdef CONFIG_DM_SERIAL + ar933x_serial_putc(dev, '\r'); +#else + ar933x_serial_putc('\r'); +#endif + do { + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_TX_CSR)); + + data = (u32)c | AR933X_UART_DATA_TX_CSR; + ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, data); +#ifdef CONFIG_DM_SERIAL + return 0; +#endif +} + +#ifdef CONFIG_DM_SERIAL +static int ar933x_serial_getc(struct udevice *dev) +#else +static int ar933x_serial_getc(void) +#endif +{ + u32 data; + + do { + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + } while (!(data & AR933X_UART_DATA_RX_CSR)); + + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR); + return data & AR933X_UART_DATA_TX_RX_MASK; +} + +#ifdef CONFIG_DM_SERIAL +static int ar933x_serial_pending(struct udevice *dev, bool input) +{ + u32 data; + + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + if (input) + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0; + else + return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1; +} + +static int ar933x_serial_probe(struct udevice *dev) +{ + ar933x_serial_init(); + return 0; +} + +static const struct dm_serial_ops ar933x_serial_ops = { + .putc = ar933x_serial_putc, + .pending = ar933x_serial_pending, + .getc = ar933x_serial_getc, + .setbrg = ar933x_serial_setbrg, +}; + +static const struct udevice_id ar933x_serial_ids[] = { + { .compatible = "ath79,ar933x-uart" }, + { } +}; + +U_BOOT_DRIVER(serial_ar933x) = { + .name = "serial_ar933x", + .id = UCLASS_SERIAL, + .of_match = ar933x_serial_ids, + .probe = ar933x_serial_probe, + .ops = &ar933x_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; +#else +static int ar933x_serial_tstc(void) +{ + u32 data; + + data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG); + return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0; +} + +static struct serial_device ar933x_serial_drv = { + .name = "ar933x_serial", + .start = ar933x_serial_init, + .stop = NULL, + .setbrg = ar933x_serial_setbrg, + .putc = ar933x_serial_putc, + .puts = default_serial_puts, + .getc = ar933x_serial_getc, + .tstc = ar933x_serial_tstc, +}; + +void ar933x_serial_initialize(void) +{ + serial_register(&ar933x_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &ar933x_serial_drv; +} +#endif -- 1.9.1

3 6

[U-Boot] [PATCH v6 07/10] ns16550: map register base address for debug UART
by Wills Wang 06 Jan '16

06 Jan '16

MIPS need to use KSEG1 address for register operation, this patch add map_physmem to convert CONFIG_DEBUG_UART_BASE for debug UART. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None drivers/serial/ns16550.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 3b24af0..1e2538e 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -270,7 +270,8 @@ int NS16550_tstc(NS16550_t com_port) static inline void _debug_uart_init(void) { - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; + struct NS16550 *com_port = (struct NS16550 *)map_physmem( + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE); int baud_divisor; /* @@ -293,7 +294,8 @@ static inline void _debug_uart_init(void) static inline void _debug_uart_putc(int ch) { - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; + struct NS16550 *com_port = (struct NS16550 *)map_physmem( + CONFIG_DEBUG_UART_BASE, 0, MAP_NOCACHE); while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) ; -- 1.9.1

3 4

[U-Boot] [PATCH 1/2] imx: mx6: add more entry for mxc_ccm_reg
by Peng Fan 06 Jan '16

06 Jan '16

Add more entries for structure mxc_ccm_reg. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/include/asm/arch-mx6/crm_regs.h | 87 ++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 13e0a3d..787eb68 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -103,6 +103,93 @@ struct mxc_ccm_reg { u32 analog_pfd_528_set; u32 analog_pfd_528_clr; u32 analog_pfd_528_tog; + u32 reg_1p1; + u32 reg_1p1_set; + u32 reg_1p1_clr; + u32 reg_1p1_tog; + u32 reg_3p0; + u32 reg_3p0_set; + u32 reg_3p0_clr; + u32 reg_3p0_tog; + u32 reg_2p5; + u32 reg_2p5_set; + u32 reg_2p5_clr; + u32 reg_2p5_tog; + u32 reg_core; + u32 reg_core_set; + u32 reg_core_clr; + u32 reg_core_tog; + u32 ana_misc0; + u32 ana_misc0_set; + u32 ana_misc0_clr; + u32 ana_misc0_tog; + u32 ana_misc1; + u32 ana_misc1_set; + u32 ana_misc1_clr; + u32 ana_misc1_tog; + u32 ana_misc2; + u32 ana_misc2_set; + u32 ana_misc2_clr; + u32 ana_misc2_tog; + u32 tempsense0; + u32 tempsense0_set; + u32 tempsense0_clr; + u32 tempsense0_tog; + u32 tempsense1; + u32 tempsense1_set; + u32 tempsense1_clr; + u32 tempsense1_tog; + u32 usb1_vbus_detect; + u32 usb1_vbus_detect_set; + u32 usb1_vbus_detect_clr; + u32 usb1_vbus_detect_tog; + u32 usb1_chrg_detect; + u32 usb1_chrg_detect_set; + u32 usb1_chrg_detect_clr; + u32 usb1_chrg_detect_tog; + u32 usb1_vbus_det_stat; + u32 usb1_vbus_det_stat_set; + u32 usb1_vbus_det_stat_clr; + u32 usb1_vbus_det_stat_tog; + u32 usb1_chrg_det_stat; + u32 usb1_chrg_det_stat_set; + u32 usb1_chrg_det_stat_clr; + u32 usb1_chrg_det_stat_tog; + u32 usb1_loopback; + u32 usb1_loopback_set; + u32 usb1_loopback_clr; + u32 usb1_loopback_tog; + u32 usb1_misc; + u32 usb1_misc_set; + u32 usb1_misc_clr; + u32 usb1_misc_tog; + u32 usb2_vbus_detect; + u32 usb2_vbus_detect_set; + u32 usb2_vbus_detect_clr; + u32 usb2_vbus_detect_tog; + u32 usb2_chrg_detect; + u32 usb2_chrg_detect_set; + u32 usb2_chrg_detect_clr; + u32 usb2_chrg_detect_tog; + u32 usb2_vbus_det_stat; + u32 usb2_vbus_det_stat_set; + u32 usb2_vbus_det_stat_clr; + u32 usb2_vbus_det_stat_tog; + u32 usb2_chrg_det_stat; + u32 usb2_chrg_det_stat_set; + u32 usb2_chrg_det_stat_clr; + u32 usb2_chrg_det_stat_tog; + u32 usb2_loopback; + u32 usb2_loopback_set; + u32 usb2_loopback_clr; + u32 usb2_loopback_tog; + u32 usb2_misc; + u32 usb2_misc_set; + u32 usb2_misc_clr; + u32 usb2_misc_tog; + u32 digprog; + u32 reserved1[7]; + u32 digprog_sololite; }; #endif -- 2.6.2

2 5

[U-Boot] [PATCH] powerpc: p1_p2_rdb_pc: rename to P2020RDB_PC
by Bryan Hundven 05 Jan '16

05 Jan '16

As I work to re-add p1_p2_rdb, CONFIG_P2020RDB conflicts with p1_p2_rdb's CONFIG_P2020RDB. Rename p1_p2_rdb_pc's CONFIG_P2020RDB to CONFIG_P2020RDB_PC. Signed-off-by: Bryan Hundven <bryanhundven(a)gmail.com> Cc: Andy Fleming <afleming(a)freescale.com> Cc: York Sun <yorksun(a)freescale.com> --- board/freescale/p1_p2_rdb_pc/ddr.c | 2 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_36BIT_defconfig | 2 +- configs/P2020RDB-PC_NAND_defconfig | 2 +- configs/P2020RDB-PC_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_defconfig | 2 +- include/configs/p1_p2_rdb_pc.h | 8 ++++---- 10 files changed, 13 insertions(+), 13 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 946d503..ef59b58 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -49,7 +49,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_P2020RDB) +#elif defined(CONFIG_P2020RDB_PC) /* Micron MT41J128M16_15E */ dimm_params_t ddr_raw_timing = { .n_ranks = 1, diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 578bfc5..c7bb971 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -3,7 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,NAND" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 19c795a..c79399e 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SDCARD" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index bdc5e43..898993f 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index b9d4a47..16af720 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,36BIT" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index ea9f830..19ec9d2 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -3,7 +3,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_TPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,NAND" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 997887d..ee0fd33 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SDCARD" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index e547ea4..40190c4 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC,SPIFLASH" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index fdad880..6629285 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -1,7 +1,7 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y -CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" +CONFIG_SYS_EXTRA_OPTIONS="P2020RDB_PC" CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_NETDEVICES=y diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 60bedaa..e64805a 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -154,7 +154,7 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_P2020RDB_PC) #define CONFIG_BOARDNAME "P2020RDB-PCA" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P2020 @@ -323,7 +323,7 @@ #define CONFIG_LIBATA #define CONFIG_LBA48 -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_P2020RDB_PC) #define CONFIG_SYS_CLK_FREQ 100000000 #else #define CONFIG_SYS_CLK_FREQ 66666666 @@ -382,7 +382,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifndef CONFIG_P2020RDB +#ifndef CONFIG_P2020RDB_PC #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -618,7 +618,7 @@ #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_P2020RDB_PC) #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) #else #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) -- 2.5.0

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Re: [U-Boot] Please pull u-boot-mpc85xx master
by York Sun 05 Jan '16

05 Jan '16

+list On 01/05/2016 09:22 AM, York Sun wrote: > Tom, > > The following changes since commit 78680314c53a95c0bb25e942662979843b60d7b9: > > Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-12-27 09:15:57 > -0500) > > are available in the git repository at: > > > git://git.denx.de/u-boot-mpc85xx.git master > > for you to fetch changes up to 6a655d8e34e044e1030f88a611c890a50c9be413: > > powerpc, mpc5xxx: fix missing bootflag init (2016-01-05 08:33:44 -0800) > > ---------------------------------------------------------------- > Heiko Schocher (1): > powerpc, mpc5xxx: fix missing bootflag init > > arch/powerpc/cpu/mpc5xxx/start.S | 2 ++ > 1 file changed, 2 insertions(+) > > Thanks. > > York > > PS, I will be sending out a patch to change my email from freescale.com to nxp.com. >

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[U-Boot] [PATCH 1/3] phy: atheros: Use ar8035_config for AR8031
by Fabio Estevam 05 Jan '16

05 Jan '16

From: Fabio Estevam <fabio.estevam(a)nxp.com> Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- This is 2016.04 material. Zhao Qiang, could you please test this on your platform? drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index d509e30..ba57b1a 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -51,7 +51,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8021_config, + .config = ar8035_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; -- 1.9.1

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[U-Boot] Allowing rtt_nom to be configurable to all possible values
by Fabio Estevam 05 Jan '16

05 Jan '16

Hi, Currently we have in arch/arm/cpu/armv7/mx6/ddr.c: /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227; ,but the mx6 reference manual states rtt_nom = 1 ---> 120 ohm rtt_nom = 2 ---> 60 ohm which is the opposite of what the code and comment do. Also, it is currently not possible to set rtt_nom to any other values other than 1 and 2. On mx6sl evk, for example, we need rtt_nom = 0, which is not possible to be achieved currently. Shouldn't we do like this instead? --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -834,11 +834,12 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, MMDC1(mprddqby3dl, 0x33333333); } - /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */ - val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227; - mmdc0->mpodtctrl = val; + /* MMDC Termination */ + val = sysinfo->rtt_nom; + mmdc0->mpodtctrl = (val << 16) | (val << 12) | (val << 8) | (val << 4) | + 0x7; if (sysinfo->dsize > 1) - MMDC1(mpodtctrl, val); + MMDC1(mpodtctrl, mmdc0->mpodtctrl); Regards, Fabio Estevam

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[U-Boot] [PATCH V3] usb:ci_udc: Remove ULPI setting for i.MX OTG controller
by Peng Fan 05 Jan '16

05 Jan '16

From: "Ye.Li" <B37916(a)freescale.com> All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI interface. Set to ULPI is not correct, even the controller will reject this setting in PORTSC register. Signed-off-by: Ye.Li <B37916(a)freescale.com> Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- Hi Marek, In V2: https://patchwork.ozlabs.org/patch/541663/ The reason still use DBG, but not change to debug, is that the driver use DBG for debugging and error handling usage. So In this patch, I still keep DBG. If you think, it better to switch to use function debug, I can write another patch to convert all the DBGs to debug for ci_udc driver. Regards, Peng. Changes since v2: - Correct code indent. Changes since v1: - Add error handling for udc probe drivers/usb/gadget/ci_udc.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 1ba5054..d36bcf6 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -1018,18 +1018,10 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) return ret; ret = ci_udc_probe(); -#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS) - /* - * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all - * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection - */ - if (!ret) { - struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; - - /* select ULPI phy */ - writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); + if (ret) { + DBG("udc probe failed, returned %d\n", ret); + return ret; } -#endif ret = driver->bind(&controller.gadget); if (ret) { -- 2.6.2

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[U-Boot] [PATCH v6 01/10] mips: implement to access the KSEG0/1 memory range in map_physmem
by Wills Wang 05 Jan '16

05 Jan '16

U-boot just use the no MMU virtual address segment(KSEG0/1), this patch enable access the uncached memory range(KSEG1) by flag "MAP_NOCACHE", other flag for KSEG0 access. Signed-off-by: Wills Wang <wills.wang(a)live.com> --- Changes in v6: - Remove useless "else" Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/include/asm/io.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index a7ab087..77353e5 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -485,7 +485,7 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -#define MAP_NOCACHE (0) +#define MAP_NOCACHE (1) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) #define MAP_WRTHROUGH (0) @@ -493,7 +493,9 @@ static inline void sync(void) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { - return (void *)paddr; + if (flags) + return (void *)KSEG1ADDR(paddr); + return (void *)KSEG0ADDR(paddr); } /* -- 1.9.1

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