January 2016 - U-Boot

[U-Boot] [PATCH 0/4] add support for loading ACPI tables from QEMU
by Miao Yan 20 Jan '16

20 Jan '16

Currently, if CONFIG_GENERATE_ACPI_TABLE is defined, U-Boot will generate ACPI tables itlself, this patchset adds the ability to load the ACPI tables generated by QEMU. Miao Yan (4): x86: qemu: re-structure qemu_fwcfg_list_firmware() x86: qemu: setup PM IO base for ACPI in southbridge x86: qemu: add the ability to load and link ACPI tables from QEMU x86: qemu: loading ACPI table from QEMU arch/x86/cpu/qemu/fw_cfg.c | 274 ++++++++++++++++++++++++++++++-- arch/x86/cpu/qemu/qemu.c | 39 +++++ arch/x86/include/asm/arch-qemu/device.h | 8 + arch/x86/include/asm/fw_cfg.h | 78 +++++++++ arch/x86/lib/tables.c | 5 +- 5 files changed, 389 insertions(+), 15 deletions(-) -- 1.9.1

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[U-Boot] pull request: u-boot-uniphier/master
by Masahiro Yamada 20 Jan '16

20 Jan '16

Hi Tom, Sorry for the short interval from the previous one, but please pull one more series. The following changes since commit 3ed2ece5e162b104cd3ea3788cae841ecd24408f: armv8: cavium: Get DRAM size from ATF (2016-01-19 22:26:13 +0000) are available in the git repository at: git://git.denx.de/u-boot-uniphier.git master for you to fetch changes up to 048c61d674c4e5c793f5391fb7a57c8c79c99ebd: ARM: uniphier: remove unneeded if conditionals (2016-01-20 08:40:33 +0900) ---------------------------------------------------------------- Masahiro Yamada (8): ARM: uniphier: define CONFIG_SYS_BOOTMAPSZ ARM: uniphier: add bootm_low environment ARM: uniphier: refactor outer cache operation slightly ARM: uniphier: factor out outer cache sync as a helper function ARM: uniphier: fix range invalidate for outer cache ARM: uniphier: set active ways to really enable outer cache ARM: uniphier: move UMC register macros to umc-regs.h ARM: uniphier: remove unneeded if conditionals arch/arm/mach-uniphier/cache_uniphier.c | 43 +++++++++++++++++++++++++++++++++++++------ arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c | 10 ++-------- arch/arm/mach-uniphier/dram/umc-proxstream2.c | 49 +------------------------------------------------ arch/arm/mach-uniphier/dram/umc-regs.h | 26 ++++++++++++++++++++++++++ include/configs/uniphier.h | 11 ++++++++--- 5 files changed, 74 insertions(+), 65 deletions(-) -- Best Regards Masahiro Yamada

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[U-Boot] [PATCH] ARM: uniphier: remove unneeded if conditionals
by Masahiro Yamada 20 Jan '16

20 Jan '16

The if block does the same as the else block does. The conditional is not necessary at all. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index 2c8cbc2..9fb34f7 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c @@ -40,18 +40,12 @@ int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) writel(0x0000040B, &phy->dcr); if (freq == 1333) { writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x1a8363c0, &phy->dtpr[1]); writel(0x5002c200, &phy->dtpr[2]); writel(0x00000b51, &phy->mr0); } else { writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); + writel(0x1a878400, &phy->dtpr[1]); writel(0xa00214f8, &phy->dtpr[2]); writel(0x00000d71, &phy->mr0); } -- 1.9.1

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[U-Boot] [PATCH 0/4] ARM: uniphier: refactor and fix UniPhier outer cache
by Masahiro Yamada 20 Jan '16

20 Jan '16

Masahiro Yamada (4): ARM: uniphier: refactor outer cache operation slightly ARM: uniphier: factor out outer cache sync as a helper function ARM: uniphier: fix range invalidate for outer cache ARM: uniphier: set active ways to really enable outer cache arch/arm/mach-uniphier/cache_uniphier.c | 43 ++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 6 deletions(-) -- 1.9.1

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[U-Boot] [PATCH 1/2] ARM: uniphier: define CONFIG_SYS_BOOTMAPSZ
by Masahiro Yamada 20 Jan '16

20 Jan '16

U-Boot relocates the device tree and the initramdisk to the tail of the memory region before booting the kernel. Some UniPhier boards are equipped with a large amount of memory. For those boards, the device tree and the initramdisk are placed out of the the kernel causing a kernel panic. Add CONFIG_SYS_BOOTMAPSZ to prevent them from going too high. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- include/configs/uniphier.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 463c687..c7d8628 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -226,6 +226,8 @@ "nand write $loadaddr 0x00010000 0x000f0000\0" \ LINUXBOOT_ENV_SETTINGS +#define CONFIG_SYS_BOOTMAPSZ 0x20000000 + /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT -- 1.9.1

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[U-Boot] [PATCH] arm: socfpga: revert "set the fpga global bit to disable HPS to FPGA signals"
by Dinh Nguyen 20 Jan '16

20 Jan '16

Revert "arm: socfpga: set the fpga global bit to disable HPS to FPGA signals" Apparently, the logic for the FPGA global bit is not universal between Gen5 and Gen10 devices is not the same. Disabling this bit, while applicable to Gen10 devices, will break FPGA programming on Gen5 devices. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- drivers/fpga/socfpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index 431e159..4448250 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -269,7 +269,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Prior programming the FPGA, all bridges need to be shut off */ /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &sysmgr_regs->fpgaintfgrp_gbl); + writel(0, &sysmgr_regs->fpgaintfgrp_module); /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 -- 1.9.1.315.g3f09db0

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[U-Boot] Block/Disable U-Boot Console Access
by Alan Kash 19 Jan '16

19 Jan '16

Hi, I am an application software guy learning low-level embedded programming. I am trying to block/disable u-boot console access all together. Is there any helpful documentation for this topic. The things I gathered until now: 1. Disable Serial Port pins. Question - If an attacker gains root access, can he reconfigure serial port pins to re-enable this ? How can we disable serial port access at the hardware level ? 2. Enable "silent" & bootdelay=0 environment variables. 3. Enable password protection of U-Boot console. 4. Encrypt "Environment Memory Block" in case of *any* hardware interruptions, the u-boot opens the console. Can we disable this behavior to stop the device unless a power recycle happens or start the boot process again. I appreciate any general comments on this topic. Thanks, Alan

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[U-Boot] [RESEND PATCH v2 0/2] This series adds an ability to use pl01x for early debug output.
by Sergey Temerkhanov 19 Jan '16

19 Jan '16

This is the version 2 of the patch I posted at http://lists.denx.de/pipermail/u-boot/2015-September/227210.html Changes in v2: - Broke down into 2 patches - Minor changes to accomodate Kconfig options - Broke down into 2 patches - Made CONFIG_DEBUG_UART_PL010 and CONFIG_DEBUG_UART_PL011 separate options - Typo fixes Sergey Temerkhanov (2): arm: serial: Add debug UART capability to the pl01x driver arm: serial: Add Kconfig entries to facilitate usage of the pl01x driver for early debug output drivers/serial/Kconfig | 22 ++++++++++++++++++++++ drivers/serial/serial_pl01x.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) -- 2.1.4

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[U-Boot] Block/Disable U-Boot Console Access
by crudbug 19 Jan '16

19 Jan '16

Hi, I am an application software guy learning low-level embedded programming. I am trying to block/disable u-boot console access all together. Is there any helpful documentation for this topic. The things I gathered until now: 1. Disable Serial Port pins. Question - If an attacker gains root access, can he reconfigure serial port pins to re-enable this ? How can we disable serial port access at the hardware level ? 2. Enable "silent" & bootdelay=0 environment variables. 3. Enable password protection of U-Boot console. 4. Encrypt "Environment Memory Block" in case of *any* hardware interruptions, the u-boot opens the console. Can we disable this behavior to stop the device unless a power recycle happens or start the boot process again. I appreciate any general comments on this topic. -- View this message in context: http://u-boot.10912.n7.nabble.com/Block-Disable-U-Boot-Console-Access-tp242… Sent from the U-Boot mailing list archive at Nabble.com.

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[U-Boot] [PATCH] x86: quark: Fix boot breakage
by Bin Meng 19 Jan '16

19 Jan '16

With driver model timer conversion, quark based board does not boot any more as mdelay() is called during quark_pcie_early_init() which is before driver model gets initialized. Fix this breakage. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/quark/quark.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 37ce394..72c681d 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -252,17 +252,6 @@ int arch_cpu_init(void) */ quark_setup_bars(); - /* - * Initialize PCIe controller - * - * Quark SoC holds the PCIe controller in reset following a power on. - * U-Boot needs to release the PCIe controller from reset. The PCIe - * controller (D23:F0/F1) will not be visible in PCI configuration - * space and any access to its PCI configuration registers will cause - * system hang while it is held in reset. - */ - quark_pcie_early_init(); - /* Initialize USB2 PHY */ quark_usb_early_init(); @@ -277,6 +266,22 @@ int arch_cpu_init(void) return 0; } +int arch_cpu_init_dm(void) +{ + /* + * Initialize PCIe controller + * + * Quark SoC holds the PCIe controller in reset following a power on. + * U-Boot needs to release the PCIe controller from reset. The PCIe + * controller (D23:F0/F1) will not be visible in PCI configuration + * space and any access to its PCI configuration registers will cause + * system hang while it is held in reset. + */ + quark_pcie_early_init(); + + return 0; +} + int print_cpuinfo(void) { post_code(POST_CPU_INFO); -- 1.8.2.1

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