January 2016 - U-Boot

[U-Boot] [PATCH] Revert "arm: Remove wireless_space board"
by Albert ARIBAUD 02 Apr '16

02 Apr '16

Revert commit b352182a and complete generic board support. Signed-off-by: Albert ARIBAUD <albert.u.boot(a)aribaud.net> --- arch/arm/mach-kirkwood/Kconfig | 4 + board/LaCie/wireless_space/Kconfig | 12 ++ board/LaCie/wireless_space/MAINTAINERS | 6 + board/LaCie/wireless_space/Makefile | 12 ++ board/LaCie/wireless_space/kwbimage.cfg | 71 +++++++++++ board/LaCie/wireless_space/wireless_space.c | 165 +++++++++++++++++++++++++ configs/wireless_space_defconfig | 7 ++ include/configs/wireless_space.h | 179 ++++++++++++++++++++++++++++ 8 files changed, 456 insertions(+) create mode 100644 board/LaCie/wireless_space/Kconfig create mode 100644 board/LaCie/wireless_space/MAINTAINERS create mode 100644 board/LaCie/wireless_space/Makefile create mode 100644 board/LaCie/wireless_space/kwbimage.cfg create mode 100644 board/LaCie/wireless_space/wireless_space.c create mode 100644 configs/wireless_space_defconfig create mode 100644 include/configs/wireless_space.h diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 9205b1e..9249564 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -37,6 +37,9 @@ config TARGET_NET2BIG_V2 config TARGET_NETSPACE_V2 bool "LaCie netspace_v2 Board" +config TARGET_WIRELESS_SPACE + bool "LaCie Wireless_space Board" + config TARGET_IB62X0 bool "ib62x0 Board" @@ -68,6 +71,7 @@ source "board/iomega/iconnect/Kconfig" source "board/keymile/km_arm/Kconfig" source "board/LaCie/net2big_v2/Kconfig" source "board/LaCie/netspace_v2/Kconfig" +source "board/LaCie/wireless_space/Kconfig" source "board/raidsonic/ib62x0/Kconfig" source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" diff --git a/board/LaCie/wireless_space/Kconfig b/board/LaCie/wireless_space/Kconfig new file mode 100644 index 0000000..75a2fc5 --- /dev/null +++ b/board/LaCie/wireless_space/Kconfig @@ -0,0 +1,12 @@ +if TARGET_WIRELESS_SPACE + +config SYS_BOARD + default "wireless_space" + +config SYS_VENDOR + default "LaCie" + +config SYS_CONFIG_NAME + default "wireless_space" + +endif diff --git a/board/LaCie/wireless_space/MAINTAINERS b/board/LaCie/wireless_space/MAINTAINERS new file mode 100644 index 0000000..c32ecb8 --- /dev/null +++ b/board/LaCie/wireless_space/MAINTAINERS @@ -0,0 +1,6 @@ +WIRELESS_SPACE BOARD +M: Albert ARIBAUD <albert.u.boot(a)aribaud.net> +S: Maintained +F: board/LaCie/wireless_space/ +F: include/configs/wireless_space.h +F: configs/wireless_space_defconfig diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile new file mode 100644 index 0000000..90a84f4 --- /dev/null +++ b/board/LaCie/wireless_space/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := wireless_space.o ../common/common.o diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg new file mode 100644 index 0000000..037248b --- /dev/null +++ b/board/LaCie/wireless_space/kwbimage.cfg @@ -0,0 +1,71 @@ +# +# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot(a)aribaud.net> +# +# Based on netspace_v2 kwbimage.cfg: +# Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.kwbimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # Boot from NAND flash +NAND_PAGE_SIZE 800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Values taken from image original LaCie U-Boot header dump! + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register + +DATA 0xFFD01404 0x37743000 # DDR Controller Control Low + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control + +DATA 0xFFD01418 0x00000000 # DDR Operation + +DATA 0xFFD0141C 0x00000662 # DDR Mode + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) + +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x66666666 +DATA 0xFFD10000 0x01112222 +DATA 0xFFD1000C 0x00000000 +DATA 0xFFD10104 0x00000000 +DATA 0xFFD10100 0x40000000 +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c new file mode 100644 index 0000000..8620e4b --- /dev/null +++ b/board/LaCie/wireless_space/wireless_space.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "../common/common.h" +#include "netdev.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO configuration: start FAN at low speed, USB and HDD */ + +#define WIRELESS_SPACE_OE_LOW 0xFF006808 +#define WIRELESS_SPACE_OE_HIGH 0x0000F989 +#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 +#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 + +#define WIRELESS_SPACE_REAR_BUTTON 13 +#define WIRELESS_SPACE_FRONT_BUTTON 43 + +const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Fan speed (bit 1) */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Red led */ + MPP14_GPIO, /* USB fuse */ + MPP15_SATA0_ACTn, + MPP16_GPIO, /* SATA 0 power */ + MPP17_GPIO, /* SATA 1 power */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, /* Gigabit Ethernet 1 */ + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GE1_8, + MPP29_GE1_9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GE1_15, + MPP36_GPIO, /* Fan speed (bit 2) */ + MPP37_GPIO, /* Fan speed (bit 0) */ + MPP38_GPIO, /* Fan power */ + MPP39_GPIO, /* Fan rotation fail */ + MPP40_GPIO, /* Ethernet switch link */ + MPP41_GPIO, /* USB enable host vbus */ + MPP42_GPIO, /* LED clock control */ + MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ + MPP44_GPIO, /* Red LED on/off */ + MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ + MPP46_GPIO, /* Green LED on/off */ + MPP47_GPIO, /* LED (blue, green) SATA activity blink */ + MPP48_GPIO, /* Blue LED on/off */ + 0 +}; + +struct mv88e61xx_config swcfg = { + .name = "egiga0", + .vlancfg = MV88E61XX_VLANCFG_ROUTER, + .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, + .led_init = MV88E61XX_LED_INIT_EN, + .mdip = MV88E61XX_MDIP_NOCHANGE, + .portstate = MV88E61XX_PORTSTT_FORWARDING, + .cpuport = 0x20, + .ports_enabled = 0x3F, +}; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + mvebu_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* Boot parameters address */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); + } +#endif + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + /* configure switch on egiga0 */ + mv88e61xx_switch_initialize(&swcfg); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) +/* Return GPIO button status */ +static int +do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "button") == 0) { + if (strcmp(argv[2], "rear") == 0) + /* invert GPIO result for intuitive while/until use */ + return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); + else if (strcmp(argv[2], "front") == 0) + return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); + else + return -1; + } else { + return -1; + } +} + +U_BOOT_CMD(ws, 3, 0, do_ws, + "Return GPIO button status 0=off 1=on", + "- ws button rear|front: test buttons' states\n" +); +#endif diff --git a/configs/wireless_space_defconfig b/configs/wireless_space_defconfig new file mode 100644 index 0000000..daf8870 --- /dev/null +++ b/configs/wireless_space_defconfig @@ -0,0 +1,7 @@ +CONFIG_ARM=y +CONFIG_KIRKWOOD=y +CONFIG_TARGET_WIRELESS_SPACE=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_SYS_NS16550=y diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h new file mode 100644 index 0000000..191ac1b --- /dev/null +++ b/include/configs/wireless_space.h @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot(a)aribaud.net> + * + * Based on the netspace_v2 code which is + * Copyright (C) 2011 Simon Guinot <sguinot(a)lacie.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_WIRELESS_SPACE_H +#define _CONFIG_WIRELESS_SPACE_H + +/* + * Machine number definition + */ +#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE +#define CONFIG_IDENT_STRING " Wireless Space" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +/* SoC name */ +#define CONFIG_KW88F6281 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB + +/* + * Core clock definition + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * SDRAM configuration + */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * Different SDRAM configuration and size for some of the boards derived + * from the Network Space v2 + */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_RBTREE +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */ +#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */ +#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */ +#define CONFIG_MII +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_NETCONSOLE +#define CONFIG_MV88E61XX_SWITCH +#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define CONFIG_MV88E61XX_CMD +#define CONFIG_CMD_TFTPPUT +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Enable I2C support + */ +#ifdef CONFIG_CMD_I2C +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ +#endif /* CONFIG_CMD_I2C */ + +/* + * Partition support + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* + * File systems support + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment variables configurations + */ + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ + +/* + * Board-specific command to make using buttons etc easier + */ + +#define CONFIG_WIRELESS_SPACE_CMD + +/* + * Default environment variables + */ +#define CONFIG_PREBOOT + +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=ide reset && " \ + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \ + "preboot=" \ + "dhcp && run netconsole\0" + +#endif /* _CONFIG_WIRELESS_SPACE_H */ -- 2.5.0

2 2

[U-Boot] [PATCH V4 1/3] arm: discard relocation entries for secure text
by Peng Fan 31 Mar '16

31 Mar '16

The code such as PSCI in section named secure is bundled with u-boot image, and when bootm, the code will be copied to their runtime address same to compliation/linking address - CONFIG_ARMV7_SECURE_BASE. When compile the PSCI code and link it into the u-boot image, there will be relocation entries in .rel.dyn section for PSCI. Actually, we do not needs these relocation entries. If still keep the relocation entries in .rel.dyn section, r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid address which may not support read/write for one SoC. 102 /* relative fix: increase location by offset */ 103 add r0, r0, r4 104 ldr r1, [r0] 105 add r1, r1, r4 106 str r1, [r0] So discard them to avoid touching the relocation entry in arch/arm/lib/relocate.S. Signed-off-by: Peng Fan <Peng.Fan(a)freescale.com> Cc: Tom Warren <twarren(a)nvidia.com> Cc: York Sun <yorksun(a)freescale.com> Cc: Hans De Goede <hdegoede(a)redhat.com> Cc: Ian Campbell <ijc(a)hellion.org.uk> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Tom Rini <trini(a)konsulko.com> Cc: Jan Kiszka <jan.kiszka(a)siemens.com> Cc: Stefano Babic <sbabic(a)denx.de> --- Changes v4: none V2 thread: http://lists.denx.de/pipermail/u-boot/2015-October/230755.html Changes v3: Move the relocation entries to the very begining and discard them. V1 thread: http://lists.denx.de/pipermail/u-boot/2015-October/229426.html Changes V2: Refine commit msg. Discard the relocation entry section for secure text. arch/arm/cpu/u-boot.lds | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 03cd9f6..d48a905 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -14,6 +14,23 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { + /* + * Discard the relocation entries for secure text. + * The secure code is bundled with u-boot image, so there will + * be relocations entries for the secure code, since we use + * "-mword-relocations" to compile and "-pie" to link into the + * final image. We do not need the relocation entries for secure + * code, because secure code will not be relocated, it only needs + * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE, + * which is the linking and running address for secure code. + * If keep the relocation entries in .rel.dyn section, + * "relocation offset + linking address" may locates into an + * address that is reserved by SoC, then will trigger data abort. + * + * The reason that move .rel._secure at the beginning, is to + * avoid hole in the final image. + */ + /DISCARD/ : { *(.rel._secure*) } . = 0x00000000; . = ALIGN(4); -- 1.8.4

6 11

[U-Boot] [PATCH] tools/kwboot.c: Support UART fallback mode
by Kevin Smith 29 Mar '16

29 Mar '16

On some processors such as Armada 38x, if the hardware- configured boot mode fails, the CPU falls back to booting over UART. When this happens the chip prints a failure message, waits for the magic sequence and, when it is received, prints a "(boot)" message, then sends a NAK to start the transfer. This breaks the current kwboot behavior because the xmodem transfer only tries to read one character after the magic sequence, looking for the NAK. Instead it gets the "(boot)" text, and retries the magic sequence. The CPU thinks the repeated sequence is part of the packet, stops NAKing, and one side or another eventually times out. This patch adds support for a fallback mode which continues to scan for a NAK in the characters received after the sequence, printing out any non-NAK characters. This allows kwboot to skip the "(boot)" message, find the NAK, and start the transfer successfully. Signed-off-by: Kevin Smith <kevin.smith(a)elecsyscorp.com> --- tools/kwboot.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/tools/kwboot.c b/tools/kwboot.c index af7a6ee..6b58fc9 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -71,6 +71,7 @@ struct kwboot_block { #define KWBOOT_BLK_RSP_TIMEO 1000 /* ms */ static int kwboot_verbose; +static int support_fallback; static int msg_req_delay = KWBOOT_MSG_REQ_DELAY; static int msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO; @@ -300,7 +301,15 @@ kwboot_bootmsg(int tty, void *msg) continue; } - rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo); + while (1) { + rc = kwboot_tty_recv(tty, &c, 1, msg_rsp_timeo); + if (support_fallback && rc == 0 && c != NAK) { + printf("%c", c); + fflush(stdout); + continue; + } + break; + } kwboot_spinner(); @@ -657,7 +666,7 @@ static void kwboot_usage(FILE *stream, char *progname) { fprintf(stream, - "Usage: %s [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n", + "Usage: %s [-f] [-d | -a | -q <req-delay> | -s <resp-timeo> | -b <image> | -D <image> ] [ -t ] [-B <baud> ] <TTY>\n", progname); fprintf(stream, "\n"); fprintf(stream, @@ -667,6 +676,7 @@ kwboot_usage(FILE *stream, char *progname) " -D <image>: boot <image> without preamble (Dove)\n"); fprintf(stream, " -d: enter debug mode\n"); fprintf(stream, " -a: use timings for Armada XP\n"); + fprintf(stream, " -f: support UART fallback after failed boot\n"); fprintf(stream, " -q <req-delay>: use specific request-delay\n"); fprintf(stream, " -s <resp-timeo>: use specific response-timeout\n"); fprintf(stream, "\n"); @@ -701,7 +711,7 @@ main(int argc, char **argv) kwboot_verbose = isatty(STDOUT_FILENO); do { - int c = getopt(argc, argv, "hb:ptaB:dD:q:s:"); + int c = getopt(argc, argv, "hb:ptfaB:dD:q:s:"); if (c < 0) break; @@ -728,6 +738,10 @@ main(int argc, char **argv) term = 1; break; + case 'f': + support_fallback = 1; + break; + case 'a': msg_req_delay = KWBOOT_MSG_REQ_DELAY_AXP; msg_rsp_timeo = KWBOOT_MSG_RSP_TIMEO_AXP; -- 2.4.6

2 3

[U-Boot] [PATCH] mvebu: usb: Add missing controller reset after initialization
by Phil Sutter 24 Mar '16

24 Mar '16

In order to allow for Linux properly register the integrated EHCI host, we have to reset it after initialization. Without this, enumeration fails if 'usb start' wasn't issued prior to booting Linux. Signed-off-by: Phil Sutter <phil(a)nwl.cc> --- arch/arm/mach-mvebu/cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 5c62fd5..cb885f8 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -281,6 +281,8 @@ static void set_cbar(u32 addr) (((addr) & 0xF) << 6)) #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \ (((reg) & 0xF) << 2)) +#define MV_USB_CMD_REG(dev) (MVEBU_AXP_USB_BASE + (dev * 0x1000) + 0x140) +#define MV_USB_MODE_REG(dev) (MVEBU_AXP_USB_BASE + (dev * 0x1000) + 0x1A8) static void setup_usb_phys(void) { @@ -313,6 +315,16 @@ static void setup_usb_phys(void) setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); udelay(40); clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12)); + + /* disable (bit 0) and reset (bit 1) controller */ + /* XXX: do this in two steps? */ + clrsetbits_le32(MV_USB_CMD_REG(dev), BIT(0), BIT(1)); + + while(readl(MV_USB_CMD_REG(dev)) & BIT(1)) + ; + + /* set host mode (device mode is (0x2 | 1 << 3)) */ + writel(0x3, MV_USB_MODE_REG(dev)); } } -- 2.5.3

4 8

[U-Boot] [PATCH v0 0/5] Some improvements for mvebu/a38x
by dirk.eibach＠gdsys.cc 24 Mar '16

24 Mar '16

From: Dirk Eibach <dirk.eibach(a)gdsys.cc> Dirk Eibach (5): pci: mvebu: Fix Armada 38x support arm: mvebu: Add gpio support arm: mvebu: Fix SAR1_CPU_CORE_MASK arm: mvebu: Fix ddr3_init() cpu config spi: Add support for Armada 38x second controller arch/arm/mach-mvebu/include/mach/gpio.h | 41 ++++++++++++++++- arch/arm/mach-mvebu/include/mach/soc.h | 1 + .../ddr/marvell/a38x/ddr3_hws_hw_training_def.h | 7 +-- drivers/ddr/marvell/a38x/ddr3_init.c | 2 - drivers/pci/pci_mvebu.c | 22 ++++----- drivers/spi/kirkwood_spi.c | 52 +++++++++++++++++++--- 6 files changed, 98 insertions(+), 27 deletions(-) -- 2.1.3

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[U-Boot] [PATCH] arm: mvebu: enable generic distro boot config
by Dennis Gilmore 24 Mar '16

24 Mar '16

Switch all of the mvebu boards to support disto generic booting This will enable Fedora, Debian and other distros to support mvebu systems easier. Tested on SolidRun ClearFog Signed-off-by: Dennis Gilmore <dgilmore(a)redhat.com> --- include/configs/clearfog.h | 5 --- include/configs/mv-common.h | 86 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 85 insertions(+), 6 deletions(-) diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index f0de827..926b3c5 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -104,11 +104,6 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - /* SPL */ /* * Select the boot device here diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index d12d725..e219243 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -57,7 +57,7 @@ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200,230400, 460800, 921600 } /* auto boot */ -#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ +#define CONFIG_BOOTDELAY 2 /* default enable autoboot */ #define CONFIG_PREBOOT #define CONFIG_OF_LIBFDT /* Device tree support */ @@ -152,4 +152,88 @@ #define CONFIG_LZO #endif +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +/* +* 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. +* 32M uncompressed kernel, 16M compressed kernel, 1M fdt, +* 1M script, 1M pxe and the ramdisk at the end. +*/ +#define SDRAM_OFFSET(x) 0x0##x + +#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) +#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) +#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) +#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) +#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0xa000000\0" \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_CMD_SATA +#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0) func(SATA, sata, 1) +#define CONFIG_PREBOOT "sata init" +#else +#define BOOT_TARGET_DEVICES_SATA(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_SATA(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) + +#include <config_distro_bootcmd.h> + +#ifdef CONFIG_USB_KEYBOARD +#define CONSOLE_STDIN_SETTINGS \ + "preboot=usb start\0" \ + "stdin=serial,usbkbd\0" +#else +#define CONSOLE_STDIN_SETTINGS \ + "stdin=serial\0" +#endif + +#ifdef CONFIG_VIDEO +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial,vga\0" \ + "stderr=serial,vga\0" +#else +#define CONSOLE_STDOUT_SETTINGS \ + "stdout=serial\0" \ + "stderr=serial\0" +#endif + +#define CONSOLE_ENV_SETTINGS \ + CONSOLE_STDIN_SETTINGS \ + CONSOLE_STDOUT_SETTINGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONSOLE_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "console=ttyS0,115200\0" \ + BOOTENV +#else /* ifndef CONFIG_SPL_BUILD */ +#define CONFIG_EXTRA_ENV_SETTINGS +#endif + #endif /* _MV_COMMON_H */ -- 2.5.0

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[U-Boot] [PATCH 0/4] ARM: sheevaplug: misc fixes
by Peter Korsgaard 24 Mar '16

24 Mar '16

Hi, The following patch series fixes a number of issues I noticed while updating a sheevaplug from 2013.10 to 2016.01: Peter Korsgaard (4): ARM: sheevaplug: unbreak default environment ARM: sheevaplug: unbreak kernel bootargs / mtdparts command by dropping double mtdparts= ARM: sheevaplug: drop unneded 'usb start' from boot command ARM: sheevaplug: correct nand partition layout -- Bye, Peter Korsgaard

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[U-Boot] [PATCHv2 1/3] armv8: fsl-layerscape: add i/d-cache enable function to enable_caches
by Zhiqiang Hou 23 Mar '16

23 Mar '16

From: Hou Zhiqiang <Zhiqiang.Hou(a)freescale.com> This function assume that the d-cache and MMU has been enabled earlier, so it just created MMU table in main memory. But the assumption is not always correct, for example, the early setup is done in EL3, while enable_caches() is called when the PE has turned into another EL. Define the function mmu_setup() for fsl-layerscape to cover the weak one. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)freescale.com> --- Tested on LS1043A RDB board V2: - Replace patch [PATCH 1/3] ARMv8/layerscape: Add mmu_init API arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 6ea28ed..3147870 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -393,15 +393,21 @@ int arch_cpu_init(void) return 0; } +void mmu_setup(void) +{ + final_mmu_setup(); +} + /* - * This function is called from lib/board.c. - * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. - * There is no need to disable d-cache for this operation. + * This function is called from common/board_r.c. + * It recreates MMU table in main memory. */ void enable_caches(void) { - final_mmu_setup(); + mmu_setup(); __asm_invalidate_tlb_all(); + icache_enable(); + dcache_enable(); } #endif -- 2.1.0.27.g96db324

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[U-Boot] [PATCH] eth: dtsec: fix TBI ANA setting bug in dtsec_configure_serdes()
by Yuanzheng Li 22 Mar '16

22 Mar '16

The TBI_ANA register is configurated with the wrong value 0x4001, refer to QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual. It set the reserved areas, bit 1 and bit 11 to bit 15 in big endian, which should be cleared. But the normal functions of the auto-negotiation, e.g. Pause and Full Duplex, do not be set. There is no problem in the p2041rdb board, because the ppc is connected directly with the phy chip which support auto-negotiation by default in SGMII interface. But the link problem will occur when it is connected with a switch chip like BCM5389, the switch chip disable auto-negotiation by default, and the ppc also disable auto-negotiation, then there is no link between them. So use the vlue TBIANA_SETTINGS to enable the ppc's auto-negotiation. Signed-off-by: Yuanzheng Li <liyuanzheng01(a)163.com> Cc: York Sun <yorksun(a)freescale.com> --- drivers/net/fm/eth.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index eb8e936..78c0988 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -81,7 +81,7 @@ qsgmii_loop: tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON, TBICON_CLK_SELECT); tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA, - TBIANA_SGMII_ACK); + TBIANA_SETTINGS); tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_CR, TBICR_SETTINGS); #endif -- 1.7.8

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[U-Boot] [PATCH][v2] armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
by shh.xie＠gmail.com 22 Mar '16

22 Mar '16

From: Shaohui Xie <Shaohui.Xie(a)nxp.com> To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)nxp.com> --- changes in v2: 1. move Interrupt register offset define to immap_lsch3.h. arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 ++++ board/freescale/ls2080ardb/ls2080ardb.c | 4 ++++ include/configs/ls2080ardb.h | 1 + 3 files changed, 9 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index cd96604..f182dea 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -94,6 +94,10 @@ #define DCFG_DCSR_BASE 0X700100000ULL #define DCFG_DCSR_PORCR1 0x000 +/* Interrupt Sampling Control */ +#define ISC_BASE 0x01F70000 +#define IRQCR_OFFSET 0x14 + /* Supplemental Configuration */ #define SCFG_BASE 0x01fc0000 #define SCFG_USB3PRM1CR 0x000 diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 2ae9d6c..da227a7 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -149,6 +149,7 @@ int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; u32 val; init_final_memctl_regs(); @@ -170,6 +171,9 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); + /* invert AQR405 IRQ pins polarity */ + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); + return 0; } diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 65d4f64..0d60420 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -336,6 +336,7 @@ unsigned long get_board_sys_clk(void); #define AQ_PHY_ADDR2 0x01 #define AQ_PHY_ADDR3 0x02 #define AQ_PHY_ADDR4 0x03 +#define AQR405_IRQ_MASK 0x36 #define CONFIG_MII #define CONFIG_ETHPRIME "DPNI1" -- 2.1.0.27.g96db324

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