January 2016 - U-Boot

[U-Boot] [PATCH] drivers/crypto/fsl : Allocate output ring with size aligned to CACHELNE SIZE
by Ruchika Gupta 24 Feb '16

24 Feb '16

From: Ruchika Gupta <ruchika.gupta(a)freescale.com> The output ring needs to be invalidated before enqueuing the job to SEC. While allocation of space to output ring, it should be taken care that the size is cacheline size aligned inorder to prevent invalidating valid data. The patch also correct the method of aligning end of structs while flushing caches Since start = align(start_of_struct), it is incorrect to assign end = align(start + struct_size). It should instead be, end = align(start_of_struct + struct_size). Signed-off-by: Saksham Jain <saksham(a)nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> --- drivers/crypto/fsl/jr.c | 28 ++++++++++++++++------------ drivers/crypto/fsl/jr.h | 2 ++ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b553e3c..4566ec3 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -95,14 +95,16 @@ static int jr_init(void) JR_SIZE * sizeof(dma_addr_t)); if (!jr.input_ring) return -1; + + jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring), + ARCH_DMA_MINALIGN); jr.output_ring = - (struct op_ring *)memalign(ARCH_DMA_MINALIGN, - JR_SIZE * sizeof(struct op_ring)); + (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size); if (!jr.output_ring) return -1; memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); - memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring)); + memset(jr.output_ring, 0, jr.op_size); start_jr0(); @@ -190,8 +192,8 @@ static int jr_enqueue(uint32_t *desc_addr, unsigned long start = (unsigned long)&jr.info[head] & ~(ARCH_DMA_MINALIGN - 1); - unsigned long end = ALIGN(start + sizeof(struct jr_info), - ARCH_DMA_MINALIGN); + unsigned long end = ALIGN((unsigned long)&jr.info[head] + + sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); #ifdef CONFIG_PHYS_64BIT @@ -216,11 +218,19 @@ static int jr_enqueue(uint32_t *desc_addr, #endif /* ifdef CONFIG_PHYS_64BIT */ start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); - end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN); + end = ALIGN((unsigned long)&jr.input_ring[head] + + sizeof(dma_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); jr.head = (head + 1) & (jr.size - 1); + /* Invalidate output ring */ + start = (unsigned long)jr.output_ring & + ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)jr.output_ring + jr.op_size, + ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + sec_out32(&regs->irja, 1); return 0; @@ -241,12 +251,6 @@ static int jr_dequeue(void) #endif while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) { - unsigned long start = (unsigned long)jr.output_ring & - ~(ARCH_DMA_MINALIGN - 1); - unsigned long end = ALIGN(start + - sizeof(struct op_ring)*JR_SIZE, - ARCH_DMA_MINALIGN); - invalidate_dcache_range(start, end); found = 0; diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 5899696..545d964 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -72,6 +72,8 @@ struct jobring { int write_idx; /* Size of the rings. */ int size; + /* Op ring size aligned to cache line size */ + int op_size; /* The ip and output rings have to be accessed by SEC. So the * pointers will ahve to point to the housekeeping region provided * by SEC -- 1.8.1.4

3 2

[U-Boot] [PATCH] ls2-2085a: Increase default hugepage count
by Ashish Kumar 24 Feb '16

24 Feb '16

* Increase default hugepage count to 256 from 16 * Note: default env variables are stored at 0x580200000/0x584200000 of size 0x2000 Signed-off-by: Ashish Kumar <Ashish.Kumar(a)freescale.com> --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4ae7d11..a503934 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -272,7 +272,7 @@ unsigned long long get_qixis_addr(void); #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 10 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 116dbcd..356d254 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -333,7 +333,7 @@ unsigned long get_board_sys_clk(void); #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0600" \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" + " hugepagesz=2m hugepages=256" /* MAC/PHY configuration */ #ifdef CONFIG_FSL_MC_ENET -- 1.7.6.GIT

4 10

[U-Boot] [PATCH v2] ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
by Dongsheng Wang 24 Feb '16

24 Feb '16

From: Wang Dongsheng <dongsheng.wang(a)nxp.com> "DISCARD" will remove ._secure.text relocate, but PSCI framework has already used some absolute address those need to relocate. Use readelf -t -r u-boot show us: .__secure_start addr: 601408e4 .__secure_end addr: 60141460 60141140 00000017 R_ARM_RELATIVE 46 _secure_monitor: 47 #ifdef CONFIG_ARMV7_PSCI 48 ldr r5, =_psci_vectors 60141194 00000017 R_ARM_RELATIVE 6014119c 00000017 R_ARM_RELATIVE 601411a4 00000017 R_ARM_RELATIVE 601411ac 00000017 R_ARM_RELATIVE 64 _psci_table: 66 .word psci_cpu_suspend ... 72 .word psci_migrate 60141344 00000017 R_ARM_RELATIVE 6014145c 00000017 R_ARM_RELATIVE 202 ldr r5, =psci_text_end Solutions: 1. Change absolute address to RelAdr. Based on LDR (immediate, ARM), we only have 4K offset to jump. Now PSCI code size is close to 4K size that is LDR limit jump size, so even if the LDR is based on the current instruction address, there is also have a risk for RelAdr. If we use two jump steps I think we can fix this issue, but looks too hack, so give up this way. 2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined. If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure will in the BASE address that is absolute. Signed-off-by: Wang Dongsheng <dongsheng.wang(a)nxp.com> diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index d48a905..e148ab7 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -14,23 +14,24 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) /* - * Discard the relocation entries for secure text. - * The secure code is bundled with u-boot image, so there will - * be relocations entries for the secure code, since we use - * "-mword-relocations" to compile and "-pie" to link into the - * final image. We do not need the relocation entries for secure - * code, because secure code will not be relocated, it only needs - * to be copied from loading address to CONFIG_ARMV7_SECURE_BASE, - * which is the linking and running address for secure code. - * If keep the relocation entries in .rel.dyn section, - * "relocation offset + linking address" may locates into an - * address that is reserved by SoC, then will trigger data abort. + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. * - * The reason that move .rel._secure at the beginning, is to - * avoid hole in the final image. + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. */ /DISCARD/ : { *(.rel._secure*) } +#endif . = 0x00000000; . = ALIGN(4); -- 2.1.0.27.g96db324

3 3

[U-Boot] [PATCH 1/3][v3] Pointers in ESBC header made 32 bit
by Aneesh Bansal 23 Feb '16

23 Feb '16

For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal(a)freescale.com> --- Changes in v3: Patch Rebased and removed compile time warnings board/freescale/common/fsl_validate.c | 20 ++++++++++---------- include/fsl_validate.h | 14 +++++++------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 5283648..465676f 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -63,12 +63,12 @@ static u32 check_ie(struct fsl_secboot_img_priv *img) * address */ #if defined(CONFIG_MPC85xx) -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); - ulong flash_addr, addr; + u32 flash_addr, addr; int found = 0; int i = 0; @@ -76,7 +76,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) flash_addr = flash_info[i].start[0]; addr = flash_info[i].start[0] + csf_flash_offset; if (memcmp((u8 *)addr, barker_code, ESBC_BARKER_LEN) == 0) { - debug("Barker found on addr %lx\n", addr); + debug("Barker found on addr %x\n", addr); found = 1; break; } @@ -94,7 +94,7 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) /* For platforms like LS1020, correct flash address is present in * the header. So the function reqturns flash base address as 0 */ -int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) +int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); @@ -108,11 +108,11 @@ int get_csf_base_addr(ulong *csf_addr, ulong *flash_base_addr) } #endif -static int get_ie_info_addr(ulong *ie_addr) +static int get_ie_info_addr(u32 *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; - ulong flash_base_addr, csf_addr; + u32 flash_base_addr, csf_addr; if (get_csf_base_addr(&csf_addr, &flash_base_addr)) return -1; @@ -127,11 +127,11 @@ static int get_ie_info_addr(ulong *ie_addr) */ #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) sg_tbl = (struct fsl_secboot_sg_table *) - (((ulong)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else sg_tbl = (struct fsl_secboot_sg_table *)(csf_addr + - (ulong)hdr->psgtable); + (u32)hdr->psgtable); #endif /* IE Key Table is the first entry in the SG Table */ @@ -142,7 +142,7 @@ static int get_ie_info_addr(ulong *ie_addr) *ie_addr = sg_tbl->src_addr; #endif - debug("IE Table address is %lx\n", *ie_addr); + debug("IE Table address is %x\n", *ie_addr); return 0; } @@ -549,7 +549,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) if (memcmp(hdr->barker, barker_code, ESBC_BARKER_LEN)) return ERROR_ESBC_CLIENT_HEADER_BARKER; - sprintf(buf, "%p", hdr->pimg); + sprintf(buf, "%x", hdr->pimg); setenv("img_addr", buf); if (!hdr->img_size) diff --git a/include/fsl_validate.h b/include/fsl_validate.h index c460534..92dd98b 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -82,14 +82,14 @@ struct fsl_secboot_img_hdr { u32 psign; /* signature offset */ u32 sign_len; /* length of the signature in bytes */ union { - struct fsl_secboot_sg_table *psgtable; /* ptr to SG table */ - u8 *pimg; /* ptr to ESBC client image */ + u32 psgtable; /* ptr to SG table */ + u32 pimg; /* ptr to ESBC client image */ }; union { u32 sg_entries; /* no of entries in SG table */ u32 img_size; /* ESBC client image size in bytes */ }; - ulong img_start; /* ESBC client entry point */ + u32 img_start; /* ESBC client entry point */ u32 sg_flag; /* Scatter gather flag */ u32 uid_flag; u32 fsl_uid_0; @@ -133,7 +133,7 @@ struct srk_table { */ struct fsl_secboot_sg_table { u32 len; /* length of the segment in bytes */ - ulong src_addr; /* ptr to the data segment */ + u32 src_addr; /* ptr to the data segment */ }; #else /* @@ -146,8 +146,8 @@ struct fsl_secboot_sg_table { struct fsl_secboot_sg_table { u32 len; u32 trgt_id; - ulong src_addr; - ulong dst_addr; + u32 src_addr; + u32 dst_addr; }; #endif @@ -162,7 +162,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - ulong ie_addr; + u32 ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr; -- 1.8.1.4

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[U-Boot] [PATCH 01/10] video: Add S3C24xx framebuffer support
by Marek Vasut 22 Feb '16

22 Feb '16

Add basic framebuffer driver for the S3C24xx family of CPUs. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Anatolij Gustschin <agust(a)denx.de> Cc: Kyungmin Park <kyungmin.park(a)samsung.com> Cc: Lukasz Majewski <l.majewski(a)samsung.com> Cc: Minkyu Kang <mk7.kang(a)samsung.com> Cc: Vladimir Zapolskiy <vz(a)mleia.com> V2: Keep the Makefile sorted. --- drivers/video/Makefile | 1 + drivers/video/cfb_console.c | 2 +- drivers/video/s3c-fb.c | 172 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+), 1 deletion(-) create mode 100644 drivers/video/s3c-fb.c diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 14a6781..0e407d0 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o +obj-$(CONFIG_VIDEO_S3C) += s3c-fb.o videomodes.o obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 9231927..98d10e3 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -135,7 +135,7 @@ #endif #endif -#ifdef CONFIG_VIDEO_MXS +#if defined(CONFIG_VIDEO_MXS) || defined(CONFIG_VIDEO_S3C) #define VIDEO_FB_16BPP_WORD_SWAP #endif diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c new file mode 100644 index 0000000..521eb75 --- /dev/null +++ b/drivers/video/s3c-fb.c @@ -0,0 +1,172 @@ +/* + * S3C24x0 LCD driver + * + * NOTE: Only 16/24 bpp operation with TFT LCD is supported. + * + * Copyright (C) 2014 Marek Vasut <marex(a)denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <malloc.h> +#include <video_fb.h> + +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h> + +#include "videomodes.h" + +static GraphicDevice panel; + +/* S3C requires the FB to be 4MiB aligned. */ +#define S3CFB_ALIGN (4 << 20) + +#define S3CFB_LCDCON1_CLKVAL(x) ((x) << 8) +#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 << 5) +#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1) +#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1) + +#define S3CFB_LCDCON2_VBPD(x) ((x) << 24) +#define S3CFB_LCDCON2_LINEVAL(x) ((x) << 14) +#define S3CFB_LCDCON2_VFPD(x) ((x) << 6) +#define S3CFB_LCDCON2_VSPW(x) ((x) << 0) + +#define S3CFB_LCDCON3_HBPD(x) ((x) << 19) +#define S3CFB_LCDCON3_HOZVAL(x) ((x) << 8) +#define S3CFB_LCDCON3_HFPD(x) ((x) << 0) + +#define S3CFB_LCDCON4_HSPW(x) ((x) << 0) + +#define S3CFB_LCDCON5_BPP24BL (1 << 12) +#define S3CFB_LCDCON5_FRM565 (1 << 11) +#define S3CFB_LCDCON5_HWSWP (1 << 0) + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +/* + * Example: + * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\ + * pclk:30066,le:41,ri:89,up:45,lo:12, + * hs:1,vs:1,sync:100663296,vmode:0 + */ +static void s3c_lcd_init(GraphicDevice *panel, + struct ctfb_res_modes *mode, int bpp) +{ + uint32_t clk_divider; + struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd(); + + /* Stop the controller. */ + clrbits_le32(&regs->lcdcon1, 1); + + /* Calculate clock divider. */ + clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000; + clk_divider = DIV_ROUND_UP(clk_divider, 2); + if (clk_divider) + clk_divider -= 1; + + /* Program LCD configuration. */ + switch (bpp) { + case 16: + writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + &regs->lcdcon1); + writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565, + &regs->lcdcon5); + break; + case 24: + writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP | + S3CFB_LCDCON1_PNRMODE_TFT | + S3CFB_LCDCON1_CLKVAL(clk_divider), + &regs->lcdcon1); + writel(S3CFB_LCDCON5_BPP24BL, &regs->lcdcon5); + break; + } + + writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) | + S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) | + S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) | + S3CFB_LCDCON2_VSPW(mode->vsync_len - 1), + &regs->lcdcon2); + + writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) | + S3CFB_LCDCON3_HFPD(mode->left_margin - 1) | + S3CFB_LCDCON3_HOZVAL(mode->xres - 1), + &regs->lcdcon3); + + writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1), + &regs->lcdcon4); + + /* Write FB address. */ + writel(panel->frameAdrs >> 1, &regs->lcdsaddr1); + writel((panel->frameAdrs + + (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1, + &regs->lcdsaddr2); + writel(mode->xres * bpp / 16, &regs->lcdsaddr3); + + /* Start the controller. */ + setbits_le32(&regs->lcdcon1, 1); +} + +void *video_hw_init(void) +{ + int bpp = -1; + char *penv; + void *fb; + struct ctfb_res_modes mode; + + puts("Video: "); + + /* Suck display configuration from "videomode" variable */ + penv = getenv("videomode"); + if (!penv) { + puts("S3CFB: 'videomode' variable not set!\n"); + return NULL; + } + + bpp = video_get_params(&mode, penv); + + /* fill in Graphic device struct */ + sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); + + panel.winSizeX = mode.xres; + panel.winSizeY = mode.yres; + panel.plnSizeX = mode.xres; + panel.plnSizeY = mode.yres; + + switch (bpp) { + case 24: + panel.gdfBytesPP = 4; + panel.gdfIndex = GDF_32BIT_X888RGB; + break; + case 16: + panel.gdfBytesPP = 2; + panel.gdfIndex = GDF_16BIT_565RGB; + break; + default: + printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp); + return NULL; + } + + panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; + + /* Allocate framebuffer */ + fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN)); + if (!fb) { + printf("S3CFB: Error allocating framebuffer!\n"); + return NULL; + } + + /* Wipe framebuffer */ + memset(fb, 0, panel.memSize); + + panel.frameAdrs = (u32)fb; + + printf("%s\n", panel.modeIdent); + + /* Start framebuffer */ + s3c_lcd_init(&panel, &mode, bpp); + + return (void *)&panel; +} -- 2.1.1

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[U-Boot] [PATCH 00/26] spl: Support loading a FIT image containing U-Boot
by Simon Glass 22 Feb '16

22 Feb '16

7 42

[U-Boot] [PATCH V2 00/11] imx: introduce rdc and boot auxiliary core
by Peng Fan 21 Feb '16

21 Feb '16

From: Peng Fan <peng.fan(a)nxp.com> To i.MX6SX and i.MX7D, there is a M4 core embedded. Resources can be shared or occupied exclusively by setting Resource domain controller between A9/7 core and M4 core. Refer "Chapter 52 Resource Domain Controller (RDC)" of i.MX 6SoloX RM and "Chapter 3.2 Resource Domain Controller (RDC)" of i.MX 7Dual RM for detailed infomation. To bootup M4 core, a new command 'bootaux' is introduced. To i.MX7D, we need to setting RDC when booting M4 core, so make RDC and boot auxiliary core patches into one patch set. Since we also sometimes put the M4 image in QSPI to let M4 directly fecth code in the memory mapped QSPI space, we can not support such as libz compressed image. Peng Fan (11): imx: mx6: introduce rdc regs imx: imx-common: introduce Resource Domain Controller support imx: mx6sx Add RDC mappings of masters and peripherals imx: mx7d: Add RDC support imx: mx7d: clock support for RDC imx: imx-common: introduce boot auxiliary core imx: mx6: implement functions to boot auxiliary core imx: mx6sxsabresd: add command and macros for boot m4 core imx: mx7: implement functions to boot auxiliary core imx: mx7dsabresd: add command and macros for boot m4 core imx: mx7d: isolate resources to domain 0 for A7 core arch/arm/cpu/armv7/mx6/soc.c | 38 ++++++ arch/arm/cpu/armv7/mx7/clock.c | 6 + arch/arm/cpu/armv7/mx7/soc.c | 100 ++++++++++++++++ arch/arm/imx-common/Kconfig | 14 +++ arch/arm/imx-common/Makefile | 2 + arch/arm/imx-common/imx_bootaux.c | 72 ++++++++++++ arch/arm/imx-common/rdc-sema.c | 183 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/imx-rdc.h | 16 +++ arch/arm/include/asm/arch-mx6/imx-regs.h | 29 +++++ arch/arm/include/asm/arch-mx6/mx6sx_rdc.h | 155 ++++++++++++++++++++++++ arch/arm/include/asm/arch-mx7/imx-rdc.h | 16 +++ arch/arm/include/asm/arch-mx7/imx-regs.h | 8 ++ arch/arm/include/asm/arch-mx7/mx7d_rdc.h | 163 +++++++++++++++++++++++++ arch/arm/include/asm/imx-common/rdc-sema.h | 100 ++++++++++++++++ configs/mx7dsabresd_defconfig | 2 + include/configs/mx6sxsabresd.h | 24 ++++ include/configs/mx7dsabresd.h | 24 ++++ 17 files changed, 952 insertions(+) create mode 100644 arch/arm/imx-common/imx_bootaux.c create mode 100644 arch/arm/imx-common/rdc-sema.c create mode 100644 arch/arm/include/asm/arch-mx6/imx-rdc.h create mode 100644 arch/arm/include/asm/arch-mx6/mx6sx_rdc.h create mode 100644 arch/arm/include/asm/arch-mx7/imx-rdc.h create mode 100644 arch/arm/include/asm/arch-mx7/mx7d_rdc.h create mode 100644 arch/arm/include/asm/imx-common/rdc-sema.h -- 2.6.2

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[U-Boot] [PATCH 00/10] x86: ivybridge: Add Intel FSP support
by Bin Meng 19 Feb '16

19 Feb '16

This series adds Intel FSP support to IvyBridge processor and Panther Point chipset (aka Chief River platform), and is validated on Intel Cougar Canyon 2 board. This only adds basic features like serial, keyboard, RTC, timer, SPI, GPIO, PCI, SATA, USB. Other features will be enabled in future patch set. Bin Meng (10): fdtdec: Add compatible string for Intel IvyBridge FSP x86: ivybridge: Add FSP support tools: microcode-tool: Support parsing header file with a license block x86: ivybridge: Add microcode blobs for all the steppings superio: Add SMSC SIO1007 driver x86: ivybridge: Do not require HAVE_INTEL_ME x86: fsp: Make sure HOB list is not overwritten by U-Boot x86: fsp: Always use hex numbers in the hob command output x86: ivybridge: Add macros for LPC decode ranges x86: Add Intel Cougar Canyon 2 board arch/x86/cpu/ivybridge/Kconfig | 9 +- arch/x86/cpu/ivybridge/Makefile | 4 + arch/x86/cpu/ivybridge/fsp_configs.c | 45 ++ arch/x86/cpu/ivybridge/ivybridge.c | 22 + arch/x86/dts/Makefile | 1 + arch/x86/dts/cougarcanyon2.dts | 96 +++ arch/x86/dts/microcode/m12306a2_00000008.dtsi | 554 +++++++++++++++++ arch/x86/dts/microcode/m12306a4_00000007.dtsi | 618 +++++++++++++++++++ arch/x86/dts/microcode/m12306a5_00000007.dtsi | 618 +++++++++++++++++++ arch/x86/dts/microcode/m12306a8_00000010.dtsi | 682 +++++++++++++++++++++ .../include/asm/arch-ivybridge/fsp/fsp_configs.h | 40 ++ arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h | 12 + arch/x86/include/asm/arch-ivybridge/pch.h | 10 + arch/x86/lib/fsp/cmd_fsp.c | 4 +- arch/x86/lib/fsp/fsp_support.c | 27 + board/google/chromebook_link/Kconfig | 1 + board/google/chromebox_panther/Kconfig | 1 + board/intel/Kconfig | 9 + board/intel/cougarcanyon2/Kconfig | 25 + board/intel/cougarcanyon2/MAINTAINERS | 6 + board/intel/cougarcanyon2/Makefile | 7 + board/intel/cougarcanyon2/cougarcanyon2.c | 48 ++ board/intel/cougarcanyon2/start.S | 9 + configs/cougarcanyon2_defconfig | 21 + drivers/misc/Makefile | 1 + drivers/misc/smsc_sio1007.c | 126 ++++ include/configs/cougarcanyon2.h | 34 + include/fdtdec.h | 1 + include/smsc_sio1007.h | 115 ++++ lib/fdtdec.c | 1 + tools/microcode-tool.py | 14 + 31 files changed, 3158 insertions(+), 3 deletions(-) create mode 100644 arch/x86/cpu/ivybridge/fsp_configs.c create mode 100644 arch/x86/cpu/ivybridge/ivybridge.c create mode 100644 arch/x86/dts/cougarcanyon2.dts create mode 100644 arch/x86/dts/microcode/m12306a2_00000008.dtsi create mode 100644 arch/x86/dts/microcode/m12306a4_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a5_00000007.dtsi create mode 100644 arch/x86/dts/microcode/m12306a8_00000010.dtsi create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-ivybridge/fsp/fsp_vpd.h create mode 100644 board/intel/cougarcanyon2/Kconfig create mode 100644 board/intel/cougarcanyon2/MAINTAINERS create mode 100644 board/intel/cougarcanyon2/Makefile create mode 100644 board/intel/cougarcanyon2/cougarcanyon2.c create mode 100644 board/intel/cougarcanyon2/start.S create mode 100644 configs/cougarcanyon2_defconfig create mode 100644 drivers/misc/smsc_sio1007.c create mode 100644 include/configs/cougarcanyon2.h create mode 100644 include/smsc_sio1007.h -- 1.8.2.1

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[U-Boot] [PATCH v4 0/6] rockchip: kylin: Boot with android boot image
by Jeffy Chen 19 Feb '16

19 Feb '16

We are porting android to kylin board now. This series could let it boot up with android's boot image. Changes in v4: Remove unused reboot mode definitions. Changes in v3: Use rockchip's legacy reboot mode definitions. Changes in v2: Add comments. Jeffy Chen (6): common/image-fdt.c: Make boot_get_fdt() perform a check for Android images ARM: bootm: Try to use relocated ramdisk rockchip: rk3036: Bind GPIO banks rockchip: kylin: Add default gpt partition table rockchip: kylin: Enable boot with android boot image rockchip: kylin: Check fastboot request arch/arm/lib/bootm.c | 12 ++++++- board/kylin/kylin_rk3036/kylin_rk3036.c | 32 ++++++++++++++++++ common/image-fdt.c | 4 +++ drivers/pinctrl/rockchip/pinctrl_rk3036.c | 8 +++++ include/configs/kylin_rk3036.h | 55 +++++++++++++++++++++++++++++++ 5 files changed, 110 insertions(+), 1 deletion(-) -- 2.1.4

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[U-Boot] [PATCH] usb: dwc2: Enhance interrupt handling for CONTROL transaction
by Chin Liang See 19 Feb '16

19 Feb '16

Per DesignWare USB OTG databook, driver should retry up to 3 times when transaction error (hcint.xacterr) happen. But the 3 times doesn't count when the response is nack (hcint.nak) or frame overrun (hcint.frmoverun) This patch solved the enumeration error as spotted at socfpga cyclone5_socdk when plugging in certain pendrive. Signed-off-by: Chin Liang See <clsee(a)altera.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Dinh Nguyen <dinguyen(a)opensource.altera.com> Cc: Dinh Nguyen <dinh.linux(a)gmail.com> Cc: Pavel Machek <pavel(a)denx.de> Cc: Oleksandr Tymoshenko <gonzo(a)bluezbox.com> Cc: Stephen Warren <swarren(a)wwwdotorg.org> Cc: Alexander Stein <alexanders83(a)web.de> Cc: Peter Griffin <peter.griffin(a)linaro.org> --- drivers/usb/host/dwc2.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 541c0f9..f00cd1b 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -786,15 +786,12 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, uint32_t xfer_len; uint32_t num_packets; int stop_transfer = 0; + int error_retry_count = 0; debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, in, len); do { - /* Initialize channel */ - dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, - eptype, max); - xfer_len = len - done; if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1; @@ -818,6 +815,14 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, *pid, xfer_len, num_packets); + /* per DW spec, we can retry up to 3 times */ + error_retry_count = 3; + +error_retry: + /* Initialize channel */ + dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, + eptype, max); + writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | (*pid << DWC2_HCTSIZ_PID_OFFSET), @@ -841,8 +846,14 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, DWC2_HCCHAR_CHEN); ret = wait_for_chhltd(regs, &sub, pid, ignore_ack); - if (ret) - break; + if (ret) { + if (ret == -EINVAL) + error_retry_count--; + if (error_retry_count) + goto error_retry; + else + break; + } if (in) { xfer_len -= sub; -- 1.9.2.468.g3f0c02a

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