January 2016 - U-Boot

[U-Boot] Converting openrisc to generic board
by Simon Glass 15 May '16

15 May '16

Hi Stefan, I would like to remove all the arch/*/lib/board.c files soon. Can you please take a look at converting openrisc to use generic board? doc/README.generic-board Thanks! Simon

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[U-Boot] [PATCH] fdt: fix setting MAC addresses for multiple interfaces
by Lev Iserovich 04 May '16

04 May '16

For multiple ethernet interfaces the FDT offset of '/aliases' will change as we are adding MAC addresses to the FDT. Therefore only the first interface ('ethernet0') will get properly updated in the FDT, with the rest getting FDT errors when we try to set their MAC address. Switch to using fdt_get_alias() which is the proper way to get the FDT path. Signed-off-by: Lev Iserovich <iserovil(a)deshawresearch.com> --- common/fdt_support.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 66464db..20e0e1c 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -481,16 +481,12 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size) void fdt_fixup_ethernet(void *fdt) { - int node, i, j; + int i, j; char enet[16], *tmp, *end; char mac[16]; const char *path; unsigned char mac_addr[6]; - node = fdt_path_offset(fdt, "/aliases"); - if (node < 0) - return; - if (!getenv("ethaddr")) { if (getenv("usbethaddr")) { strcpy(mac, "usbethaddr"); @@ -505,7 +501,7 @@ void fdt_fixup_ethernet(void *fdt) i = 0; while ((tmp = getenv(mac)) != NULL) { sprintf(enet, "ethernet%d", i); - path = fdt_getprop(fdt, node, enet, NULL); + path = fdt_get_alias(fdt, enet); if (!path) { debug("No alias for %s\n", enet); sprintf(mac, "eth%daddr", ++i); -- 2.1.0

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[U-Boot] [PATCH 0/2] net: phy: mv88e61xx: Revise as a PHY driver
by Kevin Smith 03 May '16

03 May '16

The previous version of this driver implemented a shell command to manually comfigure the switch. It did not integrate with the PHY infrastructure to allow a MAC to use it as its PHY. This is complete rewrite to allow this switch to function as a driver. Since none of the original driver remains, the old driver is first removed and the new PHY driver is added. This version configures the switch to have a CPU connected over an MII interface. It will enable PHY interfaces based on the MV88E61XX_PHY_PORTS macro. The switch is configured to allow PHY ports to only communicate to the CPU. This allows the switch to be used as a basic PHY on any/all ports. This was developed on a board with an mv88e6176 connected over SGMII. It is intended to work with other configurations, but these could not be tested. Any testing on other configurations or with other mv88e61xx chips is appreciated. Signed-off-by: Kevin Smith <kevin.smith(a)elecsyscorp.com> Acked-by: Prafulla Wadaskar <prafulla(a)marvell.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Marek Vasut <marex(a)denx.de> Kevin Smith (2): net: Remove unused mv88e61xx switch driver net: phy: Add PHY driver for mv88e61xx switches drivers/net/phy/mv88e61xx.c | 959 +++++++++++++++++++++++++------------------- drivers/net/phy/mv88e61xx.h | 61 --- drivers/net/phy/phy.c | 3 + include/netdev.h | 58 --- include/phy.h | 1 + 5 files changed, 547 insertions(+), 535 deletions(-) delete mode 100644 drivers/net/phy/mv88e61xx.h -- 2.4.6

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[U-Boot] [PATCH 0/8] net: Split out the Ethernet uclass into its own file
by Simon Glass 01 May '16

01 May '16

Every other uclass is in its own file. It makes sense to put the Ethernet uclass code into its own file too. The result is less code in each file, and it becomes easier to see which code is related to driver model. This series creates a new common file to hold the common code, moves the driver-model into its own file and tidies up. Some boards use PCI to obtain Ethernet. With driver model, unless this is mentioned in the device tree, the Ethernet device will not be present on initial startup. So we need to probe PCI just in case there is a device there. Simon Glass (8): tegra: Report errors from PCI init net: Don't call board/cpu_eth_init() with driver model net: Move common init into a new eth_common.c file net: Move environment functions to the common file net: Move remaining common functions to eth_common.c net: Move driver-model code into its own file net: Rename eth.c to eth_lecacy.c net: Probe PCI before looking for ethernet devices drivers/pci/pci_tegra.c | 6 +- net/Makefile | 7 +- net/{eth.c => eth-uclass.c} | 601 +------------------------------------------- net/eth_common.c | 166 ++++++++++++ net/eth_internal.h | 40 +++ net/eth_legacy.c | 439 ++++++++++++++++++++++++++++++++ 6 files changed, 664 insertions(+), 595 deletions(-) rename net/{eth.c => eth-uclass.c} (50%) create mode 100644 net/eth_common.c create mode 100644 net/eth_internal.h create mode 100644 net/eth_legacy.c -- 2.6.0.rc2.230.g3dd15c0

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[U-Boot] [PATCH] net: Add mv88e60xx support to the mv88e61xx driver
by Joshua Scott 26 Apr '16

26 Apr '16

The Marvell Link Street mv88e60xx is a series of FastEthernet switch chips, some of which also support Gigabit ports. It is similar to the mv88e61xx series which support Gigabit on all ports. There is already a driver for the mv88e61xx in U-Boot, and this patch updates it to also work with the mv88e60xx. The main change that was required was the size of the port bitmaps. Previously, 8-bit port bitmaps were in use, as the driver had only been used with six-port mv88e61xx devices. This has been changed so that 16-bit port bitmaps are now used, which covers the largest port-counts available for the mv88e60xx / mv88e61xx. Reviewed-by: Chris Packham <chris.packham(a)alliedtelesis.co.nz> Signed-off-by: Joshua Scott <joshua.scott(a)alliedtelesis.co.nz> --- drivers/net/phy/mv88e61xx.c | 29 +++++++++++++++++++++-------- drivers/net/phy/mv88e61xx.h | 2 -- include/netdev.h | 20 +++++++++++++++----- 3 files changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 302abe8..79204f3 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -215,17 +215,17 @@ static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) u32 port_mask = swconfig->ports_enabled; /* apply internal vlan config */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { /* only for enabled ports */ if ((1 << prt) & port_mask) { /* take vlan map from swconfig */ - u8 vlanmap = swconfig->vlancfg[prt]; + u16 vlanmap = swconfig->vlancfg[prt]; /* remove disabled ports from vlan map */ vlanmap &= swconfig->ports_enabled; /* apply vlan map to port */ RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_VMAP_REG, &reg); - reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); + reg &= ~((1 << swconfig->numports) - 1); reg |= vlanmap; WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_VMAP_REG, reg); @@ -331,32 +331,44 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) return -1; } - if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { + if (!(swconfig->cpuport & ((1 << 4) | (1 << 5) | (1 << 10)))) { swconfig->cpuport = (1 << 5); printf("Invalid cpu port config, using default port5\n"); } RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg); switch (reg &= 0xfff0) { + case 0x0980: + idstr = "88E6096"; + swconfig->numports = 0x0b; + break; + case 0x0990: + idstr = "88E6097"; + swconfig->numports = 0x0b; + break; case 0x1610: idstr = "88E6161"; + swconfig->numports = 0x06; break; case 0x1650: idstr = "88E6165"; + swconfig->numports = 0x06; break; case 0x1210: idstr = "88E6123"; + swconfig->numports = 0x06; /* ports 2,3,4 not available */ swconfig->ports_enabled &= 0x023; break; default: /* Could not detect switch id */ idstr = "88E61??"; + swconfig->numports = 0x06; break; } /* be sure all ports are disabled */ - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg); reg &= ~0x3; WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); @@ -405,12 +417,13 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); } - for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + for (prt = 0; prt < swconfig->numports; prt++) { /* configure port's PHY */ if (!((1 << prt) & swconfig->cpuport)) { - /* port 4 has phy 6, not 4 */ - int phy = (prt == 4) ? 6 : prt; + /* 88e61xx: port 4 has phy 6, not 4 */ + int phy = (swconfig->numports == 6 && + prt == 4) ? 6 : prt; if (mv88361xx_powerup(swconfig, phy)) return -1; if (mv88361xx_reverse_mdipn(swconfig, phy)) diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h index 9c62e4a..b289f21 100644 --- a/drivers/net/phy/mv88e61xx.h +++ b/drivers/net/phy/mv88e61xx.h @@ -11,8 +11,6 @@ #include <miiphy.h> -#define MV88E61XX_CPU_PORT 0x5 - #define MV88E61XX_PHY_TIMEOUT 100000 /* port dev-addr (= port + 0x10) */ diff --git a/include/netdev.h b/include/netdev.h index 34651ab..cbd0420 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -154,7 +154,9 @@ static inline int pci_eth_init(bd_t *bis) #if defined(CONFIG_MV88E61XX_SWITCH) /* constants for any 88E61xx switch */ -#define MV88E61XX_MAX_PORTS_NUM 6 +/* Allow enough space in the struct to fit 11 ports, as this is + * the number used in the mv88e60xx */ +#define MV88E61XX_MAX_PORTS_NUM 0x0b enum mv88e61xx_cfg_mdip { MV88E61XX_MDIP_NOCHANGE, @@ -180,13 +182,14 @@ enum mv88e61xx_cfg_prtstt { struct mv88e61xx_config { char *name; - u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; + u16 vlancfg[MV88E61XX_MAX_PORTS_NUM]; enum mv88e61xx_cfg_rgmiid rgmii_delay; enum mv88e61xx_cfg_prtstt portstate; enum mv88e61xx_cfg_ledinit led_init; enum mv88e61xx_cfg_mdip mdip; + u32 numports; u32 ports_enabled; - u8 cpuport; + u32 cpuport; }; /* @@ -196,10 +199,17 @@ struct mv88e61xx_config { */ /* Switch mode : routes any port to any port */ -#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } +#define MV88E61XX_VLANCFG_SWITCH { 0x003F, 0x003F, 0x003F, 0x003F, 0x003F, \ + 0x003F, 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000 } /* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ -#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } +#define MV88E61XX_VLANCFG_ROUTER { 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, \ + 0x001F, 0x0000, 0x0000, 0x0000, 0x0000, \ + 0x0000 } +#define MV88E60XX_VLANCFG_ROUTER { 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, \ + 0x0400, 0x0400, 0x0400, 0x0400, 0x0400, \ + 0x03ff } int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); #endif /* CONFIG_MV88E61XX_SWITCH */ -- 1.9.1

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[U-Boot] [PATCH v2 1/2] m68k: add malloc memory for early malloc
by Angelo Dureghello 23 Apr '16

23 Apr '16

To use serial uclass and DM, CONFIG_SYS_MALLOC_F must be used. So CONFIG_SYS_GENERIC_GLOBAL_DATA has been undefined and call to board_init_f_mem() is added for all cpu's. Signed-off-by: Angelo Dureghello <angelo(a)sysam.it> --- Changes in v2: None arch/m68k/cpu/mcf5227x/start.S | 8 ++++++++ arch/m68k/cpu/mcf523x/start.S | 8 ++++++++ arch/m68k/cpu/mcf52x2/start.S | 8 ++++++++ arch/m68k/cpu/mcf530x/cpu_init.c | 2 +- arch/m68k/cpu/mcf530x/start.S | 8 ++++++++ arch/m68k/cpu/mcf532x/start.S | 8 ++++++++ arch/m68k/cpu/mcf5445x/start.S | 8 ++++++++ arch/m68k/cpu/mcf547x_8x/start.S | 8 ++++++++ arch/m68k/include/asm/config.h | 2 -- 9 files changed, 57 insertions(+), 3 deletions(-) diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index 23024f9..bcb5611 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -379,6 +379,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index 8a23e72..14b3025 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -141,6 +141,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index 8a59496..abb9291 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -198,6 +198,14 @@ _after_flashbar_copy: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c index 80dc239..b09eed8 100644 --- a/arch/m68k/cpu/mcf530x/cpu_init.c +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -142,7 +142,7 @@ int cpu_init_r(void) return 0; } -void uart_port_conf(void) +void uart_port_conf(int port) { } diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 097958a..d9034e1 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -137,6 +137,14 @@ _start: /* put relocation table address to a5 */ move.l #__got_start, %a5 + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + /* run low-level CPU init code (from flash) */ bsr cpu_init_f diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 3b9ede0..98a5401 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -155,6 +155,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index 979eb5a..340ab84 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -664,6 +664,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + bsr cpu_init_f /* run low-level CPU init code (from flash) */ bsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index 75de22d..0468d1a 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -148,6 +148,14 @@ _start: move.l #__got_start, %a5 /* put relocation table address to a5 */ + /* Allocate and zero GD, update SP */ + move.l %sp,-(%sp) + bsr board_init_f_mem + + /* Update stack- and frame-pointers */ + move.l %d0, %sp + move.l %sp, %fp + jbsr cpu_init_f /* run low-level CPU init code (from flash) */ jbsr board_init_f /* run low-level board init code (from flash) */ diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index e1458ac..9c4d3fb 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -7,8 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA - #define CONFIG_NEEDS_MANUAL_RELOC #define CONFIG_LMB -- 2.5.3

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[U-Boot] FPGA detection failure on Cyclone V soc development kit
by Måns Rullgård 12 Apr '16

12 Apr '16

I'm having a problem with u-boot 2016.01 failing to detect the FPGA on my Altera Cyclone V SoC Development Kit. On startup, it simply prints "FPGA: Not Altera chip ID" (the ID having been read as all-zero). No amount of messing with jumpers or switches makes a difference. The software on the SD card included in the box appears to work, so on a whim I took the SPL pre-loader from this card and combined it with the main 2016.01 u-boot. This makes the detection succeed, despite Marek baulking at this idea. The "good" SPL identifies as "U-Boot SPL 2013.01.01 (Dec 04 2014 - 08:59:41)" which is a different build date than the main u-boot on the same SD card, so which source code version it was built from is anyone's guess. What's interesting is that Marek's board works with u-boot 2016.01 while mine fails even with the very same binary. The boards are different revisions (his 100-0321003-C1, mine -E1), and the main Cyclone V chips are also different (his 5CSXFC6D6F31C8NES, mine 5CSXFC6D6F31C6N). Any suggestions for what to try next? -- Måns Rullgård

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[U-Boot] [RFC 0/2] Add cdns-i2c driver as drop in for zynq-i2c
by Moritz Fischer 12 Apr '16

12 Apr '16

Hi all, I spent some time moving over the zynq-i2c.c to support dm. While doing that I realized that renaming it to cdns-i2c might make sense since it now could be used with other SoCs that also use the the Cadence IP. This is a first shot, but I'd like to get some early feedback ;-) Cheers, Moritz PS: I skipped touching the Zynq board files for now, since I wanted to make sure I get the driver right first ;-) Moritz Fischer (2): i2c: Describe Cadence I2C devicetree bindings dm: i2c: Add driver for Cadence I2C IP doc/device-tree-bindings/i2c/i2c-cdns.txt | 20 ++ drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/i2c-cdns.c | 339 ++++++++++++++++++++++++++++++ 4 files changed, 367 insertions(+) create mode 100644 doc/device-tree-bindings/i2c/i2c-cdns.txt create mode 100644 drivers/i2c/i2c-cdns.c -- 2.4.3

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[U-Boot] Fwd: Marvell Armada XP u-boot from uart
by Konstantin Lezhnyev 06 Apr '16

06 Apr '16

---------- Forwarded message ---------- From: Konstantin Lezhnyev <konst.ru(a)gmail.com> Date: 2015-05-26 13:30 GMT+05:00 Subject: Re: [U-Boot] Marvell Armada XP u-boot from uart To: Stefan Roese <sr(a)denx.de> I'm sorry, the wording of my question was too short. I have already fulfilled the steps described in the article. But the article describes loading of the image from manufacturer - it is not my case. 1. I create a configuration for my board from maxbcm config. 2. Set `BOOT_FROM` parameter in board\my\kwbimage.cfg to `uart`. 3. Set DDR timings/settings. 4. Upload and execute image via uart. 5. Memory training ended successfully. But then I get the following messages in the terminal: | >>spl:board_init_r() | boot device - 8 | ... | SPI probe failed. Boot device 8 - constant `BOOT_DEVICE_SPI`. Function code returns this value looks like: | u32 spl_boot_device(void) | { | /* Right now only booting via SPI NOR flash is supported */ | return BOOT_DEVICE_SPI; | } And now I repeat my question: >Is it possible to load and boot Marvell Armada XP u-boot completely from uart without spi or nand flash? Regards, kon5t. 2015-05-23 13:08 GMT+05:00 Stefan Roese <sr(a)denx.de>: > On 22.05.2015 16:12, Peter Robinson wrote: > >> Is it possible to load and boot Marvell Armada XP u-boot completely from >>> uart without spi or nand flash? >>> I have custom board with MV78460 and clean flash memory. >>> >> >> You can use kwboot I believe. >> > > Correct. kwboot can be used to upload and execute a binary (compiled for > UART booting) via UART. Please make sure to use the "-a" parameter for the > Armada XP timings. > > Thanks, > Stefan > >

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[U-Boot] [RFC PATCH v1] kirkwood_nand: claim MPP pins on the fly
by Chris Packham 06 Apr '16

06 Apr '16

Claim the MPP pins for the NAND flash controller only when it's actually being used. This allows the pins to be shared with the SPI interface which already supports an equivalent on-access MPP reconfiguration. Reviewed-by: Mark Tomlinson <mark.tomlinson(a)alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- I haven't wrapped this with a configuration option because I think it should be safe to enable by default. It will either re-apply the same MPP configuration that has already been done in the board init or put the MPP pins into the correct mode to access NAND. I've only got access to one kirkwood based board with NAND flash so I'd appreciate some feedback from someone with access to a few different boards. >From the datasheets I have access to it looks like there is only one possible MPP configuration for NF_IO[0-7] so that is what I've implemented. I'm not aware of anything using this driver that needs a different MPP config. drivers/mtd/nand/kirkwood_nand.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index 4fc34d6..ff81212 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -9,6 +9,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/soc.h> +#include <asm/arch/mpp.h> #include <nand.h> /* NAND Flash Soc registers */ @@ -22,6 +23,8 @@ struct kwnandf_registers { static struct kwnandf_registers *nf_reg = (struct kwnandf_registers *)KW_NANDF_BASE; +static u32 nand_mpp_backup[9] = { 0 }; + /* * hardware specific access to control-lines/bits */ @@ -49,6 +52,22 @@ static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, void kw_nand_select_chip(struct mtd_info *mtd, int chip) { u32 data; + u32 nand_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP18_NF_IO0, + MPP19_NF_IO1, + 0 + }; + + if (chip >= 0) + kirkwood_mpp_conf(nand_config, nand_mpp_backup); + else + kirkwood_mpp_conf(nand_mpp_backup, NULL); data = readl(&nf_reg->ctrl); data |= NAND_ACTCEBOOT_BIT; -- 2.7.0

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