September 2015 - U-Boot

[U-Boot] [PATCH] arm: at91: Change the Chip ID registers' addresses
by Wenyou Yang 03 Nov '15

03 Nov '15

Provide the specific addresses for the Chip ID and Chip ID Extension registers, instead of the offset, which make it use on other chips. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- arch/arm/mach-at91/armv7/cpu.c | 7 ++++--- arch/arm/mach-at91/include/mach/at91_dbu.h | 4 ---- arch/arm/mach-at91/include/mach/sama5d3.h | 3 +++ arch/arm/mach-at91/include/mach/sama5d4.h | 3 +++ 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 8d86f97..7843aed 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -12,7 +12,6 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/at91_dbu.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_pit.h> #include <asm/arch/at91_gpbr.h> @@ -65,12 +64,14 @@ void enable_caches(void) dcache_enable(); } +#define ATMEL_CHIPID_CIDR_VERSION 0x1f + unsigned int get_chip_id(void) { - return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK; + return readl(ATMEL_CHIPID_CIDR) & ~ATMEL_CHIPID_CIDR_VERSION; } unsigned int get_extension_chip_id(void) { - return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID); + return readl(ATMEL_CHIPID_EXID); } diff --git a/arch/arm/mach-at91/include/mach/at91_dbu.h b/arch/arm/mach-at91/include/mach/at91_dbu.h index 7346fc0..3181138 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbu.h @@ -35,8 +35,4 @@ typedef struct at91_dbu { #define AT91_DBU_CID_ARCH_9xx 0x01900000 #define AT91_DBU_CID_ARCH_9XExx 0x02900000 -#define AT91_DBU_CIDR_MASK 0x1f -#define AT91_DBU_CIDR 0x40 -#define AT91_DBU_EXID 0x44 - #endif diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index b749cb3..33f6c97 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -158,6 +158,9 @@ #define ATMEL_BASE_RTC 0xfffffeb0 /* Reserved: 0xfffffee0 - 0xffffffff */ +#define ATMEL_CHIPID_CIDR 0xffffee40 +#define ATMEL_CHIPID_EXID 0xffffee44 + /* * Internal Memory. */ diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index 7773ace..3da8aff 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -144,6 +144,9 @@ #define ATMEL_BASE_PIOE 0xfc06d000 #define ATMEL_BASE_AIC 0xfc06e000 +#define ATMEL_CHIPID_CIDR 0xfc069040 +#define ATMEL_CHIPID_EXID 0xfc069044 + /* * Internal Memory. */ -- 1.7.9.5

3 3

[U-Boot] [v2, 4/4] mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter Card
by Yangbo Lu 02 Nov '15

02 Nov '15

When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card), enable EVDD automatic control via SDHC_VS. This could support SD card IO voltage switching for UHS-1 speed mode. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- board/freescale/common/qixis.h | 3 +++ drivers/mmc/fsl_esdhc.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 450cd0d..0aa56a0 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -125,10 +125,13 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */ #define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */ #define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ + #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 #define QIXIS_DAT5_6_7 0X02 #define QIXIS_DAT4 0X01 + +#define QIXIS_EVDD_BY_SDHC_VS 0x0c #endif #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 639ec02..f400dc9 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -752,6 +752,9 @@ void mmc_adapter_card_type_ident(void) QIXIS_WRITE(brdcfg[5], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: + value = QIXIS_READ(pwr_ctl[1]); + value |= QIXIS_EVDD_BY_SDHC_VS; + QIXIS_WRITE(pwr_ctl[1], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: value = QIXIS_READ(brdcfg[5]); -- 2.1.0.27.g96db324

2 1

[U-Boot] [v2, 3/4] powerpc/t1040qds: enable peripheral clock for eSDHC
by Yangbo Lu 02 Nov '15

02 Nov '15

Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- include/configs/T1040QDS.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8353b8f..92bc295 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -593,6 +593,7 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC +#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC -- 2.1.0.27.g96db324

2 1

[U-Boot] [v2, 2/4] powerpc/t1040qds: enable adapter card type identification support
by Yangbo Lu 02 Nov '15

02 Nov '15

Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- include/configs/T1040QDS.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index a0390a8..8353b8f 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -599,6 +599,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC_ADAPTER_IDENT #endif /* Qman/Bman */ -- 2.1.0.27.g96db324

2 1

[U-Boot] [v2, 1/4] mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter Card
by Yangbo Lu 02 Nov '15

02 Nov '15

If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 Adapter Card. Signed-off-by: Yangbo Lu <yangbo.lu(a)freescale.com> --- Changes for v2: - Modified the commit message - Added a patch enabling EVDD automatic control --- board/freescale/common/qixis.h | 2 ++ drivers/mmc/fsl_esdhc.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 51ce9c3..450cd0d 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -127,6 +127,8 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ #define QIXIS_SDCLKIN 0x08 #define QIXIS_SDCLKOUT 0x02 +#define QIXIS_DAT5_6_7 0X02 +#define QIXIS_DAT4 0X01 #endif #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0b37002..639ec02 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -747,6 +747,9 @@ void mmc_adapter_card_type_ident(void) switch (card_id) { case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); + QIXIS_WRITE(brdcfg[5], value); break; case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: break; -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH] Powerpc: eSDHC: expand a fix to T4160
by shh.xie＠gmail.com 02 Nov '15

02 Nov '15

From: Shaohui Xie <Shaohui.Xie(a)freescale.com> commit b8e5b07225 "Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS board", T4160 also needs this fix. Signed-off-by: Shaohui Xie <Shaohui.Xie(a)freescale.com> --- drivers/mmc/fsl_esdhc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 0b37002..73730b3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -106,7 +106,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) xfertyp |= XFERTYP_RSPTYP_48; #if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \ - defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) + defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A) || \ + defined(CONFIG_PPC_T4160) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif -- 2.1.0.27.g96db324

2 1

[U-Boot] [PATCH V2] t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdm
by Zhao Qiang 02 Nov '15

02 Nov '15

qe-tdm is muxed with diu, if hwconfig setted as qe-tdm, assign muxed pins to qe-tdm, then delete diu node from device tree. Signed-off-by: Zhao Qiang <qiang.zhao(a)freescale.com> --- changes for v2 - move fdt_del_diu to arch/powerpc/cpu/mpc85xx/fdt.c - add new .h file arch/powerpc/include/asm/fsl_fdt.h for FSL-FDT arch/powerpc/cpu/mpc85xx/fdt.c | 11 +++++++++++ arch/powerpc/include/asm/fsl_fdt.h | 11 +++++++++++ board/freescale/t104xrdb/cpld.h | 1 + board/freescale/t104xrdb/t104xrdb.c | 10 ++++++++++ 4 files changed, 33 insertions(+) create mode 100644 arch/powerpc/include/asm/fsl_fdt.h diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index d4c3d9d..7270be1 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -13,6 +13,7 @@ #include <asm/processor.h> #include <linux/ctype.h> #include <asm/io.h> +#include <asm/fsl_fdt.h> #include <asm/fsl_portals.h> #include <hwconfig.h> #ifdef CONFIG_FSL_ESDHC @@ -943,3 +944,13 @@ int ft_verify_fdt(void *fdt) return 1; } + +void fdt_del_diu(void *blob) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, + "fsl,diu")) >= 0) { + fdt_del_node(blob, nodeoff); + } +} diff --git a/arch/powerpc/include/asm/fsl_fdt.h b/arch/powerpc/include/asm/fsl_fdt.h new file mode 100644 index 0000000..82e8f45 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_fdt.h @@ -0,0 +1,11 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _FSL_FDT_H_ +#define _FSL_FDT_H_ + +void fdt_del_diu(void *blob); + +#endif diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 2fb4105..86de26c 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -44,3 +44,4 @@ void cpld_write(unsigned int reg, u8 value); cpld_write(offsetof(struct cpld_data, reg), value) #define MISC_CTL_SG_SEL 0x80 #define MISC_CTL_AURORA_SEL 0x02 +#define MISC_MUX_QE_TDM 0xc0 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index d982dfc..3227652 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -6,12 +6,14 @@ #include <common.h> #include <command.h> +#include <hwconfig.h> #include <netdev.h> #include <linux/compiler.h> #include <asm/mmu.h> #include <asm/processor.h> #include <asm/cache.h> #include <asm/immap_85xx.h> +#include <asm/fsl_fdt.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_portals.h> @@ -110,6 +112,12 @@ int misc_init_r(void) MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); #if defined(CONFIG_T1040D4RDB) + if (hwconfig("qe-tdm")) { + CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | + MISC_MUX_QE_TDM); + printf("QECSR : 0x%02x, mux to qe-tdm\n", + CPLD_READ(sfp_ctl_status)); + } /* Mask all CPLD interrupt sources, except QSGMII interrupts */ if (CPLD_READ(sw_ver) < 0x03) { debug("CPLD SW version 0x%02x doesn't support int_mask\n", @@ -149,5 +157,7 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); #endif + if (hwconfig("qe-tdm")) + fdt_del_diu(blob); return 0; } -- 2.1.0.27.g96db324

2 1

[U-Boot] [RFC PATCH] x86: Support booting SeaBIOS
by Bin Meng 02 Nov '15

02 Nov '15

SeaBIOS is an open source implementation of a 16-bit X86 BIOS. It can run in an emulator or natively on X86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. No U-Boot native support there. Booting SeaBIOS is done via U-Boot's bootelf command. This is the initial attempt to support booting SeaBIOS from U-Boot. If the basic concept is good, I can spend time working on follow-on patches to enable BIOS tables as well as graphics support. One issue is that U-Boot x86 does not has a ROM file system like coreboot. This brings difficulities to pass PCI option ROM to SeaBIOS, if we don't modify SeaBIOS's source codes. Maybe we should promote CBFS in U-Boot x86? This is tested on an Intel Crown Bay board with VGA card, booting SeaBIOS then chain loading a GRUB on a USB drive, then Linux kernel finally. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/Kconfig | 10 ++++++++++ arch/x86/include/asm/tables.h | 29 +++++++++++++++++++++++++++++ arch/x86/lib/tables.c | 39 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5e42d7d..b432ff8 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -401,6 +401,16 @@ config PCIE_ECAM_SIZE so a default 0x10000000 size covers all of the 256 buses which is the maximum number of PCI buses as defined by the PCI specification. +config SEABIOS + bool "Support booting SeaBIOS" + help + SeaBIOS is an open source implementation of a 16-bit X86 BIOS. + It can run in an emulator or natively on X86 hardware with the use + of coreboot/U-Boot. By turning on this option, U-Boot prepares + all the configuration tables that are necessary to boot SeaBIOS. + + Check http://www.seabios.org/SeaBIOS for details. + source "arch/x86/lib/efi/Kconfig" endmenu diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index 0aa6d9b..a083cac 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -7,6 +7,32 @@ #ifndef _X86_TABLES_H_ #define _X86_TABLES_H_ +#ifdef CONFIG_SEABIOS + +#define CB_TAG_MEMORY 1 + +struct cb_header { + u8 signature[4]; + u32 header_bytes; + u32 header_checksum; + u32 table_bytes; + u32 table_checksum; + u32 table_entries; +}; + +struct cb_memory_range { + u64 start; + u64 size; + u32 type; +}; + +struct cb_memory { + u32 tag; + u32 size; + struct cb_memory_range map[0]; +}; +#endif + /* * All x86 tables happen to like the address range from 0xf0000 to 0x100000. * We use 0xf0000 as the starting address to store those tables, including @@ -14,6 +40,9 @@ */ #define ROM_TABLE_ADDR 0xf0000 +/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */ +#define CB_TABLE_ADDR 0x800 + /** * table_compute_checksum() - Compute a table checksum * diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index f15b2e2..5849b2f 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -9,6 +9,7 @@ #include <asm/mpspec.h> #include <asm/tables.h> #include <asm/acpi_table.h> +#include <asm/e820.h> u8 table_compute_checksum(void *v, int len) { @@ -36,6 +37,41 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad) dest[i] = pad; } +#ifdef CONFIG_SEABIOS +static u32 write_cb_tables(u32 addr) +{ + struct cb_header *cbh = (struct cb_header *)addr; + struct cb_memory *mem; + struct cb_memory_range *map; + struct e820entry entry[32]; + int num, i; + + memset(cbh, 0, sizeof(struct cb_header)); + strncpy((char *)cbh->signature, "LBIO", 4); + cbh->header_bytes = sizeof(struct cb_header); + + /* populate memory map table */ + mem = (struct cb_memory *)(cbh + 1); + mem->tag = CB_TAG_MEMORY; + map = mem->map; + num = install_e820_map(32, entry); + for (i = 0; i < num; i++) { + map->start = entry[i].addr; + map->size = entry[i].size; + map->type = entry[i].type; + map++; + } + mem->size = num * sizeof(struct cb_memory_range) + 8; + + cbh->table_bytes = mem->size; + cbh->table_checksum = compute_ip_checksum(mem, cbh->table_bytes); + cbh->table_entries = 1; + cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes); + + return (u32)map; +} +#endif + void write_tables(void) { u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR; @@ -56,4 +92,7 @@ void write_tables(void) rom_table_end = write_acpi_tables(rom_table_end); rom_table_end = ALIGN(rom_table_end, 1024); #endif +#ifdef CONFIG_SEABIOS + write_cb_tables(CB_TABLE_ADDR); +#endif } -- 1.8.2.1

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[U-Boot] [PATCH] gpio: atmel: Add the PIO4 driver support
by Wenyou Yang 02 Nov '15

02 Nov '15

The PIO4 is introduced from SAMA5D2, as a new version for Atmel PIO controller. Signed-off-by: Wenyou Yang <wenyou.yang(a)atmel.com> --- arch/arm/mach-at91/include/mach/atmel_pio4.h | 48 +++++ drivers/gpio/Kconfig | 11 + drivers/gpio/Makefile | 1 + drivers/gpio/atmel_pio4.c | 278 ++++++++++++++++++++++++++ 4 files changed, 338 insertions(+) create mode 100644 arch/arm/mach-at91/include/mach/atmel_pio4.h create mode 100644 drivers/gpio/atmel_pio4.c diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h new file mode 100644 index 0000000..5748da6 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2015 Atmel Corporation. + * Wenyou Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ATMEL_PIO4_H +#define __ATMEL_PIO4_H + +#ifndef __ASSEMBLY__ + +struct atmel_pio4_port { + u32 mskr; /* 0x00 PIO Mask Register */ + u32 cfgr; /* 0x04 PIO Configuration Register */ + u32 pdsr; /* 0x08 PIO Pin Data Status Register */ + u32 locksr; /* 0x0C PIO Lock Status Register */ + u32 sodr; /* 0x10 PIO Set Output Data Register */ + u32 codr; /* 0x14 PIO Clear Output Data Register */ + u32 odsr; /* 0x18 PIO Output Data Status Register */ + u32 reserved0; + u32 ier; /* 0x20 PIO Interrupt Enable Register */ + u32 idr; /* 0x24 PIO Interrupt Disable Register */ + u32 imr; /* 0x28 PIO Interrupt Mask Register */ + u32 isr; /* 0x2C PIO Interrupt Status Register */ + u32 reserved1[3]; + u32 iofr; /* 0x3C PIO I/O Freeze Register */ +}; + +#endif + +#define AT91_PIO_PORTA 0x0 +#define AT91_PIO_PORTB 0x1 +#define AT91_PIO_PORTC 0x2 +#define AT91_PIO_PORTD 0x3 + +int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup); +int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup); +void atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value); +u32 atmel_pio4_get_pio_input(u32 port, u32 pin); + +#endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ef57a89..ddc47c6 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -21,6 +21,17 @@ config DWAPB_GPIO help Support for the Designware APB GPIO driver. +config ATMEL_PIO4 + bool "ATMEL PIO4 driver" + depends on DM + default n + help + Say yes here to support the Atmel PIO4 driver. + The PIO4 is new version of Atmel PIO controller, which manages + up to 128 fully programmable input/output lines. Each I/O line + may be dedicated as a general purpose I/O or be assigned to + a function of an embedded peripheral. + config LPC32XX_GPIO bool "LPC32XX GPIO driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index c58aa4d..fb4fd25 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -12,6 +12,7 @@ endif obj-$(CONFIG_DM_GPIO) += gpio-uclass.o obj-$(CONFIG_AT91_GPIO) += at91_gpio.o +obj-$(CONFIG_ATMEL_PIO4) += atmel_pio4.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c new file mode 100644 index 0000000..21095ce --- /dev/null +++ b/drivers/gpio/atmel_pio4.c @@ -0,0 +1,278 @@ +/* + * Atmel PIO4 device driver + * + * Copyright (C) 2015 Atmel Corporation + * Wenyou.Yang <wenyou.yang(a)atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dm.h> +#include <asm/arch/hardware.h> +#include <mach/gpio.h> +#include <mach/atmel_pio4.h> + +#define ATMEL_PIO4_PINS_PER_BANK 32 + +/* + * Register Field Definitions + */ +#define ATMEL_PIO4_CFGR_FUNC (0x07 << 0) +#define ATMEL_PIO4_CFGR_FUNC_GPIO (0x0 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_A (0x1 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_B (0x2 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_C (0x3 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_D (0x4 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_E (0x5 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_F (0x6 << 0) +#define ATMEL_PIO4_CFGR_FUNC_PERIPH_G (0x7 << 0) +#define ATMEL_PIO4_CFGR_DIR (0x01 << 8) +#define ATMEL_PIO4_CFGR_PUEN (0x01 << 9) +#define ATMEL_PIO4_CFGR_PDEN (0x01 << 10) +#define ATMEL_PIO4_CFGR_IFEN (0x01 << 12) +#define ATMEL_PIO4_CFGR_IFSCEN (0x01 << 13) +#define ATMEL_PIO4_CFGR_OPD (0x01 << 14) +#define ATMEL_PIO4_CFGR_SCHMITT (0x01 << 15) +#define ATMEL_PIO4_CFGR_DRVSTR (0x03 << 16) +#define ATMEL_PIO4_CFGR_DRVSTR_HIGH (0x00 << 16) +#define ATMEL_PIO4_CFGR_DRVSTR_MEDIUM (0x01 << 16) +#define ATMEL_PIO4_CFGR_DRVSTR_LOW (0x02 << 16) +#define ATMEL_PIO4_CFGR_EVTSEL (0x07 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_FALLING (0x00 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_RISING (0x01 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_BOTH (0x02 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_LOW (0x03 << 24) +#define ATMEL_PIO4_CFGR_EVTSEL_HIGH (0x04 << 24) +#define ATMEL_PIO4_CFGR_PCFS (0x01 << 29) +#define ATMEL_PIO4_CFGR_ICFS (0x01 << 30) +#define ATMEL_PIO4_CFGR_TAMPEN (0x01 << 31) + +static struct atmel_pio4_port *atmel_pio4_port_base(u32 port) +{ + struct atmel_pio4_port *base = NULL; + + switch (port) { + case AT91_PIO_PORTA: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA; + break; + case AT91_PIO_PORTB: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB; + break; + case AT91_PIO_PORTC: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC; + break; + case AT91_PIO_PORTD: + base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD; + break; + default: + printf("Error: Atmel PIO4: Failed to get PIO base!\n"); + break; + } + + return base; +} + +static int atmel_pio4_config_io_func(u32 port, u32 pin, + u32 func, u32 use_pullup) +{ + struct atmel_pio4_port *port_base; + u32 reg, mask; + + if (pin >= ATMEL_PIO4_PINS_PER_BANK) + return -1; + + port_base = atmel_pio4_port_base(port); + mask = 1 << pin; + reg = func; + reg |= use_pullup ? ATMEL_PIO4_CFGR_PUEN : 0; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + return 0; +} + +int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_GPIO, + use_pullup); +} + +int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_A, + use_pullup); +} + +int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_B, + use_pullup); +} + +int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_C, + use_pullup); +} + +int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_D, + use_pullup); +} + +int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_E, + use_pullup); +} + +int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_F, + use_pullup); +} + +int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup) +{ + return atmel_pio4_config_io_func(port, pin, + ATMEL_PIO4_CFGR_FUNC_PERIPH_G, + use_pullup); +} + +void atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value) +{ + struct atmel_pio4_port *port_base; + u32 reg, mask; + + port_base = atmel_pio4_port_base(port); + mask = 0x01 << pin; + reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + if (value) + writel(mask, &port_base->sodr); + else + writel(mask, &port_base->codr); +} + +u32 atmel_pio4_get_pio_input(u32 port, u32 pin) +{ + struct atmel_pio4_port *port_base; + u32 reg, mask; + + port_base = atmel_pio4_port_base(port); + mask = 0x01 << pin; + reg = ATMEL_PIO4_CFGR_FUNC_GPIO; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + return (readl(&port_base->pdsr) & mask) ? 1 : 0; +} + +#ifdef CONFIG_DM_GPIO +static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + return 0; +} + +static int atmel_pio4_direction_output(struct udevice *dev, + unsigned offset, int value) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR; + + writel(mask, &port_base->mskr); + writel(reg, &port_base->cfgr); + + if (value) + writel(mask, &port_base->sodr); + else + writel(mask, &port_base->codr); + + return 0; +} + +static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + + return (readl(&port_base->pdsr) & mask) ? 1 : 0; +} + +static int atmel_pio4_set_value(struct udevice *dev, + unsigned offset, int value) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + + if (value) + writel(mask, &port_base->sodr); + else + writel(mask, &port_base->codr); + + return 0; +} + +static int atmel_pio4_get_function(struct udevice *dev, unsigned offset) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; + u32 mask = 0x01 << offset; + + writel(mask, &port_base->mskr); + + return (readl(&port_base->cfgr) & + ATMEL_PIO4_CFGR_DIR) ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +static const struct dm_gpio_ops atmel_pio4_ops = { + .direction_input = atmel_pio4_direction_input, + .direction_output = atmel_pio4_direction_output, + .get_value = atmel_pio4_get_value, + .set_value = atmel_pio4_set_value, + .get_function = atmel_pio4_get_function, +}; + +static int atmel_pio4_probe(struct udevice *dev) +{ + struct at91_port_platdata *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + uc_priv->bank_name = plat->bank_name; + uc_priv->gpio_count = ATMEL_PIO4_PINS_PER_BANK; + + return 0; +} + +U_BOOT_DRIVER(gpio_atmel_pio4) = { + .name = "gpio_atmel_pio4", + .id = UCLASS_GPIO, + .ops = &atmel_pio4_ops, + .probe = atmel_pio4_probe, +}; +#endif -- 1.7.9.5

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[U-Boot] [PATCH 00/28] dm: input: Move keyboard drivers to driver model
by Simon Glass 30 Oct '15

30 Oct '15

This series adds a new uclass for keyboards and converts some drivers over to use it. This series includes some work to remove code duplication in the keyboard drivers by updating them to use the input library (input.c). This unifies the keycode decoding logic in one place. In order to do this some enhancements are needed to the input library and these are also included. The cros_ec and tegra_kbc drivers are converted to use driver model. The i8042 driver is converted also, after various tidy-ups. The driver has some strange interactions with the cfb_console driver. This is removed in this series which is possible because the only user is x86. Some i8042 features have been dropped (the only deliberate one is the flashing cursor which does not seem to be used by any board). Also the i8042 driver currently has its own keycode decoding logic. This series removes it in favour of the input library. Therefore testing of this new driver would be appreciated. So far I have only been able to test on link, which does not have a full keyboard. Also, while German keyboard support is implemented, I am unable to test that either. These changes can be considered the first step towards moving stdio to driver model. For that to be useful we need to convert LCD and video also. Note: This series is missing the code to call the update_leds() method when the LEDs change. This needs to be added to keyboard_tstc() and keyboard_getc(). If someone is able to test this I can send a patch for that also. Simon Glass (28): dm: input: Create a keyboard uclass input: Add a device pointer to the input config input: Return -ENOSPC when there is not space input: Add the keycode translation tables separately cros_ec: Use udevice instead of cros_ec_dev for keyboard functions dm: stdio: Plumb in the new keyboard uclass dm: tegra: Convert keyboard driver to driver model dm: cros_ec: Convert cros_ec keyboard driver to driver model video: Drop unused console functions i8042: Use functions to handle register access i8042: Handle a duplicate power-on-reset response i8042: Adjust kbd_reset() to collect all failures i8042: Adjust keyboard init to assume success input: Correct keycode for Ctrl-Y input: Add a few more keyboard keycodes input: Add a function to add a keycode to the existing set input: Allow repeat filtering to be disabled input: Support the German keymap input: Adjust structure of code in process_modifier() input: Handle caps lock input: Allow updating of keyboard LEDs input: i8042: Convert to use the input library input: Add a Kconfig option for the i8042 keyboard x86: Add an i8042 device for boards that have it Drop CONFIG_ISA_KEYBOARD input: Convert i8042 to driver model video: input: Clean up after i8042 conversion input: Convert 'keyboard' driver to use input library README | 42 +-- arch/arm/Kconfig | 1 + arch/arm/mach-tegra/Kconfig | 1 + arch/sandbox/Kconfig | 3 + arch/x86/Kconfig | 6 + arch/x86/dts/bayleybay.dts | 1 + arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/keyboard.dtsi | 5 + board/kosagi/novena/novena.c | 1 + board/mpl/pip405/README | 4 - common/stdio.c | 31 +- common/usb_kbd.c | 6 - drivers/input/Kconfig | 19 ++ drivers/input/Makefile | 4 +- drivers/input/cros_ec_keyb.c | 147 ++++----- drivers/input/i8042.c | 632 ++++++++++----------------------------- drivers/input/input.c | 202 ++++++++++--- drivers/input/keyboard-uclass.c | 84 ++++++ drivers/input/keyboard.c | 290 +++--------------- drivers/input/tegra-kbc.c | 242 +++++++-------- drivers/misc/cros_ec.c | 14 +- drivers/video/cfb_console.c | 82 +---- include/configs/MIP405.h | 5 - include/configs/MPC8536DS.h | 1 - include/configs/MPC8544DS.h | 1 - include/configs/MPC8572DS.h | 1 - include/configs/MPC8641HPCN.h | 1 - include/configs/PIP405.h | 5 - include/configs/x86-chromebook.h | 2 +- include/configs/x86-common.h | 2 +- include/cros_ec.h | 4 +- include/fdtdec.h | 1 - include/i8042.h | 6 - include/input.h | 65 +++- include/keyboard.h | 83 +++++ lib/fdtdec.c | 1 - 36 files changed, 866 insertions(+), 1130 deletions(-) create mode 100644 arch/x86/dts/keyboard.dtsi create mode 100644 drivers/input/keyboard-uclass.c -- 2.6.0.rc0.131.gf624c3d

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