September 2015 - U-Boot

[U-Boot] [PATCH] x86: fsp: Report correct number of E820 table entries
by Bin Meng 24 Sep '15

24 Sep '15

The logic to calculate the number of E820 table entries is wrong when walking through the FSP HOB tables. Fix it. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Simon, I think we need get this fix in v2015.10 release. arch/x86/lib/fsp/fsp_dram.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 28552fa..e51ca96 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -72,9 +72,10 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) entries[num_entries].type = E820_RAM; else if (res_desc->type == RES_MEM_RESERVED) entries[num_entries].type = E820_RESERVED; + + num_entries++; } hdr = get_next_hob(hdr); - num_entries++; } /* Mark PCIe ECAM address range as reserved */ -- 1.8.2.1

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[U-Boot] [PATCH] arm: socfpga: Enable env support on MCV
by Marek Vasut 24 Sep '15

24 Sep '15

Enable support for env in eMMC on MCV SoM. Signed-off-by: Marek Vasut <marex(a)denx.de> --- include/configs/socfpga_mcvevk.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index ed9b5cc..65816a0 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -43,7 +43,11 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_ENV_IS_NOWHERE +/* Environment is in MMC */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ /* USB */ #ifdef CONFIG_CMD_USB -- 2.1.4

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[U-Boot] [PATCHv4] arm: socfpga: Enable saveenv for SD/MMC
by dinguyen＠opensource.altera.com 24 Sep '15

24 Sep '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Enable the able to save the environment variables when SD/MMC is used. Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- v4: Move ENV_IS_NOWHERE to the mcvevk board config file v3: Only define ENV_IS_NOWHERE if env is not in MMC, NAND, FAT, and SPI_FLASH v2: Move this option to be on a per-board basis Add config for socfpga_cyclone5 and socfpga_arria5 --- include/configs/socfpga_arria5_socdk.h | 4 ++++ include/configs/socfpga_common.h | 1 - include/configs/socfpga_cyclone5_socdk.h | 4 ++++ include/configs/socfpga_de0_nano_soc.h | 4 ++++ include/configs/socfpga_mcvevk.h | 2 ++ include/configs/socfpga_sockit.h | 4 ++++ 6 files changed, 18 insertions(+), 1 deletion(-) diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h index 3193684..b75b0a2 100644 --- a/include/configs/socfpga_arria5_socdk.h +++ b/include/configs/socfpga_arria5_socdk.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a2811ba..cece095 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -281,7 +281,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_ENV_IS_NOWHERE #define CONFIG_ENV_SIZE 4096 /* diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h index 9e733e5..fa67b25 100644 --- a/include/configs/socfpga_cyclone5_socdk.h +++ b/include/configs/socfpga_cyclone5_socdk.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h index 2508d03..191e1f7 100644 --- a/include/configs/socfpga_de0_nano_soc.h +++ b/include/configs/socfpga_de0_nano_soc.h @@ -55,6 +55,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index c5b4b4c..ed9b5cc 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -43,6 +43,8 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_ENV_IS_NOWHERE + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h index 747e988..6c71ef4 100644 --- a/include/configs/socfpga_sockit.h +++ b/include/configs/socfpga_sockit.h @@ -59,6 +59,10 @@ #endif +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS -- 2.4.5

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[U-Boot] [PATCH] nios2: convert altera_uart to driver model
by Thomas Chou 24 Sep '15

24 Sep '15

Convert altera_uart to driver model. Signed-off-by: Thomas Chou <thomas(a)wytron.com.tw> --- arch/nios2/dts/3c120_devboard.dts | 1 + drivers/serial/Kconfig | 6 ++ drivers/serial/altera_uart.c | 153 ++++++++++++++++++-------------------- include/configs/nios2-generic.h | 9 +-- 4 files changed, 79 insertions(+), 90 deletions(-) diff --git a/arch/nios2/dts/3c120_devboard.dts b/arch/nios2/dts/3c120_devboard.dts index 7f76328..2159cfc 100644 --- a/arch/nios2/dts/3c120_devboard.dts +++ b/arch/nios2/dts/3c120_devboard.dts @@ -130,6 +130,7 @@ interrupts = <10>; current-speed = <115200>; clock-frequency = <62500000>; + u-boot,dm-pre-reloc; }; }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5a8cb3a..34195e1 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -122,6 +122,12 @@ config ALTERA_JTAG_UART_BYPASS Bypass console output and keep going even if there is no JTAG terminal connection with the host. +config ALTERA_UART + bool "Altera UART support" + depends on NIOS2 && DM_SERIAL + help + Select this to enable an UART for Altera devices. + config ROCKCHIP_SERIAL bool "Rockchip on-chip UART support" depends on ARCH_UNIPHIER && DM_SERIAL diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c index d6b1484..8393d39 100644 --- a/drivers/serial/altera_uart.c +++ b/drivers/serial/altera_uart.c @@ -5,50 +5,31 @@ * SPDX-License-Identifier: GPL-2.0+ */ - #include <common.h> -#include <watchdog.h> +#include <dm.h> +#include <errno.h> #include <asm/io.h> #include <linux/compiler.h> #include <serial.h> -typedef volatile struct { +struct altera_uart_regs { unsigned rxdata; /* Rx data reg */ unsigned txdata; /* Tx data reg */ unsigned status; /* Status reg */ unsigned control; /* Control reg */ unsigned divisor; /* Baud rate divisor reg */ unsigned endofpacket; /* End-of-packet reg */ -} nios_uart_t; +}; + +struct altera_uart_platdata { + struct altera_uart_regs *reg; + unsigned int uartclk; +}; /* status register */ -#define NIOS_UART_PE (1 << 0) /* parity error */ -#define NIOS_UART_FE (1 << 1) /* frame error */ -#define NIOS_UART_BRK (1 << 2) /* break detect */ -#define NIOS_UART_ROE (1 << 3) /* rx overrun */ -#define NIOS_UART_TOE (1 << 4) /* tx overrun */ #define NIOS_UART_TMT (1 << 5) /* tx empty */ #define NIOS_UART_TRDY (1 << 6) /* tx ready */ #define NIOS_UART_RRDY (1 << 7) /* rx ready */ -#define NIOS_UART_E (1 << 8) /* exception */ -#define NIOS_UART_DCTS (1 << 10) /* cts change */ -#define NIOS_UART_CTS (1 << 11) /* cts */ -#define NIOS_UART_EOP (1 << 12) /* eop detected */ - -/* control register */ -#define NIOS_UART_IPE (1 << 0) /* parity error int ena*/ -#define NIOS_UART_IFE (1 << 1) /* frame error int ena */ -#define NIOS_UART_IBRK (1 << 2) /* break detect int ena */ -#define NIOS_UART_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_UART_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_UART_ITMT (1 << 5) /* tx empty int ena */ -#define NIOS_UART_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_UART_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_UART_IE (1 << 8) /* exception int ena */ -#define NIOS_UART_TBRK (1 << 9) /* transmit break */ -#define NIOS_UART_IDCTS (1 << 10) /* cts change int ena */ -#define NIOS_UART_RTS (1 << 11) /* rts */ -#define NIOS_UART_IEOP (1 << 12) /* eop detected int ena */ DECLARE_GLOBAL_DATA_PTR; @@ -56,82 +37,90 @@ DECLARE_GLOBAL_DATA_PTR; * UART the serial port *-----------------------------------------------------------------*/ -static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; +static int altera_uart_setbrg(struct udevice *dev, int baudrate) +{ + struct altera_uart_platdata *plat = dev->platdata; + struct altera_uart_regs *const regs = plat->reg; + unsigned div; -#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + div = (plat->uartclk / baudrate) - 1; + writel(div, &regs->divisor); -/* - * Everything's already setup for fixed-baud PTF - * assignment - */ -static void altera_serial_setbrg(void) -{ + return 0; } -static int altera_serial_init(void) +static int altera_uart_putc(struct udevice *dev, const char c) { - return 0; -} + struct altera_uart_platdata *plat = dev->platdata; + struct altera_uart_regs *const regs = plat->reg; -#else + if (!(readl(&regs->status) & NIOS_UART_TRDY)) + return -EAGAIN; -static void altera_serial_setbrg(void) -{ - unsigned div; + writel((unsigned char)c, &regs->txdata); - div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1; - writel (div, &uart->divisor); + return 0; } -static int altera_serial_init(void) +static int altera_uart_pending(struct udevice *dev, bool input) { - serial_setbrg(); - return 0; + struct altera_uart_platdata *plat = dev->platdata; + struct altera_uart_regs *const regs = plat->reg; + unsigned st = readl(&regs->status); + + if (input) + return (st & NIOS_UART_RRDY) ? 1 : 0; + else + return (st & NIOS_UART_TMT) ? 0 : 1; } -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - -/*----------------------------------------------------------------------- - * UART CONSOLE - *---------------------------------------------------------------------*/ -static void altera_serial_putc(char c) +static int altera_uart_getc(struct udevice *dev) { - if (c == '\n') - serial_putc ('\r'); - while ((readl (&uart->status) & NIOS_UART_TRDY) == 0) - WATCHDOG_RESET (); - writel ((unsigned char)c, &uart->txdata); + struct altera_uart_platdata *plat = dev->platdata; + struct altera_uart_regs *const regs = plat->reg; + + if (readl(&regs->status) & NIOS_UART_RRDY) + return (readl(&regs->rxdata) & 0xff); + else + return -EAGAIN; } -static int altera_serial_tstc(void) +static int altera_uart_probe(struct udevice *dev) { - return (readl (&uart->status) & NIOS_UART_RRDY); + return 0; } -static int altera_serial_getc(void) +static int altera_uart_ofdata_to_platdata(struct udevice *dev) { - while (serial_tstc () == 0) - WATCHDOG_RESET (); - return (readl (&uart->rxdata) & 0x00ff ); + struct altera_uart_platdata *plat = dev_get_platdata(dev); + + plat->reg = ioremap(dev_get_addr(dev), + sizeof(struct altera_uart_regs)); + plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 0); + + return 0; } -static struct serial_device altera_serial_drv = { - .name = "altera_serial", - .start = altera_serial_init, - .stop = NULL, - .setbrg = altera_serial_setbrg, - .putc = altera_serial_putc, - .puts = default_serial_puts, - .getc = altera_serial_getc, - .tstc = altera_serial_tstc, +static const struct dm_serial_ops altera_uart_ops = { + .putc = altera_uart_putc, + .pending = altera_uart_pending, + .getc = altera_uart_getc, + .setbrg = altera_uart_setbrg, }; -void altera_serial_initialize(void) -{ - serial_register(&altera_serial_drv); -} +static const struct udevice_id altera_uart_ids[] = { + { .compatible = "altr,uart-1.0", }, + { } +}; -__weak struct serial_device *default_serial_console(void) -{ - return &altera_serial_drv; -} +U_BOOT_DRIVER(altera_uart) = { + .name = "altera_uart", + .id = UCLASS_SERIAL, + .of_match = altera_uart_ids, + .ofdata_to_platdata = altera_uart_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_uart_platdata), + .probe = altera_uart_probe, + .ops = &altera_uart_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index bd6d45c..dcb90de 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -23,14 +23,7 @@ /* * SERIAL */ -#if defined(CONFIG_ALTERA_JTAG_UART) -#else -# define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_UART_BASE -#endif - -#define CONFIG_SYS_NIOS_FIXEDBAUD -#define CONFIG_BAUDRATE CONFIG_SYS_UART_BAUD -#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE} +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */ /* -- 2.1.4

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[U-Boot] [PATCH v3 0/2] nios2: convert altera_jtag_uart to driver model
by Thomas Chou 24 Sep '15

24 Sep '15

Update the dts and convert altera_jtag_uart to driver model. v2 add ioremap. make the change to dts compatible with linux. v3 use fdt address translation patch from Stefan Roese. fix watchdog and loop as Marek suggested. Thomas Chou (2): nios2: map physical address to uncached virtual address nios2: convert altera_jtag_uart to driver model arch/nios2/cpu/interrupts.c | 4 +- arch/nios2/dts/3c120_devboard.dts | 5 ++ arch/nios2/include/asm/io.h | 5 ++ configs/nios2-generic_defconfig | 3 + drivers/serial/Kconfig | 13 +++++ drivers/serial/altera_jtag_uart.c | 112 ++++++++++++++++++++++---------------- include/configs/nios2-generic.h | 3 - 7 files changed, 93 insertions(+), 52 deletions(-) -- 2.1.4

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[U-Boot] [PATCH 1/3] arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files
by dinguyen＠opensource.altera.com 23 Sep '15

23 Sep '15

From: Dinh Nguyen <dinguyen(a)opensource.altera.com> Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex(a)denx.de> Signed-off-by: Dinh Nguyen <dinguyen(a)opensource.altera.com> --- arch/arm/mach-socfpga/Kconfig | 4 ++-- include/configs/{socfpga_arria5.h => socfpga_arria5_socdk.h} | 0 include/configs/{socfpga_cyclone5.h => socfpga_cyclone5_socdk.h} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename include/configs/{socfpga_arria5.h => socfpga_arria5_socdk.h} (100%) rename include/configs/{socfpga_cyclone5.h => socfpga_cyclone5_socdk.h} (100%) diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 089280a..a413ea4 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -50,8 +50,8 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME - default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK - default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5_socdk.h similarity index 100% rename from include/configs/socfpga_arria5.h rename to include/configs/socfpga_arria5_socdk.h diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5_socdk.h similarity index 100% rename from include/configs/socfpga_cyclone5.h rename to include/configs/socfpga_cyclone5_socdk.h -- 2.4.5

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[U-Boot] [PATCH V2] ARM: tegra: expand all SPL sizes to be consistent
by Stephen Warren 23 Sep '15

23 Sep '15

From: Stephen Warren <swarren(a)nvidia.com> The size allocation for SPL is increased in all cases to match the already-expanded value used on Tegra124. This is both for general consistency, and because the seaboard build trips over the limit already when using one of the ARM compilers packaged with 14.04. For the record, when building Seaboard: arm-linux-gnueabi- SPL is too big by 0x36 bytes arm-linux-gnueabihf- SPL fits by 0x2a bytes arm-none-eabi- SPL fits by 0xa bytes (Those figures are from builds with the expanded SPL size allocation, relative to the non-expanded SPL size limit; they're better by about 6 bytes in the more constrained build.) Fixes: ba521994229c ("tegra124: Expand SPL space by 8KB") Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- v2: Fix "111" vs "110" type in the updated values. Now, the new values really are consistent with T124. --- include/configs/tegra114-common.h | 2 +- include/configs/tegra20-common.h | 2 +- include/configs/tegra210-common.h | 2 +- include/configs/tegra30-common.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 252e607d73f4..671071ba9810 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -34,7 +34,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 0841f33bfc9e..00e85c48c41b 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -32,7 +32,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x0010E000 +#define CONFIG_SYS_TEXT_BASE 0x00110000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index e6c815212d7b..8f35a7bf3dc6 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -26,7 +26,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* Generic Interrupt Controller */ #define CONFIG_GICV2 diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 3e8e3c1e5bd9..9afd86484bb2 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -31,7 +31,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80110000 /* * Memory layout for where various images get loaded by boot scripts: -- 1.9.1

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[U-Boot] [PATCH v6 0/5] spi: cadence_qspi: optimize & fix indirect rd-writes
by Vikas Manocha 23 Sep '15

23 Sep '15

This patchset: - fixes trigger base & transfer start address register programming. This fix superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger address setting". - adds support to get fifo width from device tree Changes in v6: - fixed binding for trigger-address. Changes in v5: - fixed compilation warnings. Changes in v4: - fifo-width & trigger address alligned to linux device tree binding. - removed un-necessary casting. - renaming of one parameter splitted to separate patch. - trigger address of socfpga reverted back to 0x0. - code formatting done to avoid checkpatch CHECKS. Changes in v3: - removed two patches which were bypassing the sram level check. - format string in patch corrected 3/4 - added commit message in patch 1/4 Changes in v2: - rebased to master. - removed patch "spi: cadence_qspi: read can be independent of fifo width", it was implemented in other patchset, in mainline now. Vikas Manocha (5): spi: cadence_qspi: move trigger base configuration in init spi: cadence_qspi: fix indirect read/write start address spi: cadence_qspi: fix base trigger address & transfer start address spi: cadence_qspi: rename ahbbase to flashbase for clarity spi: cadence_qspi: get fifo width from device tree arch/arm/dts/socfpga.dtsi | 2 ++ arch/arm/dts/stv0991.dts | 2 ++ drivers/spi/cadence_qspi.c | 14 ++++++++------ drivers/spi/cadence_qspi.h | 6 ++++-- drivers/spi/cadence_qspi_apb.c | 42 ++++++++++++++++------------------------ 5 files changed, 33 insertions(+), 33 deletions(-) -- 1.7.9.5

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[U-Boot] [PATCH] ARM: tegra: expand all SPL sizes to be consistent
by Stephen Warren 23 Sep '15

23 Sep '15

From: Stephen Warren <swarren(a)nvidia.com> The size allocation for SPL is increased in all cases to match the already-expanded value used on Tegra124. This is both for general consistency, and because the seaboard build trips over the limit already when using one of the ARM compilers packaged with 14.04. For the record, when building Seaboard: arm-linux-gnueabi- SPL is too big by 0x36 bytes arm-linux-gnueabihf- SPL fits by 0x2a bytes arm-none-eabi- SPL fits by 0xa bytes (Those figures are from builds with the expanded SPL size allocation, relative to the non-expanded SPL size limit; they're better by about 6 bytes in the more constrained build.) Fixes: ba521994229c ("tegra124: Expand SPL space by 8KB") Signed-off-by: Stephen Warren <swarren(a)nvidia.com> --- include/configs/tegra114-common.h | 2 +- include/configs/tegra20-common.h | 2 +- include/configs/tegra210-common.h | 2 +- include/configs/tegra30-common.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 252e607d73f4..33746cb90986 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -34,7 +34,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80111000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 0841f33bfc9e..45b0a1a61427 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -32,7 +32,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x0010E000 +#define CONFIG_SYS_TEXT_BASE 0x00111000 /* * Memory layout for where various images get loaded by boot scripts: diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index e6c815212d7b..aee26c14c272 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -26,7 +26,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80111000 /* Generic Interrupt Controller */ #define CONFIG_GICV2 diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 3e8e3c1e5bd9..b6952fdb1eee 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -31,7 +31,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_SYS_TEXT_BASE 0x8010E000 +#define CONFIG_SYS_TEXT_BASE 0x80111000 /* * Memory layout for where various images get loaded by boot scripts: -- 1.9.1

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[U-Boot] [PATCH 1/3] net: phy: Don't create phy device when there is no phy
by Bin Meng 23 Sep '15

23 Sep '15

In get_phy_device_by_mask(), when no phy is found, we should not create any phy device. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/net/phy/phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 65c731a..0d66e75 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -672,7 +672,8 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, return phydev; } printf("Phy %d not found\n", ffs(phy_mask) - 1); - return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface); + + return NULL; } /** -- 1.8.2.1

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