July 2015 - U-Boot

[U-Boot] [PATCH] usb: CONFIG_USB_FASTBOOT prefix replacement for consistency
by Paul Kocialkowski 15 Jul '15

15 Jul '15

FASTBOOT is defined both by CONFIG_USB_FUNCTION_FASTBOOT AND CONFIG_CMD_FASTBOOT, so it doesn't make much sense to have a CONFIG_USB_FASTBOOT prefix for fastboot-specific options, especially given that other config options for fastboot use the CONFIG_FASTBOOT prefix. This replaces the CONFIG_USB_FASTBOOT prefix with CONFIG_FASTBOOT, for consistency. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- README | 4 ++-- doc/README.android-fastboot | 4 ++-- drivers/usb/gadget/f_fastboot.c | 8 ++++---- include/configs/am335x_evm.h | 4 ++-- include/configs/bav335x.h | 4 ++-- include/configs/dra7xx_evm.h | 4 ++-- include/configs/nitrogen6x.h | 4 ++-- include/configs/omap3_beagle.h | 4 ++-- 8 files changed, 18 insertions(+), 18 deletions(-) diff --git a/README b/README index ab171f9..c871e7c 100644 --- a/README +++ b/README @@ -1730,12 +1730,12 @@ The following options need to be configured: This enables support for booting images which use the Android image format header. - CONFIG_USB_FASTBOOT_BUF_ADDR + CONFIG_FASTBOOT_BUF_ADDR The fastboot protocol requires a large memory buffer for downloads. Define this to the starting RAM address to use for downloaded images. - CONFIG_USB_FASTBOOT_BUF_SIZE + CONFIG_FASTBOOT_BUF_SIZE The fastboot protocol requires a large memory buffer for downloads. This buffer should be as large as possible for a platform. Define this to the size available RAM for fastboot. diff --git a/doc/README.android-fastboot b/doc/README.android-fastboot index 92f2897..ce12bc5 100644 --- a/doc/README.android-fastboot +++ b/doc/README.android-fastboot @@ -47,8 +47,8 @@ CONFIG_CMD_FASTBOOT and CONFIG_ANDROID_BOOT_IMAGE. The fastboot protocol requires a large memory buffer for downloads. This buffer should be as large as possible for a platform. The location of the -buffer and size are set with CONFIG_USB_FASTBOOT_BUF_ADDR and -CONFIG_USB_FASTBOOT_BUF_SIZE. +buffer and size are set with CONFIG_FASTBOOT_BUF_ADDR and +CONFIG_FASTBOOT_BUF_SIZE. Fastboot partition aliases can also be defined for devices where GPT limitations prevent user-friendly partition names such as "boot", "system" diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 60c846d..ca01a01 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -380,7 +380,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req) !strcmp_l1("max-download-size", cmd)) { char str_num[12]; - sprintf(str_num, "0x%08x", CONFIG_USB_FASTBOOT_BUF_SIZE); + sprintf(str_num, "0x%08x", CONFIG_FASTBOOT_BUF_SIZE); strncat(response, str_num, chars_left); } else if (!strcmp_l1("serialno", cmd)) { s = getenv("serial#"); @@ -430,7 +430,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req) if (buffer_size < transfer_size) transfer_size = buffer_size; - memcpy((void *)CONFIG_USB_FASTBOOT_BUF_ADDR + download_bytes, + memcpy((void *)CONFIG_FASTBOOT_BUF_ADDR + download_bytes, buffer, transfer_size); pre_dot_num = download_bytes / BYTES_PER_DOT; @@ -483,7 +483,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req) if (0 == download_size) { sprintf(response, "FAILdata invalid size"); - } else if (download_size > CONFIG_USB_FASTBOOT_BUF_SIZE) { + } else if (download_size > CONFIG_FASTBOOT_BUF_SIZE) { download_size = 0; sprintf(response, "FAILdata too large"); } else { @@ -544,7 +544,7 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req) strcpy(response, "FAILno flash device defined"); #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV - fb_mmc_flash_write(cmd, (void *)CONFIG_USB_FASTBOOT_BUF_ADDR, + fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR, download_bytes, response); #endif fastboot_tx_write_str(response); diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index abcdfda..633391b 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -301,8 +301,8 @@ #define CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_CMD_FASTBOOT #define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 /* To support eMMC booting */ #define CONFIG_STORAGE_EMMC diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h index 31b75f2..fa32fa4 100644 --- a/include/configs/bav335x.h +++ b/include/configs/bav335x.h @@ -458,8 +458,8 @@ DEFAULT_LINUX_BOOT_ENV \ #define CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_CMD_FASTBOOT #define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 /* To support eMMC booting */ #define CONFIG_STORAGE_EMMC diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 9dd5577..334721e 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -92,8 +92,8 @@ #define CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_CMD_FASTBOOT #define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x2F000000 +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x2F000000 #define CONFIG_FASTBOOT_FLASH #define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 #endif diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 47239b1..3bb2e8f 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -349,7 +349,7 @@ #define CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_CMD_FASTBOOT #define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 59c780e..804e307 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -75,8 +75,8 @@ #define CONFIG_USB_FUNCTION_FASTBOOT #define CONFIG_CMD_FASTBOOT #define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000 +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 /* USB EHCI */ #define CONFIG_CMD_USB -- 1.9.1

1 1

[U-Boot] [PATCH 0/5] Add support for Vybrid VF610-based PCM052
by Albert ARIBAUD (3ADEV) 15 Jul '15

15 Jul '15

This patch series introduces the vf610-based PCM052 target after a few fixes to the vf610 code. As indicated in the last patch in the series, there is a bug in the FEC whereby it wrongly reports having sent out a packet. This bug does not seem specific to PCM052, and it also seems to appear in the TimeSys U-Boot deliveries and also in Linux, with varying frequencies. NOTE: this series is not checkpatch-clean. It has: - 51 "line over 80 characters" warnings. These lines are in a block for which the line lenght limit was obviously waived. arch/arm/include/asm/arch-vf610/iomux-vf610.h has 5 of these; board/phytec/pcm052/pcm052.c has the remaining 50. - 1 "please write a paragraph that describes the config symbol fully" warning for arch/arm/Kconfig. There are no such descriptions for any target in this file. - 1 "need consistent spacing around '|' (ctx:WxV)" error in board/phytec/pcm052/pcm052.c at line 98. It seems spurious to me, as this construct has the exact same spacing as all others in the file. Albert ARIBAUD (3ADEV) (5): net: fec_mxc: remove useless struct nbuf vf610: refactor DDRMC code i2c: fix vf610 support tools: mkimage: fix imximage header size vf610: add support for Phytec PCM052 arch/arm/Kconfig | 5 + arch/arm/imx-common/ddrmc-vf610.c | 239 +++--------- arch/arm/include/asm/arch-vf610/crm_regs.h | 3 + arch/arm/include/asm/arch-vf610/ddrmc-vf610.h | 60 +-- arch/arm/include/asm/arch-vf610/imx-regs.h | 3 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 11 +- arch/arm/include/asm/imx-common/iomux-v3.h | 2 + board/freescale/vf610twr/vf610twr.c | 181 ++++++--- board/phytec/pcm052/Kconfig | 15 + board/phytec/pcm052/MAINTAINERS | 6 + board/phytec/pcm052/Makefile | 7 + board/phytec/pcm052/imximage.cfg | 17 + board/phytec/pcm052/pcm052.c | 530 ++++++++++++++++++++++++++ board/toradex/colibri_vf/colibri_vf.c | 169 ++++++-- configs/pcm052_defconfig | 6 + drivers/i2c/mxc_i2c.c | 3 +- drivers/net/fec_mxc.c | 20 +- include/configs/pcm052.h | 234 ++++++++++++ tools/imximage.h | 1 + 19 files changed, 1155 insertions(+), 357 deletions(-) create mode 100644 board/phytec/pcm052/Kconfig create mode 100644 board/phytec/pcm052/MAINTAINERS create mode 100644 board/phytec/pcm052/Makefile create mode 100644 board/phytec/pcm052/imximage.cfg create mode 100644 board/phytec/pcm052/pcm052.c create mode 100644 configs/pcm052_defconfig create mode 100644 include/configs/pcm052.h -- 2.1.0

7 23

[U-Boot] [PATCH v3] arm: mvebu: add Armada XP SATA support
by Anton Schubert 15 Jul '15

15 Jul '15

This patch initializes the SATA address windows on Armada XP and allows it to work with the existing mvsata_ide driver. It also adds the necessary configuration for the db-mv784mp-gp board. Signed-off-by: Anton Schubert <anton.schubert(a)gmx.de> Tested-by: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- Changes v3: - fix config formatting arch/arm/mach-mvebu/include/mach/soc.h | 1 + drivers/block/mvsata_ide.c | 41 ++++++++++++++++++++++++++++++++++ include/configs/db-mv784mp-gp.h | 29 ++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1aaea67..619bc7e 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -52,6 +52,7 @@ #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) +#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index e54d564..52c1602 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -13,6 +13,8 @@ #include <asm/arch/orion5x.h> #elif defined(CONFIG_KIRKWOOD) #include <asm/arch/soc.h> +#elif defined(CONFIG_ARMADA_XP) +#include <linux/mbus.h> #endif /* SATA port registers */ @@ -90,6 +92,41 @@ struct mvsata_port_registers { #define MVSATA_STATUS_TIMEOUT -1 /* + * Registers for SATA MBUS memory windows + */ + +#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4)) +#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4)) + +/* + * Initialize SATA memory windows for Armada XP + */ + +#ifdef CONFIG_ARMADA_XP +static void mvsata_ide_conf_mbus_windows(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + /* Disable windows, Set Size/Base to 0 */ + for (i = 0; i < 4; i++) { + writel(0, MVSATA_WIN_CONTROL(i)); + writel(0, MVSATA_WIN_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + MVSATA_WIN_CONTROL(i)); + writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); + } +} +#endif + +/* * Initialize one MVSATAHC port: set SControl's IPM to "always active" * and DET to "reset", then wait for SStatus's DET to become "device and * comm ok" (or time out after 50 us if no device), then set SControl's @@ -137,6 +174,10 @@ int ide_preinit(void) int ret = MVSATA_STATUS_TIMEOUT; int status; +#ifdef CONFIG_ARMADA_XP + mvsata_ide_conf_mbus_windows(); +#endif + /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) status = mvsata_ide_initialize_port( diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index c33a588..a78b639 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -27,6 +27,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV #define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE #define CONFIG_CMD_PING #define CONFIG_CMD_SF #define CONFIG_CMD_SPI @@ -60,6 +61,34 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST +/* SATA support */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE + +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO + +#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */ +#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 + +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 + +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS + +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 + +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_CMD_IDE */ + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- 2.3.6

1 0

[U-Boot] [PATCH v2] add Armada XP SATA support
by Anton Schubert 15 Jul '15

15 Jul '15

This patch initializes the SATA address windows on Armada XP and allows it to work with the existing mvsata_ide driver. It also adds the necessary configuration for the db-mv784mp-gp board. Changes v2: - add second bus offset - only allow one device per bus - enable CONFIG_CMD_IDE per default Signed-off-by: Anton Schubert <anton.schubert(a)gmx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- arch/arm/mach-mvebu/include/mach/soc.h | 1 + drivers/block/mvsata_ide.c | 41 ++++++++++++++++++++++++++++++++++ include/configs/db-mv784mp-gp.h | 29 ++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1aaea67..619bc7e 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -52,6 +52,7 @@ #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) +#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index e54d564..52c1602 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -13,6 +13,8 @@ #include <asm/arch/orion5x.h> #elif defined(CONFIG_KIRKWOOD) #include <asm/arch/soc.h> +#elif defined(CONFIG_ARMADA_XP) +#include <linux/mbus.h> #endif /* SATA port registers */ @@ -90,6 +92,41 @@ struct mvsata_port_registers { #define MVSATA_STATUS_TIMEOUT -1 /* + * Registers for SATA MBUS memory windows + */ + +#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4)) +#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4)) + +/* + * Initialize SATA memory windows for Armada XP + */ + +#ifdef CONFIG_ARMADA_XP +static void mvsata_ide_conf_mbus_windows(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + /* Disable windows, Set Size/Base to 0 */ + for (i = 0; i < 4; i++) { + writel(0, MVSATA_WIN_CONTROL(i)); + writel(0, MVSATA_WIN_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + MVSATA_WIN_CONTROL(i)); + writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); + } +} +#endif + +/* * Initialize one MVSATAHC port: set SControl's IPM to "always active" * and DET to "reset", then wait for SStatus's DET to become "device and * comm ok" (or time out after 50 us if no device), then set SControl's @@ -137,6 +174,10 @@ int ide_preinit(void) int ret = MVSATA_STATUS_TIMEOUT; int status; +#ifdef CONFIG_ARMADA_XP + mvsata_ide_conf_mbus_windows(); +#endif + /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) status = mvsata_ide_initialize_port( diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index c33a588..0fdf3a5 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -32,6 +32,7 @@ #define CONFIG_CMD_SPI #define CONFIG_CMD_TFTPPUT #define CONFIG_CMD_TIME +#define CONFIG_CMD_IDE /* I2C */ #define CONFIG_SYS_I2C @@ -60,6 +61,34 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST +/* SATA support */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE + +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO + +#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for normal register accesses*/ +#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 + +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 + +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS + +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 + +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_CMD_IDE */ + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- 2.3.6

3 2

[U-Boot] [PATCH v2 00/40] ARM: tegra: Add PCIe support
by Thierry Reding 15 Jul '15

15 Jul '15

From: Thierry Reding <treding(a)nvidia.com> This series adds PCIe support for Tegra20, Tegra30 and Tegra124. The size is mostly due to the large number of infrastructure that's added (libfdt, Tegra specific drivers required by the PCIe driver). In this version I've included all patches that were previously split into three separate series. Spreading them over multiple series is probably not worth it since there might be some dependencies between them and only the end result gives a completely working setup. Patch 1 adds a %pa modifier to printf() to print physical addresses. This is required to allow code to output such addresses irrespective of whether a 64 bit or 32 bit architecture is built for. Patches 2-7 add various FDT helpers to make it easier to parse complex device trees. Patch 8 is a minor cleanup to the PCI command that prevents a spew of error messages if a bus does not exist. Patch 9 modifies the PCI enumeration code to honor theh restrictions encoded within a host controller driver's pci_ski_dev() implementation. This is required to prevent exceptions from the NVIDIA Tegra PCIe controller. Patch 10 imports the pr_fmt() macro used within the Linux kernel to reduce the number of characters consumed by literal strings by allowing a source file to specify a prefix or suffix that should be applied to all format strings in the file. It is currently used by the debug() and error() macros. Patches 11-14 are some cleanup and refactoring of I2C core code, the addition of a higher level API that makes it easier for I2C client drivers to talk to devices. The Tegra I2C driver now implements i2c_get_bus_num_fdt() to obtain bus numbers corresponding to a DT node. Patch 15 implements a driver for the AS3722 PMIC used on the Venice2 and Jetson TK1 boards. Patches 16-21 are preparatory work for the Tegra PCIe controller. They add missing clock driver functionality as well as drivers for the Tegra powergate and XUSB pad controller blocks. Patch 22 adds the PCIe controller driver for Tegra20, Tegra30 and Tegra124. Device tree nodes and configurations options to enable PCIe on the TrimSlice (Tegra20), Beaver, Cardhu (Tegra30) and Jetson TK1 (Tegra124) boards are added in patches 23-31. Patches 32-35 implement non-cached memory support that will be used in the last batch of patches to implement more reliable packet transfers in the r8169 driver. Patch 36 enables non-cached memory support on Tegra. Finally, patches 37-40 implement non-cached memory support and various fixes in the r8169 driver and add support for the revision of the NIC found on the Jetson TK1. The above boards all have an ethernet NIC connected to PCIe, which is what I tested with. Thierry Reding (40): vsprintf: Add modifier for phys_addr_t fdt: Add a function to count strings fdt: Add a function to get the index of a string fdt: Add functions to retrieve strings fdt: Add resource parsing functions fdt: Add a function to return PCI BDF triplet fdt: Add a subnodes iterator macro pci: Abort early if bus does not exist pci: Honour pci_skip_dev() Add pr_fmt() macro i2c: Initialize the correct bus i2c: Refactor adapter initialization i2c: Add high-level API i2c: tegra: Implement i2c_get_bus_num_fdt() power: Add AMS AS3722 PMIC support ARM: tegra: Implement tegra_plle_enable() ARM: tegra: Provide PCIEXCLK reset ID ARM: tegra: Implement powergate support ARM: tegra: Implement XUSB pad controller ARM: tegra: Add XUSB pad controller on Tegra124 ARM: tegra: Enable XUSB pad controller on Jetson TK1 pci: tegra: Add Tegra PCIe driver ARM: tegra: Add Tegra20 PCIe device tree node ARM: tegra: Enable PCIe on TrimSlice ARM: tegra: Add GIC for Tegra30 ARM: tegra: Add Tegra30 PCIe device tree node ARM: tegra: Enable PCIe on Cardhu ARM: tegra: Enable PCIe on Beaver ARM: tegra: Add GIC for Tegra124 ARM: tegra: Add Tegra124 PCIe device tree node ARM: tegra: Enable PCIe on Jetson TK1 ARM: cache_v7: Various minor cleanups ARM: cache-cp15: Use more accurate types malloc: Output region when debugging ARM: Implement non-cached memory support ARM: tegra: Enable non-cached memory net: rtl8169: Honor CONFIG_SYS_RX_ETH_BUFFER net: rtl8169: Properly align buffers net: rtl8169: Use non-cached memory if available net: rtl8169: Add support for RTL-8168/8111g README | 19 + arch/arm/cpu/armv7/cache_v7.c | 14 +- arch/arm/cpu/tegra-common/Makefile | 2 + arch/arm/cpu/tegra-common/powergate.c | 102 ++ arch/arm/cpu/tegra-common/xusb-padctl.c | 39 + arch/arm/cpu/tegra124-common/Makefile | 1 + arch/arm/cpu/tegra124-common/clock.c | 109 +++ arch/arm/cpu/tegra124-common/xusb-padctl.c | 716 ++++++++++++++ arch/arm/cpu/tegra20-common/clock.c | 141 ++- arch/arm/cpu/tegra30-common/clock.c | 155 +++ arch/arm/dts/tegra124-jetson-tk1.dts | 373 +++++++ arch/arm/dts/tegra124.dtsi | 90 ++ arch/arm/dts/tegra20-trimslice.dts | 69 ++ arch/arm/dts/tegra20.dtsi | 60 ++ arch/arm/dts/tegra30-beaver.dts | 245 +++++ arch/arm/dts/tegra30-cardhu.dts | 362 +++++++ arch/arm/dts/tegra30.dtsi | 84 ++ arch/arm/include/asm/arch-tegra/powergate.h | 38 + arch/arm/include/asm/arch-tegra/xusb-padctl.h | 24 + arch/arm/include/asm/arch-tegra114/powergate.h | 6 + arch/arm/include/asm/arch-tegra124/clock.h | 2 + arch/arm/include/asm/arch-tegra124/powergate.h | 6 + arch/arm/include/asm/arch-tegra20/clock-tables.h | 2 +- arch/arm/include/asm/arch-tegra20/clock.h | 2 + arch/arm/include/asm/arch-tegra20/powergate.h | 6 + arch/arm/include/asm/arch-tegra30/clock.h | 2 + arch/arm/include/asm/arch-tegra30/powergate.h | 6 + arch/arm/include/asm/system.h | 7 +- arch/arm/lib/cache-cp15.c | 6 +- arch/arm/lib/cache.c | 42 + board/compulab/trimslice/trimslice.c | 8 + board/nvidia/cardhu/cardhu.c | 56 ++ board/nvidia/common/board.c | 3 + board/nvidia/jetson-tk1/jetson-tk1.c | 52 + common/board_r.c | 11 + common/cmd_pci.c | 7 + common/dlmalloc.c | 3 + drivers/i2c/i2c_core.c | 80 +- drivers/i2c/tegra_i2c.c | 13 + drivers/net/rtl8169.c | 127 ++- drivers/pci/Makefile | 1 + drivers/pci/pci.c | 3 + drivers/pci/pci_tegra.c | 1143 ++++++++++++++++++++++ drivers/power/Makefile | 1 + drivers/power/as3722.c | 300 ++++++ include/common.h | 14 +- include/configs/beaver.h | 10 + include/configs/cardhu.h | 10 + include/configs/jetson-tk1.h | 13 + include/configs/tegra-common.h | 1 + include/configs/trimslice.h | 10 + include/dt-bindings/clock/tegra124-car.h | 341 +++++++ include/dt-bindings/clock/tegra20-car.h | 158 +++ include/dt-bindings/clock/tegra30-car.h | 265 +++++ include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 + include/fdtdec.h | 69 ++ include/i2c.h | 96 ++ include/libfdt.h | 72 ++ include/pci.h | 1 + include/power/as3722.h | 27 + lib/fdtdec.c | 76 ++ lib/libfdt/fdt_ro.c | 76 ++ lib/vsprintf.c | 16 +- 63 files changed, 5736 insertions(+), 64 deletions(-) create mode 100644 arch/arm/cpu/tegra-common/powergate.c create mode 100644 arch/arm/cpu/tegra-common/xusb-padctl.c create mode 100644 arch/arm/cpu/tegra124-common/xusb-padctl.c create mode 100644 arch/arm/include/asm/arch-tegra/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra/xusb-padctl.h create mode 100644 arch/arm/include/asm/arch-tegra114/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra124/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra20/powergate.h create mode 100644 arch/arm/include/asm/arch-tegra30/powergate.h create mode 100644 drivers/pci/pci_tegra.c create mode 100644 drivers/power/as3722.c create mode 100644 include/dt-bindings/clock/tegra124-car.h create mode 100644 include/dt-bindings/clock/tegra20-car.h create mode 100644 include/dt-bindings/clock/tegra30-car.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h create mode 100644 include/power/as3722.h -- 2.0.4

7 103

[U-Boot] [PATCH] arm: mvebu: add Armada XP SATA support
by Anton Schubert 15 Jul '15

15 Jul '15

This patch initializes the SATA address windows on Armada XP and allows it to work with the existing mvsata_ide driver. It also adds the necessary configuration for the db-mv784mp-gp board. Signed-off-by: Anton Schubert <anton.schubert(a)gmx.de> Cc: Stefan Roese <sr(a)denx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- arch/arm/mach-mvebu/include/mach/soc.h | 1 + drivers/block/mvsata_ide.c | 41 ++++++++++++++++++++++++++++++++++ include/configs/db-mv784mp-gp.h | 27 ++++++++++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1aaea67..619bc7e 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -52,6 +52,7 @@ #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) +#define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) #define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index e54d564..52c1602 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -13,6 +13,8 @@ #include <asm/arch/orion5x.h> #elif defined(CONFIG_KIRKWOOD) #include <asm/arch/soc.h> +#elif defined(CONFIG_ARMADA_XP) +#include <linux/mbus.h> #endif /* SATA port registers */ @@ -90,6 +92,41 @@ struct mvsata_port_registers { #define MVSATA_STATUS_TIMEOUT -1 /* + * Registers for SATA MBUS memory windows + */ + +#define MVSATA_WIN_CONTROL(w) (MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4)) +#define MVSATA_WIN_BASE(w) (MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4)) + +/* + * Initialize SATA memory windows for Armada XP + */ + +#ifdef CONFIG_ARMADA_XP +static void mvsata_ide_conf_mbus_windows(void) +{ + const struct mbus_dram_target_info *dram; + int i; + + dram = mvebu_mbus_dram_info(); + + /* Disable windows, Set Size/Base to 0 */ + for (i = 0; i < 4; i++) { + writel(0, MVSATA_WIN_CONTROL(i)); + writel(0, MVSATA_WIN_BASE(i)); + } + + for (i = 0; i < dram->num_cs; i++) { + const struct mbus_dram_window *cs = dram->cs + i; + writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | + (dram->mbus_dram_target_id << 4) | 1, + MVSATA_WIN_CONTROL(i)); + writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i)); + } +} +#endif + +/* * Initialize one MVSATAHC port: set SControl's IPM to "always active" * and DET to "reset", then wait for SStatus's DET to become "device and * comm ok" (or time out after 50 us if no device), then set SControl's @@ -137,6 +174,10 @@ int ide_preinit(void) int ret = MVSATA_STATUS_TIMEOUT; int status; +#ifdef CONFIG_ARMADA_XP + mvsata_ide_conf_mbus_windows(); +#endif + /* Enable ATA port 0 (could be SATA port 0 or 1) if declared */ #if defined(CONFIG_SYS_ATA_IDE0_OFFSET) status = mvsata_ide_initialize_port( diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index c33a588..1a322d5 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -60,6 +60,33 @@ #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ #define CONFIG_SYS_ALT_MEMTEST +/* SATA support */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE + +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO + +#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for normal register accesses*/ +#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 + +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 + +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 4 + +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 + +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_CMD_IDE */ + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- 2.3.6

2 1

[U-Boot] [PATCH 09/10] x86: qemu: Enable writing MP table
by Bin Meng 15 Jul '15

15 Jul '15

Enable writing MP table for QEMU boads (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/qemu/pci.c | 34 +++++++++++++++++++++++++++++++--- configs/qemu-x86_defconfig | 1 + 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index ab93e76..acbd922 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +static bool i440fx; + void board_pci_setup_hose(struct pci_controller *hose) { hose->first_busno = 0; @@ -61,7 +63,8 @@ int board_pci_post_scan(struct pci_controller *hose) * PCI device ID. */ device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); - pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM; + i440fx = (device == PCI_DEVICE_ID_INTEL_82441); + pam = i440fx ? I440FX_PAM : Q35_PAM; /* * Initialize Programmable Attribute Map (PAM) Registers @@ -71,7 +74,7 @@ int board_pci_post_scan(struct pci_controller *hose) for (i = 0; i < PAM_NUM; i++) x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); - if (device == PCI_DEVICE_ID_INTEL_82441) { + if (i440fx) { /* * Enable legacy IDE I/O ports decode * @@ -97,10 +100,35 @@ int board_pci_post_scan(struct pci_controller *hose) * board, it shows as device 2, while for Q35 and ICH9 chipset board, * it shows as device 1. */ - vga = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_VGA : Q35_VGA; + vga = i440fx ? I440FX_VGA : Q35_VGA; start = get_timer(0); ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE); debug("BIOS ran in %lums\n", get_timer(start)); return ret; } + +#ifdef CONFIG_GENERATE_MP_TABLE +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + u8 irq; + + if (i440fx) { + /* + * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not + * connected to I/O APIC INTPIN#16-19. Instead they are routed + * to an irq number controled by the PIRQ routing register. + */ + irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE); + } else { + /* + * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. + * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. + */ + irq = pirq < 8 ? pirq + 16 : pirq + 12; + } + + return irq; +} +#endif diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 62c3f35..e579c36 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -3,6 +3,7 @@ CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx" CONFIG_SMP=y CONFIG_MAX_CPUS=2 CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y CONFIG_CMD_CPU=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set -- 1.8.2.1

1 0

[U-Boot] [PATCH 00/10] x86: Add MP support to QEMU
by Bin Meng 15 Jul '15

15 Jul '15

This patch series mainly add MP support to QEMU as well as some other necessary fixes for x86. Verified by booting Linux kernel on QEMU i440FX and Q35, and make sure I/O APIC interrupt is being used by the kernel with the help of MP table provided by U-Boot. This series is the prerequisite for the follow-up ACPI support which is currently being worked on by Saket. Bin Meng (10): x86: Change pci option rom area MTRR setting to cacheable x86: Enable DM RTC support for all x86 boards x86: pci: Assign pci irqs to all functions x86: pci: Do not assign irq 0 to pci device x86: mpspec: Allow platform to determine how PIRQ is connected to I/O APIC x86: mpspec: Move writing ISA interrupt entry after PCI x86: qemu: Enable I/O APIC chip select on PIIX3 x86: qemu: Add MP initialization x86: qemu: Enable writing MP table x86: qemu: Turn on PCIe ECAM address range decoding on Q35 arch/x86/cpu/cpu.c | 27 ++++++++++++++----- arch/x86/cpu/mp_init.c | 4 +++ arch/x86/cpu/pci.c | 29 ++++++++++++++------- arch/x86/cpu/qemu/Kconfig | 11 ++++++++ arch/x86/cpu/qemu/pci.c | 45 +++++++++++++++++++++++++++++--- arch/x86/dts/chromebook_link.dts | 1 + arch/x86/dts/chromebox_panther.dts | 1 + arch/x86/dts/galileo.dts | 1 + arch/x86/dts/minnowmax.dts | 1 + arch/x86/dts/qemu-x86_i440fx.dts | 21 +++++++++++++++ arch/x86/dts/qemu-x86_q35.dts | 21 +++++++++++++++ arch/x86/include/asm/arch-qemu/qemu.h | 10 ++++++- arch/x86/include/asm/mpspec.h | 17 ++++++++++++ arch/x86/include/asm/mtrr.h | 2 ++ arch/x86/include/asm/pci.h | 3 +-- arch/x86/lib/mpspec.c | 49 ++++++++++++++++++++++++++--------- arch/x86/lib/pirq_routing.c | 3 +-- configs/chromebook_link_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/galileo_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/qemu-x86_defconfig | 6 +++++ doc/README.x86 | 5 ++++ 23 files changed, 223 insertions(+), 38 deletions(-) -- 1.8.2.1

1 0

[U-Boot] [PATCH v4 0/8] omap-common: Common boot code OMAP3 support and SYS_BOOT-based fallback boot device
by Paul Kocialkowski 15 Jul '15

15 Jul '15

This looks good to me, please let me know if it can be merged before 2015.07 is released. Changes since v3: * Tested on the OMAP5 uEVM, adjusted SYS_BOOT interpretation. * Typo fixup, other minor cleanups. Changes since v2: * ifdef save_boot_params definition and save_omap_boot_params calls with CONFIG_SPL to only use all this when U-Boot is loaded from the U-Boot SPL. This was always the case on != omap3 omap platforms, but is no longer the case with omap3 support (since some devices like the RX-51 are OMAP HS and have proprietary bootloaders loading U-Boot, and might even need some specific code instead). The first part of this changeset introduces OMAP3 support for the common omap boot code, as well as a major cleanup of the common omap boot code. First, the omap_boot_parameters structure becomes platform-specific, since its definition differs a bit across omap platforms. The offsets are removed as well since it is U-Boot's coding style to use structures for mapping such kind of data (in the sense that it is similar to registers). It is correct to assume that romcode structure encoding is the same as U-Boot, given the description of these structures in the TRMs. The original address provided by the bootrom is passed to the U-Boot binary instead of a duplicate of the structure stored in global data. This allows to have only the relevant (boot device and mode) information stored in global data. It is also expected that the address where the bootrom stores that information is not overridden by the U-Boot SPL or U-Boot. The save_omap_boot_params is expected to handle all special cases where the data provided by the bootrom cannot be used as-is, so that spl_boot_device and spl_boot_mode only return the data from global data. The second part of this changeset adds support for reading the SYS_BOOT pins on omap devices (no am33xx support yet) in order to fallback to the memory-preferred boot device described by the pins when peripheral booting is used. In particular, this allows loading the U-Boot SPL through either UART or USB and still having it to load U-Boot from memory when UART or USB are not valid boot devices. This whole changeset was build-tested on all omap boards (omap3, omap4, omap5, am33xx) and tested at run-time on a single omap3 device only. I would be very glad to see board maintainers give a go at the changeset before it gets merged, especially on devices like the Nokia RX-51 (N900) where some specific adaptation was needed.

3 23

[U-Boot] Pull request: u-boot-spi/master
by Jagan Teki 15 Jul '15

15 Jul '15

Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit 891b487098ee2169a16b1bbb354aaef28aa90630: Merge branch 'master' of git://git.denx.de/u-boot-spi (2015-07-01 15:38:12 -0400) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 8097cba809d8c40d8fe72f792c7dc0644c845a32: spi: cadence_qspi: add device tree binding doc (2015-07-03 13:50:53 +0530) ---------------------------------------------------------------- Vikas Manocha (10): stv0991: enable saving enrironment in spi flash stv0991: move OF_CONTROL config to defconfig stv0991: remove define CONFIG_OF_SEPARATE from board file stv0991: configure clock & pad muxing for qspi stv0991: enable cadence qspi controller & spi flash stv0991: configure device tree for cadence qspi & flash spi: cadence_qspi: move the sram partition in init spi: cadence_qspi: get sram size from device tree spi: cadence_qspi: support FIFO width other than 4 bytes spi: cadence_qspi: add device tree binding doc arch/arm/Kconfig | 3 ++ arch/arm/cpu/armv7/stv0991/clock.c | 4 +- arch/arm/cpu/armv7/stv0991/pinmux.c | 5 ++ arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 30 +++++++++++ arch/arm/include/asm/arch-stv0991/stv0991_cgu.h | 15 ++++++ arch/arm/include/asm/arch-stv0991/stv0991_creg.h | 9 ++++ arch/arm/include/asm/arch-stv0991/stv0991_periph.h | 2 + board/st/stv0991/stv0991.c | 8 +++ configs/stv0991_defconfig | 2 +- doc/device-tree-bindings/spi/spi-cadence.txt | 28 ++++++++++ drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 62 +++++++++------------- include/configs/stv0991.h | 21 ++++++-- 15 files changed, 151 insertions(+), 41 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-cadence.txt

2 3