July 2015 - U-Boot

[U-Boot] Last call for patches for v2015.07
by Tom Rini 13 Jul '15

13 Jul '15

Hey all, I'm feeling good, I think, about releasing v2015.07. But before I tag things, are there outstanding patches people know about that must be in for an important fix? Thanks! -- Tom

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[U-Boot] [u-boot][PATCH] ARM: DRA7-evm: prevent DCAN1 _wait_target_disable failure in kernel
by Roger Quadros 13 Jul '15

13 Jul '15

If board is booted with transitions happening on DCAN1 pins then the following warning is seen in the kernel at boot when the hwmod layer initializes. "omap_hwmod: dcan1: _wait_target_disable failed" This is because DCAN1 module's SWAKEUP mechanism is broken and it fails to correctly turn OFF if it sees a transition on the DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode while enabling/disabling DCAN1 module. The hwmod layer enables and disables all modules at boot and we have no opportunity to put the DCAN1 pins in safe mode at that point. DCAN1 is not used by u-boot so it doesn't matter to it if these pins are in safe mode. The kernel driver correctly configures the right mode when DCAN1 is active. Signed-off-by: Roger Quadros <rogerq(a)ti.com> --- board/ti/dra7xx/mux_data.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index c9301a5..91e00b9 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -358,7 +358,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {SPI2_D1, (M1 | PIN_INPUT_SLEW)}, /* spi2_d1.uart3_txd */ {SPI2_D0, (M1 | PIN_INPUT_SLEW)}, /* spi2_d0.uart3_ctsn */ {SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.uart3_rtsn */ - {DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */ + {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ {DCAN1_RX, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* dcan1_rx.gpio1_15 */ {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */ {UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_txd.uart1_txd */ @@ -370,7 +370,7 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = { {UART2_RTSN, (M3 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.mmc4_dat3 */ {I2C2_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_sda.i2c2_sda */ {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c2_scl.i2c2_scl */ - {WAKEUP0, (M1 | PIN_OUTPUT)}, /* Wakeup0.dcan1_rx */ + {WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */ {WAKEUP2, (M14 | PIN_OUTPUT)}, /* Wakeup2.gpio1_2 */ }; -- 2.1.4

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[U-Boot] [PATCH] libfdt: fix return code of fdt_get_string_index()
by Masahiro Yamada 13 Jul '15

13 Jul '15

As mentioned in the comment block in include/libfdt.h, fdt_get_string_index() is supposed to return a negative value on error. BTW, looks like this function was added only for U-Boot in spite of its location, so we need not send a bug report back to the DTC ML. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> Fixes: commit 5094eb408a5d ("fdt: Add functions to retrieve strings") --- lib/libfdt/fdt_ro.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index 44fc0aa..38bfcbd 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -577,7 +577,7 @@ int fdt_get_string_index(const void *fdt, int node, const char *property, index--; } - return FDT_ERR_NOTFOUND; + return -FDT_ERR_NOTFOUND; } int fdt_get_string(const void *fdt, int node, const char *property, -- 1.9.1

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[U-Boot] [PATCH] Fix LS102xa timer setup to use 64-bit.
by Christopher Kilgour 13 Jul '15

13 Jul '15

Fix LS102xa timer configuration to ensure timer compare value is set to all-ones as a 64-bit number rather than a 32-bit number. When the 32-bit all-ones was used, this could result in a timer compare value of 2^32-1, which at 12.5 MHz will fire in ~344 seconds. If the operating system's timer support does not expect or handle the timer compare, it can lock up when the timer compare fires and never clears (in Linux this shows up as a stuck GIC 29). It's also possible to interactively work with u-boot for longer than 344 seconds, and have the timer compare silently fire in the background without impact on u-boot operation. However, as soon as the operating system enables interrupts, it can lock up. On embedded Linux without early console support, this can be a silent lockup without warning or diagnostic output. It's likely Freescale wanted to set the timer compare to the largest possible value of all-ones at 64-bits. Rather than 344 seconds, this would fire after ~47k years. Even though Linux systems are known for long uptimes, one assumes this is Freescale's intended, safe value. Signed-off-by: Christopher Kilgour <techie(a)whiterocker.com> Cc: York Sun <yorksun(a)freescale.com> --- arch/arm/cpu/armv7/ls102xa/timer.c | 7 ++++--- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c index 11b17b2..746bfc0 100644 --- a/arch/arm/cpu/armv7/ls102xa/timer.c +++ b/arch/arm/cpu/armv7/ls102xa/timer.c @@ -56,7 +56,8 @@ static inline unsigned long long us_to_tick(unsigned long long usec) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; - unsigned long ctrl, val, freq; + unsigned long ctrl, freq; + unsigned long long val64; /* Enable System Counter */ writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); @@ -69,8 +70,8 @@ int timer_init(void) asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); /* Set PL1 Physical Comp Value */ - val = TIMER_COMP_VAL; - asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val)); + val64 = TIMER_COMP_VAL; + asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val64)); gd->arch.tbl = 0; gd->arch.tbu = 0; diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index ee547fb..1f55655 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -31,7 +31,7 @@ #define RCWSR4_SRDS1_PRTCL_SHIFT 24 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000 -#define TIMER_COMP_VAL 0xffffffff +#define TIMER_COMP_VAL ((unsigned long long)(-1)) #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) -- 2.1.0

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[U-Boot] [PATCH V2 00/15] imx: Add i.MX6UL and basic board support
by Peng Fan 12 Jul '15

12 Jul '15

Add i.MX 6UltraLite support and include mx6ul_14x14_evk basic board support. i.MX 6UltraLite is a high performance, ultra-efficient processor family featuring an advanced implementation of a single Cortex-A7 core. This patch set is based on i.MX6QP patch v5 set: https://patchwork.ozlabs.org/patch/493961/ https://patchwork.ozlabs.org/patch/493962/ https://patchwork.ozlabs.org/patch/493963/ https://patchwork.ozlabs.org/patch/493964/ https://patchwork.ozlabs.org/patch/493965/ https://patchwork.ozlabs.org/patch/493966/ Changes v2: 1. refine commit msg 2. split CONFIG_SYS_CACHELINE_SIZE part into a single patch 3. discard system counter, default use GPT now. 4. SPL support Peng Fan (15): imx: mx6ul: Add i.MX6UL CPU type imx: mx6ul: Add pins IOMUX head file imx: mx6ul: Update imx registers head file imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL imx-common: timer: add i.MX6UL support imx: mx6ul remove errata for i.MX6UL imx:mx6ul add clock support imx: mx6ul select SYS_L2CACHE_OFF imx: mx6ul update soc related settings imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/UL mxc: gpio add i.MX6UL support mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6UL imx:mx6ul add dram spl configuration and header file imx: imx6_spl add mx6ul support imx: mx6ul_14x14_evk add basic board support arch/arm/Kconfig | 8 + arch/arm/cpu/armv7/mx6/Kconfig | 4 + arch/arm/cpu/armv7/mx6/clock.c | 151 +-- arch/arm/cpu/armv7/mx6/ddr.c | 61 +- arch/arm/cpu/armv7/mx6/soc.c | 9 +- arch/arm/imx-common/cpu.c | 2 + arch/arm/imx-common/timer.c | 8 +- arch/arm/include/asm/arch-imx/cpu.h | 3 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 79 +- arch/arm/include/asm/arch-mx6/imx-regs.h | 63 +- arch/arm/include/asm/arch-mx6/mx6-ddr.h | 45 + arch/arm/include/asm/arch-mx6/mx6-pins.h | 2 + arch/arm/include/asm/arch-mx6/mx6ul-ddr.h | 45 + arch/arm/include/asm/arch-mx6/mx6ul_pins.h | 1065 +++++++++++++++++++++ arch/arm/include/asm/imx-common/iomux-v3.h | 4 + board/freescale/mx6ul_14x14_evk/Kconfig | 15 + board/freescale/mx6ul_14x14_evk/MAINTAINERS | 6 + board/freescale/mx6ul_14x14_evk/Makefile | 6 + board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 636 ++++++++++++ configs/mx6ul_14x14_evk_defconfig | 4 + drivers/gpio/mxc_gpio.c | 4 + include/configs/imx6_spl.h | 2 +- include/configs/mx6_common.h | 6 +- include/configs/mx6ul_14x14_evk.h | 227 +++++ 24 files changed, 2321 insertions(+), 134 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul-ddr.h create mode 100644 arch/arm/include/asm/arch-mx6/mx6ul_pins.h create mode 100644 board/freescale/mx6ul_14x14_evk/Kconfig create mode 100644 board/freescale/mx6ul_14x14_evk/MAINTAINERS create mode 100644 board/freescale/mx6ul_14x14_evk/Makefile create mode 100644 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c create mode 100644 configs/mx6ul_14x14_evk_defconfig create mode 100644 include/configs/mx6ul_14x14_evk.h -- 1.8.4

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[U-Boot] [PATCH] common/lcd_console: fix console/logo regression
by Marcel Ziswiler 11 Jul '15

11 Jul '15

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> The following commit changed the order of the column vs. row parameter to the lcd_init_console() function but missed actually changing it as well the second time it is called from lcd_clear() which resulted in a garbled text console which this patch fixes. commit 604c7d4a5a3cf70949f6e6094bf0d52ee3b4804d common/lcd_console: introduce display/framebuffer rotation Tested on Colibri T20 with my latest assortment of tegra fixes/enhancements patch set. Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> --- common/lcd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index 5a52fe4..d29308a 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -234,8 +234,8 @@ void lcd_clear(void) lcd_logo(); #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) addr = (ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length; - lcd_init_console((void *)addr, panel_info.vl_row, - panel_info.vl_col, panel_info.vl_rot); + lcd_init_console((void *)addr, panel_info.vl_col, + panel_info.vl_row, panel_info.vl_rot); #endif lcd_sync(); } -- 1.9.3

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[U-Boot] [PATCH v2 05/11] x86: Setup fixed range MTRRs for legacy regions
by Bin Meng 11 Jul '15

11 Jul '15

We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: None arch/x86/cpu/cpu.c | 22 ++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 27 ++++++++++++++++----------- 2 files changed, 38 insertions(+), 11 deletions(-) diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index d108ee5..9afdafb 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -28,6 +28,8 @@ #include <asm/cpu.h> #include <asm/lapic.h> #include <asm/mp.h> +#include <asm/msr.h> +#include <asm/mtrr.h> #include <asm/post.h> #include <asm/processor.h> #include <asm/processor-flags.h> @@ -352,6 +354,26 @@ int x86_cpu_init_f(void) gd->arch.has_mtrr = has_mtrr(); } + /* Configure fixed range MTRRs for some legacy regions */ + if (gd->arch.has_mtrr) { + u64 mtrr_cap; + + mtrr_cap = native_read_msr(MTRR_CAP_MSR); + if (mtrr_cap & MTRR_CAP_FIX) { + /* Mark the VGA RAM area as uncacheable */ + native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0); + + /* Mark the PCI ROM area as uncacheable */ + native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0); + native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0); + native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0); + native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0); + + /* Enable the fixed range MTRRs */ + msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); + } + } + return 0; } diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 3ad617c..70762ee 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -21,6 +21,11 @@ #define MTRR_CAP_MSR 0x0fe #define MTRR_DEF_TYPE_MSR 0x2ff +#define MTRR_CAP_SMRR (1 << 11) +#define MTRR_CAP_WC (1 << 10) +#define MTRR_CAP_FIX (1 << 8) +#define MTRR_CAP_VCNT_MASK 0xff + #define MTRR_DEF_TYPE_EN (1 << 11) #define MTRR_DEF_TYPE_FIX_EN (1 << 10) @@ -38,17 +43,17 @@ #define RANGES_PER_FIXED_MTRR 8 #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) -#define MTRR_FIX_64K_00000_MSR 0x250 -#define MTRR_FIX_16K_80000_MSR 0x258 -#define MTRR_FIX_16K_A0000_MSR 0x259 -#define MTRR_FIX_4K_C0000_MSR 0x268 -#define MTRR_FIX_4K_C8000_MSR 0x269 -#define MTRR_FIX_4K_D0000_MSR 0x26a -#define MTRR_FIX_4K_D8000_MSR 0x26b -#define MTRR_FIX_4K_E0000_MSR 0x26c -#define MTRR_FIX_4K_E8000_MSR 0x26d -#define MTRR_FIX_4K_F0000_MSR 0x26e -#define MTRR_FIX_4K_F8000_MSR 0x26f +#define MTRR_FIX_64K_00000_MSR 0x250 +#define MTRR_FIX_16K_80000_MSR 0x258 +#define MTRR_FIX_16K_A0000_MSR 0x259 +#define MTRR_FIX_4K_C0000_MSR 0x268 +#define MTRR_FIX_4K_C8000_MSR 0x269 +#define MTRR_FIX_4K_D0000_MSR 0x26a +#define MTRR_FIX_4K_D8000_MSR 0x26b +#define MTRR_FIX_4K_E0000_MSR 0x26c +#define MTRR_FIX_4K_E8000_MSR 0x26d +#define MTRR_FIX_4K_F0000_MSR 0x26e +#define MTRR_FIX_4K_F8000_MSR 0x26f #if !defined(__ASSEMBLER__) -- 1.8.2.1

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[U-Boot] Please pull u-boot-marvell master
by Luka Perkov 10 Jul '15

10 Jul '15

Hi Tom, can you please pull this 10 patches from Stefan? The following changes since commit f3edfd30541d6f245d7dfa6fa7354cc916cc53e1: net: designware: Program MAC address to hardware after soft reset (2015-07-08 13:43:19 -0400) are available in the git repository at: git://git.denx.de/u-boot-marvell.git for you to fetch changes up to 59565736839108846d8dfa6782babfaefff6b58b: arm: mvebu: db-88f6820-gp: Add USB/EHCI support (2015-07-10 14:56:07 +0200) ---------------------------------------------------------------- Stefan Roese (10): arm: mvebu: db-88f6820-gp: Add MAINTAINERS file mmc: sdhci: Use timer based timeout detection in sdhci_send_command() mmc: sdhci.c: Add config option to use a fixed buffer for transfers arm: mvebu: Add SDIO/SDHCI support for Armada A38x arm: mvebu: db-88f6820-gp: Add MMC/SDIO support block: ahci: Don't enable port interrupts arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x arm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) support usb: Add EHCI support for Armada 38x (mvebu) arm: mvebu: db-88f6820-gp: Add USB/EHCI support arch/arm/mach-mvebu/cpu.c | 66 +++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 2 + arch/arm/mach-mvebu/include/mach/gpio.h | 10 +++++ arch/arm/mach-mvebu/include/mach/soc.h | 3 ++ board/Marvell/db-88f6820-gp/MAINTAINERS | 6 +++ drivers/block/ahci.c | 3 -- drivers/mmc/sdhci.c | 25 ++++++++++--- drivers/usb/host/ehci-marvell.c | 36 ++++++++++++++++++ include/configs/db-88f6820-gp.h | 41 ++++++++++++++++++++ 9 files changed, 184 insertions(+), 8 deletions(-) create mode 100644 arch/arm/mach-mvebu/include/mach/gpio.h create mode 100644 board/Marvell/db-88f6820-gp/MAINTAINERS Thanks, Luka

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[U-Boot] please pull u-boot-samsung master
by Minkyu Kang 10 Jul '15

10 Jul '15

Dear Tom, The following changes since commit f3edfd30541d6f245d7dfa6fa7354cc916cc53e1: net: designware: Program MAC address to hardware after soft reset (2015-07-08 13:43:19 -0400) are available in the git repository at: http://git.denx.de/u-boot-samsung for you to fetch changes up to 8fd3ec770c41115b95ca80f0f0ba344ac59dc293: exynos: i2c: Correct bug in pinmux selection (2015-07-10 21:13:48 +0900) ---------------------------------------------------------------- Minkyu Kang (1): arm: adds the status info for odroid-xu3 Simon Glass (1): exynos: i2c: Correct bug in pinmux selection board/samsung/smdk5420/MAINTAINERS | 1 + drivers/i2c/s3c24x0_i2c.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) -- Thanks, Minkyu Kang.

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[U-Boot] [PATCH] mtd: fix false positive "Offset exceeds device limit" error
by Masahiro Yamada 10 Jul '15

10 Jul '15

Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Signed-off-by: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/mtd/mtd_uboot.c | 5 +++-- include/linux/mtd/mtd.h | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index 7197007..c517b9c 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -43,7 +43,7 @@ static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size, } int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, - loff_t *maxsize, int devtype, int chipsize) + loff_t *maxsize, int devtype, uint64_t chipsize) { if (!str2off(arg, off)) return get_part(arg, idx, off, size, maxsize, devtype); @@ -59,7 +59,8 @@ int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, } int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, - loff_t *size, loff_t *maxsize, int devtype, int chipsize) + loff_t *size, loff_t *maxsize, int devtype, + uint64_t chipsize) { int ret; diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 33669da..552d4d6 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -484,8 +484,9 @@ int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); int del_mtd_partitions(struct mtd_info *); int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, - loff_t *maxsize, int devtype, int chipsize); + loff_t *maxsize, int devtype, uint64_t chipsize); int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, - loff_t *size, loff_t *maxsize, int devtype, int chipsize); + loff_t *size, loff_t *maxsize, int devtype, + uint64_t chipsize); #endif #endif /* __MTD_MTD_H__ */ -- 1.9.1

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