July 2015 - U-Boot

[U-Boot] [PATCH 0/4] lpc32xx: devkit3250 board update
by Vladimir Zapolskiy 16 Jul '15

16 Jul '15

This changeset improves support of Timll DevKit3250 board: * added LPC32xx MAC and SMSC RMII phy support, this dependends on - http://patchwork.ozlabs.org/patch/489100/ - http://patchwork.ozlabs.org/patch/489190/ - http://patchwork.ozlabs.org/patch/491419/ - http://patchwork.ozlabs.org/patch/491420/ * added GPIO, SPI, I2C support, works good, many thanks to Albert, * added LPC32xx SLC NAND driver, testing of 50 MiB data raw reading shows 1 MiB/s speed, the same change has been sent to the mailing list separately, here it is duplicated as a build dependency: - http://patchwork.ozlabs.org/patch/495247/ - http://patchwork.ozlabs.org/patch/495250/ * added an option to pass DTB to an operating system, * changed serial console to commonly used as default UART5, * boot delay is set to 1 for convenience, * extended predefined environment variables and reserved space on NAND, * added an option to build SPL image for the board, by default SPL downloads U-boot image from NAND (offset 0x40000, size 0x60000). Albert, from commit logs I noticed that WORK92105 has SLC NAND chip, but it is managed by MLC controller, if you have any plans to test LPC32xx SLC NAND driver from the series, please *be aware* of different OOB layouts, I found it is quite easy to screw up the chip, if SLC and MLC are interchanged, so that only "nand scrub" helps. FWIW this SLC NAND driver uses a default OOB layout, the same one is found in Linux LPC32xx SLC NAND driver. Vladimir Zapolskiy (4): spl: nand: simple: replace readb() with chip specific read_buf() nand: lpc32xx: add SLC NAND controller support lpc32xx: devkit3250: update of board configuration lpc32xx: devkit3250: add spl build support arch/arm/Kconfig | 1 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 + arch/arm/include/asm/arch-lpc32xx/clk.h | 2 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + board/timll/devkit3250/Makefile | 1 + board/timll/devkit3250/devkit3250.c | 31 ++++- board/timll/devkit3250/devkit3250_spl.c | 68 ++++++++++ configs/devkit3250_defconfig | 4 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_slc.c | 183 ++++++++++++++++++++++++++ drivers/mtd/nand/nand_spl_simple.c | 7 +- include/configs/devkit3250.h | 145 +++++++++++++++++++- 12 files changed, 442 insertions(+), 8 deletions(-) create mode 100644 board/timll/devkit3250/devkit3250_spl.c create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c -- 2.1.4

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[U-Boot] [PATCH] nand: lpc32xx: add SLC NAND controller support
by Vladimir Zapolskiy 16 Jul '15

16 Jul '15

The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz(a)mleia.com> Cc: Albert ARIBAUD <albert.u.boot(a)3adev.fr> --- arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 + arch/arm/include/asm/arch-lpc32xx/clk.h | 2 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_slc.c | 183 ++++++++++++++++++++++++++ 5 files changed, 193 insertions(+) create mode 100644 drivers/mtd/nand/lpc32xx_nand_slc.c diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index 5a453e3..b0287be 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -54,6 +54,12 @@ void lpc32xx_mlc_nand_init(void) writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); } +void lpc32xx_slc_nand_init(void) +{ + /* Enable SLC NAND interface */ + writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl); +} + void lpc32xx_i2c_init(unsigned int devnum) { /* Enable I2C interface */ diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 9449869..010211a 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -153,7 +153,9 @@ struct clk_pm_regs { #define CLK_DMA_ENABLE (1 << 0) /* NAND Clock Control Register bits */ +#define CLK_NAND_SLC (1 << 0) #define CLK_NAND_MLC (1 << 1) +#define CLK_NAND_SLC_SELECT (1 << 2) #define CLK_NAND_MLC_INT (1 << 5) /* SSP Clock Control Register bits */ diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index c3d890d..0845f83 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -12,6 +12,7 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); +void lpc32xx_slc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); void lpc32xx_ssp_init(void); #if defined(CONFIG_SPL_BUILD) diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index f3da70b..0813b54 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o +obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_NAND_MXC) += mxc_nand.o diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c new file mode 100644 index 0000000..c888dd6 --- /dev/null +++ b/drivers/mtd/nand/lpc32xx_nand_slc.c @@ -0,0 +1,183 @@ +/* + * LPC32xx SLC NAND flash controller driver + * + * (C) Copyright 2015 Vladimir Zapolskiy <vz(a)mleia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nand.h> +#include <asm/errno.h> +#include <asm/io.h> +#include <asm/arch/clk.h> +#include <asm/arch/sys_proto.h> + +struct lpc32xx_nand_slc_registers { + u32 data; + u32 addr; + u32 cmd; + u32 stop; + u32 ctrl; + u32 cfg; + u32 stat; + u32 int_stat; + u32 ien; + u32 isr; + u32 icr; + u32 tac; + u32 tc; + u32 ecc; + u32 dma_data; +}; + +/* CFG register */ +#define CFG_CE_LOW (1 << 5) +#define CFG_ECC_EN (1 << 3) + +/* CTRL register */ +#define CTRL_SW_RESET (1 << 2) +#define CTRL_ECC_CLEAR (1 << 1) + +/* STAT register */ +#define STAT_NAND_READY (1 << 0) + +/* INT_STAT register */ +#define INT_STAT_TC (1 << 1) +#define INT_STAT_RDY (1 << 0) + +/* TAC register bits, be aware of overflows */ +#define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28) +#define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24) +#define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20) +#define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16) +#define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12) +#define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8) +#define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4) +#define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0) + +static struct lpc32xx_nand_slc_registers __iomem *lpc32xx_nand_slc_registers + = (struct lpc32xx_nand_slc_registers __iomem *)SLC_NAND_BASE; + +static void lpc32xx_nand_init(void) +{ + uint32_t hclk = get_hclk_clk_rate(); + + /* Reset SLC NAND controller */ + writel(CTRL_SW_RESET, &lpc32xx_nand_slc_registers->ctrl); + + /* 8-bit bus, no DMA, no ECC, ordinary CE signal */ + writel(0, &lpc32xx_nand_slc_registers->cfg); + + /* Interrupts disabled and cleared */ + writel(0, &lpc32xx_nand_slc_registers->ien); + writel(INT_STAT_TC | INT_STAT_RDY, + &lpc32xx_nand_slc_registers->icr); + + /* Configure NAND flash timings */ + writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) | + TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | + TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | + TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | + TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) | + TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | + TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | + TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), + &lpc32xx_nand_slc_registers->tac); +} + +static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd); + + if (ctrl & NAND_NCE) + setbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW); + else + clrbits_le32(&lpc32xx_nand_slc_registers->cfg, CFG_CE_LOW); + + if (cmd == NAND_CMD_NONE) + return; + + if (ctrl & NAND_CLE) + writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->cmd); + else /* if (ctrl & NAND_ALE) */ + writel(cmd & 0xFF, &lpc32xx_nand_slc_registers->addr); +} + +static int lpc32xx_nand_dev_ready(struct mtd_info *mtd) +{ + return readl(&lpc32xx_nand_slc_registers->stat) & STAT_NAND_READY; +} + +static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + while (len-- > 0) + *buf++ = (uint8_t)readl(&lpc32xx_nand_slc_registers->data); +} + +static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) +{ + return (uint8_t)readl(&lpc32xx_nand_slc_registers->data); +} + +static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + while (len-- > 0) + writel((uint32_t)*buf++, &lpc32xx_nand_slc_registers->data); +} + +static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte) +{ + writel((uint32_t)byte, &lpc32xx_nand_slc_registers->data); +} + +/* + * LPC32xx has only one SLC NAND controller, don't utilize + * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function + * both in SPL NAND and U-boot images. + */ +int board_nand_init(struct nand_chip *lpc32xx_chip) +{ + lpc32xx_chip->IO_ADDR_R = &lpc32xx_nand_slc_registers->data; + lpc32xx_chip->IO_ADDR_W = &lpc32xx_nand_slc_registers->data; + + lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl; + lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready; + + /* + * Hardware ECC calculation is not supported by the driver, because it + * requires DMA support, see Note after SLC_ECC register description + */ + lpc32xx_chip->ecc.mode = NAND_ECC_SOFT; + + /* + * The implementation of these functions is quite common, but + * they MUST be defined, because access to data register + * is strictly 32-bit aligned. + */ + lpc32xx_chip->read_buf = lpc32xx_read_buf; + lpc32xx_chip->read_byte = lpc32xx_read_byte; + lpc32xx_chip->write_buf = lpc32xx_write_buf; + lpc32xx_chip->write_byte = lpc32xx_write_byte; + + /* + * Use default ECC layout, but these values are predefined + * for both small and large page NAND flash devices. + */ + lpc32xx_chip->ecc.size = 256; + lpc32xx_chip->ecc.bytes = 3; + lpc32xx_chip->ecc.strength = 1; + +#if defined(CONFIG_SPL_BUILD) + lpc32xx_chip->options |= NAND_SKIP_BBTSCAN; +#endif + +#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT) + lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH; +#endif + + /* Initialize NAND interface */ + lpc32xx_nand_init(); + + return 0; +} -- 2.1.4

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[U-Boot] PCIe driver for a new Freescale ARM64 SOC
by Aurelian Floricica Voicu 16 Jul '15

16 Jul '15

Hi! I'm with Freescale and we are currently working on bringing up a ARM64 SOC platform. The PCIe module is similar with the one used by the iMX family, being a Synopsys IP. However there are many differences in terms of the SOC integration (clocking, pin muxing, control registers) plus an additional internal DMA engine. I would like to address a question about the U-Boot driver approach. What would be an acceptable solution if we plan to make this driver upstreamable : 1. Use existing pcie-imx.c driver and parameterize according to the SOC platform 2. Create another driver file specific for the new family of SOCs Thank you! Aurelian Floricica

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[U-Boot] [RFC] lib/fdtdec: Fix compiling warning for debug
by York Sun 16 Jul '15

16 Jul '15

fdt_addr_t and fdt_size_t can be either 64-bit or 32-bit, depending on the architecture. Change the type to phys_addr_t and phys_size_t. Signed-off-by: York Sun <yorksun(a)freescale.com> --- include/fdtdec.h | 7 +++---- lib/fdtdec.c | 4 ++-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/include/fdtdec.h b/include/fdtdec.h index 2323603..c61734c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -14,6 +14,7 @@ * changes to support FDT are minimized. */ +#include <linux/types.h> #include <libfdt.h> #include <pci.h> @@ -21,15 +22,13 @@ * A typedef for a physical address. Note that fdt data is always big * endian even on a litle endian machine. */ +typedef phys_addr_t fdt_addr_t; +typedef phys_size_t fdt_size_t; #ifdef CONFIG_PHYS_64BIT -typedef u64 fdt_addr_t; -typedef u64 fdt_size_t; #define FDT_ADDR_T_NONE (-1ULL) #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) #define fdt_size_to_cpu(reg) be64_to_cpu(reg) #else -typedef u32 fdt_addr_t; -typedef u32 fdt_size_t; #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be32_to_cpu(reg) #define fdt_size_to_cpu(reg) be32_to_cpu(reg) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9877849..1f22fab 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -102,8 +102,8 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, size = (fdt_size_t *)((char *)cell + sizeof(fdt_addr_t)); *sizep = fdt_size_to_cpu(*size); - debug("addr=%08lx, size=%08x\n", - (ulong)addr, *sizep); + debug("addr=%pa, size=%zx\n", + &addr, *sizep); } else { debug("%08lx\n", (ulong)addr); } -- 1.7.9.5

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[U-Boot] [PATCH 0/3] configs: make keystone2 config to start using arm_v7_common header
by Nishanth Menon 16 Jul '15

16 Jul '15

For legacy reasons, keystone2 had kind of stayed completely seperated from the rest of the TI SoC families. This makes no sense since there are a lot of common definitions that can be reused between all SoC configuration allowing for a consistent user experience. So make keystone2 follow the rest of the TI SoCs based on OMAP architecture as well. Test log: K2H: http://pastebin.ubuntu.com/11888160/ (using https://patchwork.ozlabs.org/patch/440665/) I have no other platform to verify on. Series based on master 4905dfc65d9a Merge branch 'master' of git://git.denx.de/u-boot-spi Nishanth Menon (3): configs: split ti_armv7_common into a omap generic header configs: rename ks2_evm into ti_armv7_keystone2 configs: ti_armv7_keystone2: start using armv7_common include/configs/am43xx_evm.h | 2 +- include/configs/k2e_evm.h | 4 +- include/configs/k2hk_evm.h | 4 +- include/configs/k2l_evm.h | 4 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_common.h | 31 ++++---------- .../configs/{ks2_evm.h => ti_armv7_keystone2.h} | 50 +++++++--------------- include/configs/ti_armv7_omap.h | 49 +++++++++++++++++++++ include/configs/ti_omap3_common.h | 2 +- include/configs/ti_omap4_common.h | 2 +- include/configs/ti_omap5_common.h | 2 +- 11 files changed, 81 insertions(+), 71 deletions(-) rename include/configs/{ks2_evm.h => ti_armv7_keystone2.h} (90%) create mode 100644 include/configs/ti_armv7_omap.h -- 2.1.4

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[U-Boot] Please pull u-boot-x86
by Simon Glass 16 Jul '15

16 Jul '15

Hi Tom, Here's the first pull request for x86. It includes fixes and improvements with PCI, multi-core init, Intel FSP init and adds graphics support for crownbay. The following changes since commit f4815763b410d8657f6f617067a1d53024b05220: RFC: Deprecate MAKEALL (2015-07-14 13:50:16 -0400) are available in the git repository at: git://git.denx.de/u-boot-x86.git for you to fetch changes up to f110da9984c0aa0aba9e1c4178b67b7abecf7e8d: pci: Disable expansion ROM address decoding when signature check fails (2015-07-14 18:03:20 -0600) ---------------------------------------------------------------- Bin Meng (42): x86: Add Kconfig options to be used by arch/x86/cpu/config.mk x86: fsp: Load GDT before calling FspInitEntry x86: fsp: Move FspInitEntry call to board_init_f() dm: cpu: Fix undefined ENOSYS build error dm: cpu: Test against cpu_ops->get_info in cpu_get_info() x86: dm: Clean up cpu drivers x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP x86: kconfig: Fix minor nits in MAX_CPUS dm: cpu: Add a new get_count method to cpu uclass x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS x86: Move MP initialization codes into a common place x86: Move lapic_setup() call into init_bsp() x86: Clean up lapic codes x86: crownbay: Add MP initialization dm: rtc: Support mc146818 driver in driver model cmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C x86: crownbay: Enable DM RTC support x86: queensbay: Correct Topcliff device irqs x86: Write correct bus number for the irq router x86: Ignore function number when writing PIRQ routing table x86: Reduce PIRQ routing table size x86: Clean up ioapic header file x86: Add I/O APIC register access routines x86: Remove inline for lapic access routines x86: Add MultiProcessor (MP) table APIs x86: Generate a valid MultiProcessor (MP) table x86: Update README.x86 for SMP support x86: crownbay: Enable writing MP table x86: queensbay: Change PCIe root ports' interrupt routing video: vesa_fb: Look up VGA device by class instead of id x86: Setup fixed range MTRRs for legacy regions x86: queensbay: Change CPU_ADDR_BITS to 32 x86: cmd_mtrr: Improve MTRR list information x86: Move VGA option rom macros to Kconfig x86: Remove MARK_GRAPHICS_MEM_WRCOMB x86: crownbay: Enable graphics support x86: Configure VESA parameters before loading Linux kernel tools: ifdtool: Write correct offset on 32-bit machine x86: Adjust config option order in defconfig for Crown Bay and Minnowmax drivers: block: Remove the ata_piix driver pci: Configure expansion ROM during auto config process pci: Disable expansion ROM address decoding when signature check fails Jian Luo (3): x86: bios: Synchronize stack between real and protected mode x86: bios: Allow pci config read/write to host bridge in int1a_handler video: Add 32-bit color depth support for VBE Simon Glass (12): spi: sf: Print the error code on failure dm: spi: Correct minor nits in ICH driver dm: pci: Use the correct hose when configuring devices dm: pci: Correct bus number when scanning sub-buses dm: spi: Correct status register access width dm: spi: Correct BIOS protection logic for ICH9 dm: spi: Enable environment for minnowmax x86: Add ROM image description for minnowmax x86: pci: Tidy up the generic x86 PCI driver dm: x86: minnowmax: Move PCI to use driver model dm: x86: baytrail: Correct PCI region 3 when driver model is used x86: Add binary blob checksums for Minnowboard MAX Tom Rini (1): builderthread.py: Keep 'SPL' Makefile | 4 +- arch/x86/Kconfig | 78 ++++++--- arch/x86/cpu/Makefile | 4 +- arch/x86/cpu/baytrail/Makefile | 1 - arch/x86/cpu/baytrail/cpu.c | 101 +++-------- arch/x86/cpu/baytrail/pci.c | 46 ------ arch/x86/cpu/config.mk | 6 +- arch/x86/cpu/coreboot/pci.c | 22 --- arch/x86/cpu/cpu.c | 108 +++++++++--- arch/x86/cpu/cpu_x86.c | 76 +++++++++ arch/x86/cpu/ioapic.c | 21 +++ arch/x86/cpu/irq.c | 68 ++++++-- arch/x86/cpu/ivybridge/Kconfig | 1 - arch/x86/cpu/ivybridge/model_206ax.c | 2 +- arch/x86/cpu/lapic.c | 153 ++++++++++++++--- arch/x86/cpu/mp_init.c | 47 ++++-- arch/x86/cpu/queensbay/Kconfig | 4 + arch/x86/cpu/queensbay/tnc.c | 13 +- arch/x86/cpu/start.S | 6 +- arch/x86/cpu/start16.S | 5 +- arch/x86/dts/crownbay.dts | 65 ++++++-- arch/x86/dts/minnowmax.dts | 10 ++ arch/x86/dts/rtc.dtsi | 6 + arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 14 +- arch/x86/include/asm/cpu.h | 14 -- arch/x86/include/asm/cpu_x86.h | 34 ++++ arch/x86/include/asm/ioapic.h | 46 +++--- arch/x86/include/asm/lapic.h | 229 +++++++------------------ arch/x86/include/asm/lapic_def.h | 101 ----------- arch/x86/include/asm/mp.h | 1 - arch/x86/include/asm/mpspec.h | 444 +++++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 27 +-- arch/x86/include/asm/tables.h | 14 ++ arch/x86/include/asm/u-boot-x86.h | 10 ++ arch/x86/include/asm/zimage.h | 1 + arch/x86/lib/Makefile | 1 + arch/x86/lib/bios_asm.S | 23 +++ arch/x86/lib/bios_interrupts.c | 10 +- arch/x86/lib/cmd_mtrr.c | 3 +- arch/x86/lib/fsp/fsp_car.S | 26 +-- arch/x86/lib/fsp/fsp_common.c | 8 + arch/x86/lib/fsp/fsp_support.c | 3 + arch/x86/lib/mpspec.c | 382 ++++++++++++++++++++++++++++++++++++++++++ arch/x86/lib/tables.c | 19 +++ arch/x86/lib/zimage.c | 2 + board/google/chromebook_link/Kconfig | 1 - board/google/chromebox_panther/Kconfig | 1 - common/board_f.c | 3 + common/cmd_cpu.c | 1 + common/cmd_date.c | 12 +- common/cmd_sf.c | 8 +- configs/chromebook_link_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/crownbay_defconfig | 9 + configs/minnowmax_defconfig | 2 + doc/README.x86 | 50 +++++- drivers/block/Makefile | 1 - drivers/block/ata_piix.c | 717 ------------------------------------------------------------------------------- drivers/block/ata_piix.h | 71 -------- drivers/cpu/cpu-uclass.c | 15 +- drivers/pci/pci-uclass.c | 16 +- drivers/pci/pci_auto.c | 48 +++--- drivers/pci/pci_common.c | 6 + drivers/pci/pci_rom.c | 42 ++++- drivers/pci/pci_x86.c | 13 +- drivers/rtc/mc146818.c | 312 ++++++++++++++++++++++------------ drivers/spi/ich.c | 20 ++- drivers/video/vesa_fb.c | 16 +- include/asm-generic/global_data.h | 1 + include/configs/crownbay.h | 14 +- include/configs/minnowmax.h | 9 +- include/configs/x86-chromebook.h | 3 - include/cpu.h | 16 ++ include/pci.h | 19 ++- include/vbe.h | 4 +- tools/buildman/builderthread.py | 2 +- tools/ifdtool.c | 2 +- 77 files changed, 2072 insertions(+), 1623 deletions(-) delete mode 100644 arch/x86/cpu/baytrail/pci.c create mode 100644 arch/x86/cpu/cpu_x86.c create mode 100644 arch/x86/cpu/ioapic.c create mode 100644 arch/x86/dts/rtc.dtsi create mode 100644 arch/x86/include/asm/cpu_x86.h delete mode 100644 arch/x86/include/asm/lapic_def.h create mode 100644 arch/x86/include/asm/mpspec.h create mode 100644 arch/x86/lib/mpspec.c delete mode 100644 drivers/block/ata_piix.c delete mode 100644 drivers/block/ata_piix.h Regards, Simon

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[U-Boot] debug warning
by York Sun 16 Jul '15

16 Jul '15

Simon, Did it happen to you with this warning? lib/fdtdec.c:108:4: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3 has type ‘fdt_size_t’ [-Wformat=] debug("addr=%08lx, size=%08x\n", ^ I think when we have 64-bit physical address, as defined in fdtdec.h, this debug statement needs to be changed. I am thinking to change the typedef fdt_addr_t to phys_addr_t, and fdt_size_t to phys_size_t. What do you say? York

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[U-Boot] [PATCH] powerpc/t4080: update t4160/t4080 serdes
by Shengzhou Liu 16 Jul '15

16 Jul '15

Update t4160/t4080 serdes according to latest reference manual rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu(a)freescale.com> --- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index 74c4c81..c0c952b 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -363,42 +363,42 @@ static const struct serdes_config serdes2_cfg_tbl[] = { SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} }, {37, {NONE, NONE, QSGMII_FM2_B, NONE, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, QSGMII_FM2_A, NONE, NONE} }, {38, {NONE, NONE, QSGMII_FM2_B, NONE, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, QSGMII_FM2_A, NONE, NONE} }, {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, QSGMII_FM2_A, NONE, NONE} }, {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, QSGMII_FM2_A, NONE, NONE} }, {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, QSGMII_FM2_A, NONE, NONE} }, {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, QSGMII_FM2_A, NONE, NONE} }, {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, QSGMII_FM2_A, NONE, NONE} }, {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6, SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9, - NONE, QSGMII_FM1_A, NONE, NONE} }, + NONE, QSGMII_FM2_A, NONE, NONE} }, {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, XAUI_FM2_MAC9, NONE, NONE, NONE, NONE} }, {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, - NONE, NONE, NONE, NONE} }, + NONE, NONE, QSGMII_FM2_A, NONE} }, {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, HIGIG_FM2_MAC9, NONE, NONE, NONE, NONE} }, -- 2.1.0.27.g96db324

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Re: [U-Boot] net.c: question regarding commit: fd3056337e6fcc140f400e11edd33f6f1cb37de1
by Hannes Schmelzer 15 Jul '15

15 Jul '15

hi joe, maybe my email got lost ... best regards, Hannes On 2015-06-22 14:23, Hannes Schmelzer wrote: > Hi joe, > > you did introduce callbacks on setting up ip,dns, ... in net.c > > Why it did become necessary to do following ? > > if (flags & H_PROGRAMMATIC) > return 0; > > I have actually trouble with this, because my code in > board/BuR/kwb/board.c doesn't work anymore as expected. > > /* setup default IP, in case if there is nothing in environment */ > if (!getenv("ipaddr")) { > setenv("ipaddr", "192.168.60.1"); > setenv("netmask", "255.255.255.0"); > setenv("serverip", "192.168.60.254"); > setenv("gatewayip", "192.168.60.254"); > puts("net: had no IP! made default setup.\n"); > } > > Purpose of this was/is to setup a default ip-address if nothing in > environment has been set yet. > > do you (or somebody else) have an idea how to work around this ? > > many thanks and best regards, > Hannes >

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[U-Boot] [PATCH] arm: mvebu: Call timer_init early before PHY and DDR init
by Stefan Roese 15 Jul '15

15 Jul '15

Without calling timer_init(), the xdelay() functions return immediately. We need to call timer_init() early, so that these functions work and the PHY and DDR init code works correctly. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Anton Schubert <anton.schubert(a)gmx.de> Cc: Luka Perkov <luka.perkov(a)sartura.hr> --- arch/arm/mach-mvebu/spl.c | 2 ++ arch/arm/mach-mvebu/timer.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 2df25aa..e65f6ca 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -35,6 +35,8 @@ void board_init_f(ulong dummy) preloader_console_init(); + timer_init(); + /* First init the serdes PHY's */ serdes_phy_config(); diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c index 40c4bc2..c516c41 100644 --- a/arch/arm/mach-mvebu/timer.c +++ b/arch/arm/mach-mvebu/timer.c @@ -41,6 +41,8 @@ #define timestamp gd->arch.tbl #define lastdec gd->arch.lastinc +static int init_done; + /* Timer reload and current value registers */ struct kwtmr_val { u32 reload; /* Timer reload reg */ @@ -112,6 +114,11 @@ void __udelay(unsigned long usec) */ int timer_init(void) { + /* Only init the timer once */ + if (init_done) + return 0; + init_done = 1; + /* load value into timer */ writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); -- 2.4.5

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